], ['hostid', Sim_Attr_Required, 'i', 'The hostid of the machine.'], [ 'mac_address', Sim_Attr_Required, 's', 'The main MAC address is the machine.' ], [ 'rtc_time', Sim_Attr_Required, 's', 'The date and time of the Real-Time clock.' ], [ 'memory_megs', Sim_Attr_Pseudo, 'i', 'The amount of RAM in mega-bytes in the machine.' ]] register_component_class(taco_system_component, attrs, top_level=True) register_nvram_commands(taco_system_component.classname) attrs += [[ 'num_cpus', Sim_Attr_Required, 'i', 'Number of processors in the sytem.' ]] register_component_class(enchilada_system_component, attrs, top_level=True) register_nvram_commands(enchilada_system_component.classname) ### Sun ALi MD1535D South Bridge class south_bridge_sun_md1535d_component(south_bridge_md1535d_component): classname = 'south-bridge-sun-md1535d' basename = 'south_bridge' description = ('The "south-bridge-sun-md1535d" component represents the '
'empty_ok' : True, 'hotplug' : False, 'multi' : False} attrs = [['cpu_frequency', Sim_Attr_Required, 'i', 'Processor frequency in MHz.'], ['hostid', Sim_Attr_Required, 'i', 'The hostid of the machine.'], ['mac_address', Sim_Attr_Required, 's', 'The main MAC address is the machine.'], ['rtc_time', Sim_Attr_Required, 's', 'The date and time of the Real-Time clock.'], ['memory_megs', Sim_Attr_Pseudo, 'i', 'The amount of RAM in mega-bytes in the machine.']] register_component_class(taco_system_component, attrs, top_level = True) register_nvram_commands(taco_system_component.classname) attrs += [['num_cpus', Sim_Attr_Required, 'i', 'Number of processors in the sytem.']] register_component_class(enchilada_system_component, attrs, top_level = True) register_nvram_commands(enchilada_system_component.classname) ### Sun ALi MD1535D South Bridge class south_bridge_sun_md1535d_component(south_bridge_md1535d_component): classname = 'south-bridge-sun-md1535d' basename = 'south_bridge' description = ('The "south-bridge-sun-md1535d" component represents the '
def disconnect_serial(self, connector): exec('self.o.%s.link = None' % connector) exec('self.o.%s.console = None' % connector) def get_clock(self): return self.o.cpu[0] def get_processors(self): return [x for x in self.o.cpu if x] def instantiation_done(self): component_object.instantiation_done(self) self.o.nvram_image.iface.image.set_persistent(self.o.nvram_image) # TODO: write_idprom_to_nvram(self.obj, self.hostid, self.mac) register_component_class( niagara_simple_component, [['cpu_frequency', Sim_Attr_Required, 'i', 'Processor frequency in MHz.'], ['num_cores', Sim_Attr_Required, 'i', 'Number of processor cores in the system. 1 or 8.'], ['strands_per_core', Sim_Attr_Required, 'i', 'Number of active processor strands per core in the system. ' '1, 2 or 4. There are always 4 strands created.'], ['rtc_time', Sim_Attr_Required, 's', 'The date and time of the Real-Time clock.']], top_level = True) register_nvram_commands(niagara_simple_component.classname, 0x0d7b17d7, False)