def __init__(self, platform, firmware_ram_size=0x10000, firmware_filename=None, **kwargs): clk_freq = 75 * 1000000 SDRAMSoC.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, sdram_controller_settings=LASMIconSettings( l2_size=32, with_bandwidth=True), **kwargs) self.submodules.crg = _CRG(platform, clk_freq) self.submodules.dna = dna.DNA() self.submodules.git_info = git_info.GitInfo() self.submodules.platform_info = platform_info.PlatformInfo( "atlys", self.__class__.__name__[:8]) self.submodules.firmware_ram = firmware.FirmwareROM( firmware_ram_size, firmware_filename) self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size) self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"]) if not self.integrated_main_ram_size: self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY( platform.request("ddram"), P3R1GE4JGF(self.clk_freq), rd_bitslip=0, wr_bitslip=4, dqs_ddr_alignment="C0") self.comb += [ self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb), ] self.register_sdram_phy(self.ddrphy) self.submodules.spiflash = spiflash.SpiFlash( platform.request("spiflash4x"), dummy=platform.spiflash_read_dummy_bits, div=platform.spiflash_clock_div) self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size) self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size) self.flash_boot_address = self.mem_map[ "spiflash"] + platform.gateware_size self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=platform.gateware_size) self.specials += Keep(self.crg.cd_sys.clk) platform.add_platform_command(""" NET "{sys_clk}" TNM_NET = "GRPsys_clk"; """, sys_clk=self.crg.cd_sys.clk)
def __init__(self, platform, firmware_ram_size=0xa000, firmware_filename=None, **kwargs): clk_freq = (83 + Fraction(1, 3)) * 1000 * 1000 SDRAMSoC.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, sdram_controller_settings=LASMIconSettings( l2_size=32, with_bandwidth=True), **kwargs) platform.add_extension(PipistrelloCustom) self.submodules.crg = _CRG(platform, clk_freq) self.submodules.dna = dna.DNA() self.submodules.git_info = git_info.GitInfo() self.submodules.platform_info = platform_info.PlatformInfo( "pipistrello"[:8], self.__class__.__name__[:8]) self.submodules.fx2_reset = gpio.GPIOOut(platform.request("fx2_reset")) self.submodules.fx2_hack = i2c_hack.I2CShiftReg( platform.request("fx2_hack")) self.submodules.firmware_ram = firmware.FirmwareROM( firmware_ram_size, firmware_filename) self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size) self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"]) if not self.integrated_main_ram_size: self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY( platform.request("ddram"), MT46H32M16(self.clk_freq), rd_bitslip=1, wr_bitslip=3, dqs_ddr_alignment="C1") self.comb += [ self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb), ] self.register_sdram_phy(self.ddrphy) self.submodules.spiflash = spiflash.SpiFlash( platform.request("spiflash4x"), dummy=platform.spiflash_read_dummy_bits, div=platform.spiflash_clock_div) self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size) self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size) self.flash_boot_address = self.mem_map[ "spiflash"] + platform.gateware_size self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=platform.gateware_size)
def __init__(self, platform, **kwargs): dict_set_max(kwargs, 'integrated_rom_size', 0x10000) if kwargs.get('cpu_type', None) == 'mor1kx': dict_set_max(kwargs, 'integrated_rom_size', 0x10000) else: dict_set_max(kwargs, 'integrated_rom_size', 0x8000) dict_set_max(kwargs, 'integrated_sram_size', 0x8000) dict_set_max(kwargs, 'firmware_ram_size', 0x10000) if 'firmware_filename' not in kwargs: kwargs[ 'firmware_filename'] = "build/sim_{}_{}/software/firmware/firmware.fbi".format( self.__class__.__name__.lower()[:-3], kwargs.get('cpu_type', 'lm32')) clk_freq = int((1 / (platform.default_clk_period)) * 1000000000) SoCSDRAM.__init__(self, platform, clk_freq, with_uart=False, **kwargs) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) self.submodules.uart_phy = uart.RS232PHYModel( platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) # firmware self.submodules.firmware_ram = firmware.FirmwareROM( firmware_ram_size, firmware_filename) self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size) self.flash_boot_address = self.mem_map["firmware_ram"] define_flash_constants(self) # sdram sdram_module = IS42S16160(self.clk_freq, "1:1") phy_settings = PhySettings(memtype="SDR", dfi_databits=1 * 32, nphases=1, rdphase=0, wrphase=0, rdcmdphase=0, wrcmdphase=0, cl=2, read_latency=4, write_latency=0) self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings) controller_settings = ControllerSettings(with_refresh=False) self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) # reduce memtest size to speed up simulation self.add_constant("MEMTEST_DATA_SIZE", 1024) self.add_constant("MEMTEST_ADDR_SIZE", 1024) self.add_constant("SIMULATION", 1)
def __init__(self, firmware_ram_size=0x10000, firmware_filename="firmware/firmware.bin", **kwargs): platform = sim.Platform() SoCSDRAM.__init__(self, platform, clk_freq=int((1/(platform.default_clk_period))*1000000000), integrated_rom_size=0x8000, integrated_sram_size=0x8000, with_uart=False, **kwargs) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) # firmware self.submodules.firmware_ram = firmware.FirmwareROM(firmware_ram_size, firmware_filename) self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size) self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"]) # sdram sdram_module = IS42S16160(self.clk_freq, "1:1") phy_settings = PhySettings( memtype="SDR", dfi_databits=1*32, nphases=1, rdphase=0, wrphase=0, rdcmdphase=0, wrcmdphase=0, cl=2, read_latency=4, write_latency=0 ) self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings) controller_settings = ControllerSettings(with_refresh=False) self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) # reduce memtest size to speed up simulation self.add_constant("MEMTEST_DATA_SIZE", 1024) self.add_constant("MEMTEST_ADDR_SIZE", 1024) self.add_constant("SIMULATION", 1) self.submodules.video_out = VideoOutCore(self.sdram.crossbar.get_port()) self.submodules.vga = VGAModel(platform.request("vga")) self.comb += self.video_out.source.connect(self.vga.sink)
def __init__(self, platform, firmware_ram_size=0x10000, firmware_filename=None, **kwargs): clk_freq = 50*1000000 SDRAMSoC.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, sdram_controller_settings=LASMIconSettings(l2_size=32, with_bandwidth=True), with_uart=False, **kwargs) self.submodules.crg = _CRG(platform, clk_freq) self.submodules.dna = dna.DNA() self.submodules.git_info = git_info.GitInfo() self.submodules.platform_info = platform_info.PlatformInfo("opsis", self.__class__.__name__[:8]) fx2_uart_pads = platform.request("serial_fx2") sd_card_uart_pads = platform.request("serial_sd_card") uart_pads = UARTSharedPads() self.comb += [ # TX fx2_uart_pads.tx.eq(uart_pads.tx), sd_card_uart_pads.tx.eq(uart_pads.tx), # RX uart_pads.rx.eq(fx2_uart_pads.rx & sd_card_uart_pads.rx) ] self.submodules.uart_phy = UARTPHY(uart_pads, self.clk_freq, 115200) self.submodules.uart = uart.UART(self.uart_phy) # self.submodules.opsis_eeprom_i2c = i2c.I2C(platform.request("opsis_eeprom")) self.submodules.fx2_reset = gpio.GPIOOut(platform.request("fx2_reset")) self.submodules.fx2_hack = i2c_hack.I2CShiftReg(platform.request("opsis_eeprom")) self.submodules.tofe_eeprom_i2c = i2c.I2C(platform.request("tofe_eeprom")) self.submodules.firmware_ram = firmware.FirmwareROM(firmware_ram_size, firmware_filename) self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size) self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"]) if not self.integrated_main_ram_size: self.submodules.ddrphy = s6ddrphy.S6QuarterRateDDRPHY(platform.request("ddram"), MT41J128M16(self.clk_freq), rd_bitslip=0, wr_bitslip=4, dqs_ddr_alignment="C0") self.comb += [ self.ddrphy.clk8x_wr_strb.eq(self.crg.clk8x_wr_strb), self.ddrphy.clk8x_rd_strb.eq(self.crg.clk8x_rd_strb), ] self.register_sdram_phy(self.ddrphy) self.submodules.spiflash = spiflash.SpiFlash( platform.request("spiflash4x"), dummy=platform.spiflash_read_dummy_bits, div=platform.spiflash_clock_div) self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size) self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size) self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=platform.gateware_size) self.specials += Keep(self.crg.cd_sys.clk) platform.add_platform_command(""" NET "{sys_clk}" TNM_NET = "GRPsys_clk"; """, sys_clk=self.crg.cd_sys.clk)
def __init__(self, platform, ddram="ddram_32", with_cpu=False): clk_freq = int(125e6) SoCSDRAM.__init__(self, platform, clk_freq, cpu_type="lm32" if with_cpu else None, integrated_rom_size=0x8000 if with_cpu else 0, integrated_sram_size=0x8000 if with_cpu else 0, csr_data_width=8 if with_cpu else 32, l2_size=128, with_uart=with_cpu, uart_stub=False, ident="Sayma AMC SDRAM Test Design " + _build_version(), with_timer=with_cpu ) self.submodules.crg = _CRG(platform) if not with_cpu: self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)) self.add_wb_master(self.cpu_or_bridge.wishbone) self.crg.cd_sys.clk.attr.add("keep") platform.add_period_constraint(self.crg.cd_sys.clk, 8.0) # firmware firmware_ram_size = 0x10000 firmware_filename = "firmware/firmware.bin" self.submodules.firmware_ram = firmware.FirmwareROM(firmware_ram_size, firmware_filename) self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size) self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"]) # sdram self.submodules.ddrphy = kusddrphy.KUSDDRPHY(platform.request(ddram)) sdram_module = MT41J256M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings) # sdram bist if not with_cpu: generator_user_port = self.sdram.crossbar.get_port(mode="write") self.submodules.generator = LiteDRAMBISTGenerator( generator_user_port, random=True) checker_user_port = self.sdram.crossbar.get_port(mode="read") self.submodules.checker = LiteDRAMBISTChecker( checker_user_port, random=True) # leds led_counter = Signal(32) self.sync += led_counter.eq(led_counter + 1) self.comb += [ platform.request("user_led", 0).eq(led_counter[26]), platform.request("user_led", 1).eq(led_counter[27]), platform.request("user_led", 2).eq(led_counter[28]), platform.request("user_led", 3).eq(led_counter[29]) ] # analyzer if not with_cpu: dfi_phase_groups = [] for i in range(4): dfi_phase_group = [ self.ddrphy.dfi.phases[i].address, self.ddrphy.dfi.phases[i].bank, self.ddrphy.dfi.phases[i].ras_n, self.ddrphy.dfi.phases[i].cas_n, self.ddrphy.dfi.phases[i].we_n, self.ddrphy.dfi.phases[i].cs_n, self.ddrphy.dfi.phases[i].cke, self.ddrphy.dfi.phases[i].odt, self.ddrphy.dfi.phases[i].reset_n, self.ddrphy.dfi.phases[i].wrdata_en, self.ddrphy.dfi.phases[i].wrdata_mask, self.ddrphy.dfi.phases[i].wrdata, self.ddrphy.dfi.phases[i].rddata, self.ddrphy.dfi.phases[i].rddata_valid ] dfi_phase_groups.append(dfi_phase_group) analyzer_signals = { 0 : dfi_phase_groups[0], 1 : dfi_phase_groups[1], 2 : dfi_phase_groups[2], 3 : dfi_phase_groups[3] } if not with_cpu: self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 64)