def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.check_lvsdrc = False
OPTS.spice_name="" # Unset to use any simulator
OPTS.analytical_delay = False
OPTS.trim_netlist = True
# This is a hack to reload the characterizer __init__ with the spice version
import characterizer
reload(characterizer)
from characterizer import lib
if not OPTS.spice_exe:
debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
import sram
debug.info(1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank")
s = sram.sram(word_size=2,
num_words=16,
num_banks=1,
name="sram_2_16_1_{0}".format(OPTS.tech_name))
OPTS.check_lvsdrc = True
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
lib.lib(out_dir=OPTS.openram_temp, sram=s, sp_file=tempspice, use_model=False)
# get all of the .lib files generated
files = os.listdir(OPTS.openram_temp)
nametest = re.compile("\.lib$", re.IGNORECASE)
lib_files = filter(nametest.search, files)
# and compare them with the golden model
for filename in lib_files:
newname = filename.replace(".lib","_pruned.lib")
libname = "{0}/{1}".format(OPTS.openram_temp,filename)
golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),newname)
self.isapproxdiff(libname,golden,0.40)
OPTS.analytical_delay = True
reload(characterizer)
globals.end_openram()
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
OPTS.spice_name = "hspice"
OPTS.analytical_delay = False
OPTS.netlist_only = True
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import setup_hold
import sram
import tech
slews = [tech.spice["rise_time"] * 2]
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0],
OPTS.temperatures[0])
sh = setup_hold(corner)
data = sh.analyze(slews, slews)
#print data
if OPTS.tech_name == "freepdk45":
golden_data = {
'hold_times_HL': [-0.0158691],
'hold_times_LH': [-0.0158691],
'setup_times_HL': [0.026855499999999997],
'setup_times_LH': [0.032959]
}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {
'hold_times_HL': [-0.0805664],
'hold_times_LH': [-0.11718749999999999],
'setup_times_HL': [0.16357419999999998],
'setup_times_LH': [0.1757812]
}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results
self.assertTrue(len(data.keys()) == len(golden_data.keys()))
self.assertTrue(self.check_golden_data(data, golden_data, 0.25))
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
# Use the 2 port cell since it is usually bigger/easier
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(1, "Port address 16 rows")
a = factory.create("port_address", cols=16, rows=16)
self.local_check(a)
debug.info(1, "Port address 256 rows")
a = factory.create("port_address", cols=256, rows=256)
self.local_check(a)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
for layer_stack in [("metal1", "via1", "metal2"), ("poly", "contact", "metal1")]:
stack_name = ":".join(map(str, layer_stack))
# Check single 1 x 1 contact"
debug.info(2, "1 x 1 {} test".format(stack_name))
c = factory.create(module_type="contact", layer_stack=layer_stack, dimensions=(1, 1))
self.local_drc_check(c)
# Check single 1 x 1 contact"
debug.info(2, "1 x 1 {} test".format(stack_name))
c = factory.create(module_type="contact", layer_stack=layer_stack, dimensions=(1, 1), directions=("H","V"))
self.local_drc_check(c)
# Check single x 1 contact"
debug.info(2, "1 x 1 {} test".format(stack_name))
c = factory.create(module_type="contact", layer_stack=layer_stack, dimensions=(1, 1), directions=("H","H"))
self.local_drc_check(c)
# Check single 1 x 1 contact"
debug.info(2, "1 x 1 {} test".format(stack_name))
c = factory.create(module_type="contact", layer_stack=layer_stack, dimensions=(1, 1), directions=("V","V"))
self.local_drc_check(c)
# check vertical array with one in the middle and two ends
debug.info(2, "1 x 3 {} test".format(stack_name))
c = factory.create(module_type="contact", layer_stack=layer_stack, dimensions=(1, 3))
self.local_drc_check(c)
# check horizontal array with one in the middle and two ends
debug.info(2, "3 x 1 {} test".format(stack_name))
c = factory.create(module_type="contact", layer_stack=layer_stack, dimensions=(3, 1))
self.local_drc_check(c)
# check 3x3 array for all possible neighbors
debug.info(2, "3 x 3 {} test".format(stack_name))
c = factory.create(module_type="contact", layer_stack=layer_stack, dimensions=(3, 3))
self.local_drc_check(c)
globals.end_openram()
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
from sram_config import sram_config
c = sram_config(word_size=32,
write_size=8,
num_words=1024,
num_banks=1)
c.recompute_sizes()
debug.info(
1, "Layout test for {}rw,{}r,{}w sram "
"with {} bit words, {} words, {} bit writes, {} words per "
"row, {} banks".format(OPTS.num_rw_ports, OPTS.num_r_ports,
OPTS.num_w_ports, c.word_size, c.num_words,
c.write_size, c.words_per_row, c.num_banks))
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
globals.end_openram()
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
OPTS.use_pex = True
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import setup_hold
if not OPTS.spice_exe:
debug.error("Could not find {} simulator.".format(OPTS.spice_name),
-1)
self.func_test(bank_num=1)
self.func_test(bank_num=2)
self.func_test(bank_num=4)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
# check write driver array for single port
debug.info(2, "Testing write_driver_array for columns=8, word_size=8")
a = factory.create(module_type="write_driver_array",
columns=8,
word_size=8)
self.local_check(a)
debug.info(2, "Testing write_driver_array for columns=16, word_size=8")
a = factory.create(module_type="write_driver_array",
columns=16,
word_size=8)
self.local_check(a)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.nominal_corner_only = False
OPTS.netlist_only = True
from characterizer import lib
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=2, num_words=16, num_banks=1)
c.words_per_row = 1
c.recompute_sizes()
debug.info(
1,
"Testing analytical timing for sample 2 bit, 16 words SRAM with 1 bank"
)
# This doesn't have to use the factory since worst case
# it will just replaece the top-level module of the same name
s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
lib(out_dir=OPTS.openram_temp,
sram=s.s,
sp_file=tempspice,
use_model=True)
# get all of the .lib files generated
files = os.listdir(OPTS.openram_temp)
nametest = re.compile("\.lib$", re.IGNORECASE)
lib_files = filter(nametest.search, files)
# and compare them with the golden model
for filename in lib_files:
newname = filename.replace(".lib", "_analytical.lib")
libname = "{0}/{1}".format(OPTS.openram_temp, filename)
golden = "{0}/golden/{1}".format(
os.path.dirname(os.path.realpath(__file__)), newname)
self.assertTrue(self.isapproxdiff(libname, golden, 0.15))
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config
c = sram_config(word_size=8, write_size=4, num_words=16, num_banks=1)
c.words_per_row = 1
c.recompute_sizes()
debug.info(
1, "Layout test for {}rw,{}r,{}w sram "
"with {} bit words, {} words, {} bit writes, {} words per "
"row, {} banks".format(OPTS.num_rw_ports, OPTS.num_r_ports,
OPTS.num_w_ports, c.word_size, c.num_words,
c.write_size, c.words_per_row, c.num_banks))
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import verify
(gds_dir, allnames) = setup_files()
drc_errors = 0
debug.info(1, "\nPerforming DRC on: " + ", ".join(allnames))
for f in allnames:
gds_name = "{0}/{1}.gds".format(gds_dir, f)
if not os.path.isfile(gds_name):
drc_errors += 1
debug.error("Missing GDS file: {}".format(gds_name))
drc_errors += verify.run_drc(f, gds_name)
# fails if there are any DRC errors on any cells
self.assertEqual(drc_errors, 0)
globals.end_openram()
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell="replica_pbitcell"
OPTS.dummy_bitcell="dummy_pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 1
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import functional, delay
from sram_config import sram_config
c = sram_config(word_size=2,
num_words=32,
num_banks=1)
c.words_per_row=2
c.recompute_sizes()
debug.info(1, "Functional test for {}rw,{}r,{}w psram with"
"{} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "sram.sp"
s.sp_write(tempspice)
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
f = functional(s.s, tempspice, corner)
(fail, error) = f.run()
self.assertTrue(fail,error)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
global verify
import verify
OPTS.check_lvsdrc = False
import ptx
import tech
debug.info(2, "Checking three fingers PMOS")
fet = ptx.ptx(width=tech.drc["minwidth_tx"],
mults=4,
tx_type="pmos",
connect_active=True,
connect_poly=True)
self.local_drc_check(fet)
OPTS.check_lvsdrc = True
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
OPTS.spice_version="hspice"
globals.set_spice()
import sram
import tech
slews = [tech.spice["rise_time"]*2]
import setup_hold
sh = setup_hold.setup_hold()
data = sh.analyze(slews,slews)
if OPTS.tech_name == "freepdk45":
golden_data = {'setup_times_LH': [0.014648399999999999],
'hold_times_LH': [0.0024414],
'hold_times_HL': [-0.0036620999999999997],
'setup_times_HL': [0.0085449]}
elif OPTS.tech_name == "scn3me_subm":
golden_data = {'setup_times_LH': [0.1000977],
'hold_times_LH': [0.020751999999999996],
'hold_times_HL': [-0.0830078],
'setup_times_HL': [0.020751999999999996]}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results
self.assertTrue(len(data.keys())==len(golden_data.keys()))
# Check each result
for k in data.keys():
if type(data[k])==list:
for i in range(len(data[k])):
self.assertTrue(isclose(data[k][i],golden_data[k][i]))
else:
self.assertTrue(isclose(data[k],golden_data[k]))
OPTS.check_lvsdrc = True
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell = "replica_pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 1
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import functional, delay
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4, num_words=256, num_banks=1)
c.words_per_row = 4
c.recompute_sizes()
debug.info(
1,
"Functional test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks"
.format(OPTS.num_rw_ports, OPTS.num_r_ports, OPTS.num_w_ports,
c.word_size, c.num_words, c.words_per_row, c.num_banks))
s = sram(c, name="sram")
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0],
OPTS.temperatures[0])
f = functional(s.s, tempspice, corner)
d = delay(s.s, tempspice, corner)
feasible_period = self.find_feasible_test_period(
d, s.s, f.load, f.slew)
f.num_cycles = 10
(fail, error) = f.run()
self.assertTrue(fail, error)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config
c = sram_config(word_size=4, num_words=16)
c.num_banks = 2
c.words_per_row = 1
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create("bank", sram_config=c)
self.local_check(a)
c.num_words = 32
c.words_per_row = 2
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create("bank", sram_config=c)
self.local_check(a)
c.num_words = 64
c.words_per_row = 4
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create("bank", sram_config=c)
self.local_check(a)
c.word_size = 2
c.num_words = 128
c.words_per_row = 8
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create("bank", sram_config=c)
self.local_check(a)
globals.end_openram()
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
# check write driver array for single port
debug.info(2, "Testing write_driver_array for columns=8, word_size=8")
a = factory.create(module_type="write_driver_array",
columns=8,
word_size=8)
self.local_check(a)
debug.info(2, "Testing write_driver_array for columns=16, word_size=8")
a = factory.create(module_type="write_driver_array",
columns=16,
word_size=8)
self.local_check(a)
# check write driver array for multi-port
OPTS.bitcell = "pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
factory.reset()
debug.info(
2,
"Testing write_driver_array for columns=8, word_size=8 (multi-port case)"
)
a = factory.create(module_type="write_driver_array",
columns=8,
word_size=8)
self.local_check(a)
debug.info(
2,
"Testing write_driver_array for columns=16, word_size=8 (multi-port case)"
)
a = factory.create(module_type="write_driver_array",
columns=16,
word_size=8)
self.local_check(a)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import precharge
import tech
# check precharge in single port
debug.info(2, "Checking precharge for handmade bitcell")
tx = precharge.precharge(name="precharge_driver", size=1)
self.local_check(tx)
# check precharge in multi-port
OPTS.bitcell = "pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 1
factory.reset()
debug.info(2,
"Checking precharge for pbitcell (innermost connections)")
tx = precharge.precharge(name="precharge_driver",
size=1,
bitcell_bl="bl0",
bitcell_br="br0")
self.local_check(tx)
debug.info(2,
"Checking precharge for pbitcell (innermost connections)")
tx = precharge.precharge(name="precharge_driver",
size=1,
bitcell_bl="bl1",
bitcell_br="br1")
self.local_check(tx)
debug.info(2,
"Checking precharge for pbitcell (outermost connections)")
tx = precharge.precharge(name="precharge_driver",
size=1,
bitcell_bl="bl2",
bitcell_br="br2")
self.local_check(tx)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
# Use the 2 port cell since it is usually bigger/easier
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
# Checks 2x4 and 2-input NAND decoder
debug.info(1, "Testing 16 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", num_outputs=16)
self.local_check(a)
# Checks 2x4 and 2-input NAND decoder with non-power-of-two
debug.info(1, "Testing 17 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", num_outputs=17)
self.local_check(a)
# Checks 2x4 with 3x8 and 2-input NAND decoder
debug.info(1, "Testing 32 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", num_outputs=32)
self.local_check(a)
# Checks 3 x 2x4 and 3-input NAND decoder
debug.info(1, "Testing 64 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", num_outputs=64)
self.local_check(a)
# Checks 2x4 and 2 x 3x8 and 3-input NAND with non-power-of-two
debug.info(1, "Testing 132 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", num_outputs=132)
self.local_check(a)
# Checks 3 x 3x8 and 3-input NAND decoder
debug.info(1, "Testing 512 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", num_outputs=512)
self.local_check(a)
globals.end_openram()
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
from gds_cell import gds_cell
from design import design
from signal_router import signal_router as router
class routing(design, openram_test):
"""
A generic GDS design that we can route on.
"""
def __init__(self, name):
design.__init__(self, "top")
# Instantiate a GDS cell with the design
gds_file = "{0}/{1}.gds".format(
os.path.dirname(os.path.realpath(__file__)), name)
cell = gds_cell(name, gds_file)
self.add_inst(name=name, mod=cell, offset=[0, 0])
self.connect_inst([])
r = router(gds_file)
layer_stack = ("metal1", "via1", "metal2")
# This should be infeasible because it is blocked without a detour.
self.assertFalse(
r.route(self,
layer_stack,
src="A",
dest="B",
detour_scale=1))
# This should be feasible because we allow it to detour
self.assertTrue(
r.route(self,
layer_stack,
src="A",
dest="B",
detour_scale=3))
r = routing("08_expand_region_test_{0}".format(OPTS.tech_name))
self.local_drc_check(r)
# fails if there are any DRC errors on any cells
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
# check write driver array for multi-port
OPTS.bitcell = "pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
factory.reset()
debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)")
a = factory.create(module_type="write_driver_array", columns=8, word_size=8)
self.local_check(a)
debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case)")
a = factory.create(module_type="write_driver_array", columns=16, word_size=8)
self.local_check(a)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
# check precharge array in multi-port
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Checking precharge for 1rw1r port 0")
tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(tx)
factory.reset()
debug.info(2, "Checking precharge for 1rw1r port 1")
tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl1", bitcell_br="br1")
self.local_check(tx)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Testing 4x4 array for cell_1rw_1r")
a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=1, bitcell_ports=[0, 1])
self.local_check(a)
# Sky 130 has restrictions on the symmetries
if OPTS.tech_name != "sky130":
debug.info(2, "Testing 4x4 array for cell_1rw_1r")
a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=2, right_rbl=0, bitcell_ports=[0, 1])
self.local_check(a)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import wordline_driver
import tech
debug.info(2, "Checking driver")
tx = wordline_driver.wordline_driver(rows=8)
self.local_check(tx)
if OPTS.multiport_check:
OPTS.bitcell = "pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
debug.info(2, "Checking driver (multi-port case)")
tx = wordline_driver.wordline_driver(rows=8)
self.local_check(tx)
globals.end_openram()
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
# check wordline driver for single port
debug.info(2, "Checking driver")
tx = factory.create(module_type="wordline_driver", rows=8, cols=32)
self.local_check(tx)
# check wordline driver for multi-port
OPTS.bitcell = "pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
factory.reset()
debug.info(2, "Checking driver (multi-port case)")
tx = factory.create(module_type="wordline_driver", rows=8, cols=64)
self.local_check(tx)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
factory.reset()
debug.info(2, "Testing 4x4 array for bitcell")
a = factory.create(module_type="replica_bitcell_array",
cols=4,
rows=4,
left_rbl=1,
right_rbl=0,
bitcell_ports=[0])
self.local_check(a)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
global verify
import verify
OPTS.check_lvsdrc = False
import sense_amp_array
debug.info(2,
"Testing sense_amp_array for word_size=4, words_per_row=2")
a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=2)
self.local_check(a)
debug.info(2,
"Testing sense_amp_array for word_size=4, words_per_row=4")
a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=4)
self.local_check(a)
OPTS.check_lvsdrc = True
globals.end_openram()
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
# checking hierarchical precode 3x8 for single port
debug.info(1, "Testing sample for hierarchy_predecode3x8")
a = factory.create(module_type="hierarchical_predecode3x8")
self.local_check(a)
# checking hierarchical precode 3x8 for multi-port
OPTS.bitcell = "pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
debug.info(
1, "Testing sample for hierarchy_predecode3x8 (multi-port case)")
a = factory.create(module_type="hierarchical_predecode3x8")
self.local_check(a)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(
2,
"Testing write_mask_and_array for columns=8, word_size=8, write_size=4"
)
a = factory.create(module_type="write_mask_and_array",
columns=8,
word_size=8,
write_size=4)
self.local_check(a)
debug.info(
2,
"Testing write_mask_and_array for columns=16, word_size=16, write_size=4"
)
a = factory.create(module_type="write_mask_and_array",
columns=16,
word_size=16,
write_size=4)
self.local_check(a)
debug.info(
2,
"Testing write_mask_and_array for columns=16, word_size=8, write_size=2"
)
a = factory.create(module_type="write_mask_and_array",
columns=16,
word_size=8,
write_size=2)
self.local_check(a)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.analytical_delay = False
OPTS.trim_netlist = False
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import lib
if not OPTS.spice_exe:
debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=2,
num_words=16,
num_banks=1)
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank")
s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
lib(out_dir=OPTS.openram_temp, sram=s.s, sp_file=tempspice, use_model=False)
# get all of the .lib files generated
files = os.listdir(OPTS.openram_temp)
nametest = re.compile("\.lib$", re.IGNORECASE)
lib_files = filter(nametest.search, files)
# and compare them with the golden model
for filename in lib_files:
libname = "{0}/{1}".format(OPTS.openram_temp,filename)
golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),filename)
self.assertTrue(self.isapproxdiff(libname,golden,0.40))
reload(characterizer)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Testing one left replica column for dual port")
a = factory.create(module_type="replica_column",
rows=4,
rbl=[1, 0],
replica_bit=1)
self.local_check(a)
debug.info(2, "Testing one right replica column for dual port")
a = factory.create(module_type="replica_column",
rows=4,
rbl=[0, 1],
replica_bit=5)
self.local_check(a)
debug.info(2,
"Testing two (left, right) replica columns for dual port")
a = factory.create(module_type="replica_column",
rows=4,
rbl=[1, 1],
replica_bit=1)
self.local_check(a)
debug.info(2,
"Testing two (left, right) replica columns for dual port")
a = factory.create(module_type="replica_column",
rows=4,
rbl=[1, 1],
replica_bit=6)
self.local_check(a)
globals.end_openram()
