def write_test(self, *, data_width, granularity):
core = FakeGramCore()
native_port = core.crossbar.get_native_port()
dut = gramWishbone(core,
data_width=data_width,
granularity=granularity)
def process():
# Initialize native port
yield native_port.cmd.ready.eq(0)
yield native_port.wdata.ready.eq(0)
yield native_port.rdata.valid.eq(0)
reference_value = 0xBADDCAFE_FEEDFACE_BEEFCAFE_BAD0DAB0
data_granularity_radio = data_width // granularity
for i in range(native_port.data_width // data_width):
res = yield from self.write_request(
bus=dut.bus,
native_port=native_port,
adr=i,
sel=2**data_granularity_radio - 1,
value=(reference_value >>
(i * data_width)) & 2**data_width - 1)
self.assertEqual((reference_value >>
(i * data_width)) & 2**data_width - 1,
(res >> (i * data_width)) & 2**data_width - 1)
runSimulation(dut, process, "test_frontend_wishbone.vcd")
def test_sel_empty(self):
core = FakeGramCore()
native_port = core.crossbar.get_native_port()
dut = gramWishbone(core, data_width=32, granularity=8)
def process():
# Initialize native port
yield native_port.cmd.ready.eq(0)
yield native_port.wdata.ready.eq(0)
yield native_port.rdata.valid.eq(0)
def selfirstdword(bus, native_port):
self.assertEqual((yield native_port.wdata.we), 0xF)
yield from self.write_request(bus=dut.bus,
native_port=native_port,
adr=0,
sel=0,
value=0xAAAAAAAA,
timeout=128,
ackCallback=selfirstdword)
runSimulation(dut, process, "test_frontend_wishbone.vcd")
def test_sel_write(self):
core = FakeGramCore()
native_port = core.crossbar.get_native_port()
dut = gramWishbone(core, data_width=32, granularity=8)
def process():
# Initialize native port
yield native_port.cmd.ready.eq(0)
yield native_port.wdata.ready.eq(0)
yield native_port.rdata.valid.eq(0)
def sel1(bus, native_port):
self.assertEqual((yield native_port.wdata.we), 0b1)
def sel2(bus, native_port):
self.assertEqual((yield native_port.wdata.we), 0b10)
def sel3(bus, native_port):
self.assertEqual((yield native_port.wdata.we), 0b100)
def sel4(bus, native_port):
self.assertEqual((yield native_port.wdata.we), 0b1000)
def sel5(bus, native_port):
self.assertEqual((yield native_port.wdata.we), 0b10000)
def sel9(bus, native_port):
self.assertEqual((yield native_port.wdata.we), 0b100000000)
def sel13(bus, native_port):
self.assertEqual((yield native_port.wdata.we), 0b1000000000000)
def selfirstdword(bus, native_port):
self.assertEqual((yield native_port.wdata.we), 0xF)
def sellastdword(bus, native_port):
self.assertEqual((yield native_port.wdata.we), 0xF000)
yield from self.write_request(bus=dut.bus,
native_port=native_port,
adr=0,
sel=1,
value=0xCA,
timeout=128,
ackCallback=sel1)
yield from self.write_request(bus=dut.bus,
native_port=native_port,
adr=0,
sel=0b10,
value=0xCA,
timeout=128,
ackCallback=sel2)
yield from self.write_request(bus=dut.bus,
native_port=native_port,
adr=0,
sel=0b100,
value=0xCA,
timeout=128,
ackCallback=sel3)
yield from self.write_request(bus=dut.bus,
native_port=native_port,
adr=0,
sel=0b1000,
value=0xCA,
timeout=128,
ackCallback=sel4)
yield from self.write_request(bus=dut.bus,
native_port=native_port,
adr=1,
sel=1,
value=0xCA,
timeout=128,
ackCallback=sel5)
yield from self.write_request(bus=dut.bus,
native_port=native_port,
adr=2,
sel=1,
value=0xCA,
timeout=128,
ackCallback=sel9)
yield from self.write_request(bus=dut.bus,
native_port=native_port,
adr=3,
sel=1,
value=0xCA,
timeout=128,
ackCallback=sel13)
yield from self.write_request(bus=dut.bus,
native_port=native_port,
adr=3,
sel=0xF,
value=0xCA,
timeout=128,
ackCallback=sellastdword)
yield from self.write_request(bus=dut.bus,
native_port=native_port,
adr=4,
sel=0xF,
value=0xCA,
timeout=128,
ackCallback=selfirstdword)
runSimulation(dut, process, "test_frontend_wishbone.vcd")
def test_init(self):
core = FakeGramCore()
dut = gramWishbone(core, data_width=32, granularity=8)
self.assertEqual(dut.bus.data_width, 32)
self.assertEqual(dut.bus.granularity, 8)
