def as_hdl_HdlType_array(self, typ, declaration=False):
if declaration:
return super(ToHdlAstSimModel_types,
self).as_hdl_HdlType_array(typ,
declaration=declaration)
else:
t_name = self.name_scope.get_object_name(typ)
return hdl_getattr(self.SELF, t_name)
def as_hdl_HEnumVal(self, val: HEnumVal):
try:
t_name = self.name_scope.get_object_name(val._dtype)
except ObjectForNameNotFound:
if self.debug:
t_name = val._dtype.name
else:
raise
if val.vld_mask:
try:
name = self.name_scope.get_object_name(val)
except ObjectForNameNotFound:
if self.debug:
name = val.val
else:
raise
return hdl_getattr(HdlValueId(t_name, obj=val._dtype), name)
else:
return hdl_call(hdl_getattr(HdlValueId(t_name, obj=val._dtype), "from_py"),
[None, ])
def as_hdl_Operator(self, op: Operator):
ops = op.operands
o = op.operator
if o == AllOps.EQ:
op0 = self.as_hdl_Value(ops[0])
op1 = self.as_hdl_Value(ops[1])
return hdl_call(hdl_getattr(op0, "_eq"), [
op1,
])
elif o == AllOps.TERNARY:
zero, one = BIT.from_py(0), BIT.from_py(1)
if ops[1] == one and ops[2] == zero:
# ignore redundant x ? 1 : 0
return self.as_hdl_cond(ops[0], True)
else:
op0 = self.as_hdl_cond(ops[0], True)
op1 = self.as_hdl_Value(ops[1])
op2 = self.as_hdl_Value(ops[2])
return hdl_call(hdl_getattr(op0, "_ternary"), [op1, op2])
elif o == AllOps.RISING_EDGE or o == AllOps.FALLING_EDGE:
if o == AllOps.RISING_EDGE:
fn = "_onRisingEdge"
else:
fn = "_onFallingEdge"
op0 = self.as_hdl_Value(ops[0])
# pop .val
op0 = op0.ops[0]
return hdl_call(hdl_getattr(op0, fn), [])
elif o in [
AllOps.BitsAsUnsigned, AllOps.BitsAsVec, AllOps.BitsAsSigned
]:
op0, = ops
do_cast = bool(op0._dtype.signed) != bool(op.result._dtype.signed)
op_hdl = self.as_hdl_Value(op0)
if do_cast:
if bool(op0._dtype.signed):
sign = self.TRUE
else:
sign = self.FALSE
# cast_sign()
return hdl_call(hdl_getattr(op_hdl, "cast_sign"), [
sign,
])
else:
return op_hdl
elif o == AllOps.CONCAT:
return hdl_call(hdl_getattr(self.as_hdl_Value(ops[0]), "_concat"),
[
self.as_hdl_Value(ops[1]),
])
elif o == AllOps.EQ:
return hdl_call(hdl_getattr(self.as_hdl_Value(ops[0]), "_eq"), [
self.as_hdl_Value(ops[1]),
])
else:
o = self.op_transl_dict[o]
return HdlOp(o, [self.as_hdl_Value(o2) for o2 in ops])
def visit_HdlStmAssign(self, o):
"""
:type o: HdlStmAssign
"""
assert o.event_delay is None, o
assert o.time_delay is None, o
is_clock_edge_dependent = self.is_clock_edge_dependent(o)
dst, dst_index = self.pop_index_list(o.dst)
o.dst = hdl_getattr(dst, "val_next")
if dst_index:
o.src = [o.src, dst_index, is_clock_edge_dependent]
else:
o.src = [o.src, is_clock_edge_dependent]
def visit_HdlOp(self, o):
"""
:type o: HdlOp
:return: iHdlExpr
"""
if o.fn == HdlOpType.DOT:
# update only left most name
o.ops[0] = self.visit_iHdlExpr(o.ops[0])
if not self._stm_dst:
return hdl_getattr(o, "val")
else:
o.ops = [self.visit_iHdlExpr(op) for op in o.ops]
return o
def as_hdl_SignalItem(self, si: SignalItem, declaration=False):
if declaration:
sigType = systemCTypeOfSig(si)
with SignalTypeSwap(self, sigType):
return ToHdlAst_Value.as_hdl_SignalItem(self, si, declaration=True)
else:
if si.hidden and si.origin is not None:
return self.as_hdl(si.origin)
else:
sigType = systemCTypeOfSig(si)
_si = HdlValueId(si.name, obj=si)
if self._in_sensitivity_list or self._is_target or sigType is SIGNAL_TYPE.REG:
return _si
else:
return hdl_call(hdl_getattr(_si, "read"), [])
def as_hdl_BitsVal(self, val: BitsVal):
isFullVld = val._is_full_valid()
if not self._valueWidthRequired:
if isFullVld:
return HdlValueInt(val.val, None, 16)
elif val.vld_mask == 0:
return self.NONE
t = self.as_hdl_HdlType_bits(val._dtype, declaration=False)
c = hdl_getattr(t, "from_py")
args = [HdlValueInt(val.val, None, 16), ]
if not isFullVld:
args.append(HdlValueInt(val.vld_mask, None, 16))
return hdl_call(c, args)
def _as_hdl_Assignment(self, dst, typeOfDst, src):
orig_is_target = self._is_target
try:
self._is_target = True
dst_hdl = self.as_hdl(dst)
finally:
self._is_target = orig_is_target
src_hdl = self.as_hdl_Value(src)
if typeOfDst == SIGNAL_TYPE.REG:
return HdlStmAssign(src_hdl, dst_hdl)
else:
return hdl_call(hdl_getattr(dst_hdl, "write"), [
src_hdl,
])
def visit_iHdlExpr(self, o):
"""
:type o: iHdlExpr
:return: iHdlExpr
"""
if isinstance(o, HdlValueId):
o = add_io_prefix(o)
if not self._stm_dst:
return hdl_getattr(o, "val")
return o
elif o is None or isinstance(o, HdlValueInt) or is_str(o):
return o
elif isinstance(o, list):
return [self.visit_iHdlExpr(_o) for _o in o]
elif isinstance(o, HdlOp):
return self.visit_HdlOp(o)
else:
raise NotImplementedError("Do not know how to convert %s" % (o))
class ToHdlAstSimModel_value(ToHdlAst_Value):
Bits3val = HdlValueId("Bits3val", obj=Bits3val)
Bits3t = HdlValueId("Bits3t", obj=Bits3t)
SELF = HdlValueId("self", obj=LanguageKeyword())
Array3val = HdlValueId("Array3val", obj=Array3val)
SLICE = HdlValueId("slice", obj=slice)
TRUE = HdlValueId("True", obj=True)
FALSE = HdlValueId("False", obj=False)
Bits3val = HdlValueId("Bits3val", obj=Bits3val)
ABits3t = HdlValueId("Bits3t", obj=Bits3t)
SELF_IO = hdl_getattr(HdlValueId("self", obj=LanguageKeyword()), "io")
CONCAT = HdlValueId("Concat", obj=Concat)
op_transl_dict = {
**HWT_TO_HDLCONVEROTR_OPS,
AllOps.INDEX: HdlOpType.INDEX,
}
_cast_ops = {
AllOps.BitsAsSigned,
AllOps.BitsAsUnsigned,
AllOps.BitsAsVec,
}
def is_suitable_for_const_extract(self, val: HValue):
return not isinstance(val._dtype, HEnum) or val.vld_mask == 0
def as_hdl_SignalItem(self,
si: Union[SignalItem, HdlIdDef],
declaration=False):
if not declaration and not si.hidden:
if si._const:
return hdl_getattr(self.SELF, si.name)
else:
return hdl_getattr(hdl_getattr(self.SELF_IO, si.name), "val")
else:
return super(ToHdlAstSimModel_value,
self).as_hdl_SignalItem(si, declaration=declaration)
def as_hdl_BitsVal(self, val: BitsVal):
dtype = val._dtype
as_hdl_int = self.as_hdl_int
t = hdl_call(self.Bits3t, [
as_hdl_int(dtype.bit_length()),
as_hdl_int(int(bool(dtype.signed)))
])
return hdl_call(self.Bits3val,
[t, as_hdl_int(val.val),
as_hdl_int(val.vld_mask)])
def as_hdl_DictVal(self, val):
return {
self.as_hdl_int(int(k)): self.as_hdl_Value(v)
for k, v in val.items()
}
def as_hdl_HArrayVal(self, val):
return hdl_call(self.Array3val, [
self.as_hdl_HdlType(val._dtype),
self.as_hdl_DictVal(val.val),
self.as_hdl_int(val.vld_mask)
])
def as_hdl_SliceVal(self, val):
args = (val.val.start, val.val.stop, val.val.step)
return hdl_call(self.SLICE, [self.as_hdl_int(int(a)) for a in args])
def as_hdl_HEnumVal(self, val: HEnumVal):
t_name = self.name_scope.get_object_name(val._dtype)
if val.vld_mask:
name = self.name_scope.get_object_name(val)
return hdl_getattr(hdl_getattr(self.SELF, t_name), name)
else:
return hdl_call(
hdl_getattr(hdl_getattr(self.SELF, t_name), "from_py"), [
None,
])
def as_hdl_Operator(self, op: Operator):
ops = op.operands
o = op.operator
if o == AllOps.EQ:
op0 = self.as_hdl_Value(ops[0])
op1 = self.as_hdl_Value(ops[1])
return hdl_call(hdl_getattr(op0, "_eq"), [
op1,
])
elif o == AllOps.TERNARY:
if ops[1] == one and ops[2] == zero:
# ignore redundant x ? 1 : 0
return self.as_hdl_cond(ops[0], True)
else:
op0 = self.as_hdl_cond(ops[0], True)
op1 = self.as_hdl_Value(ops[1])
op2 = self.as_hdl_Value(ops[2])
return hdl_call(hdl_getattr(op0, "_ternary"), [op1, op2])
elif o == AllOps.RISING_EDGE or o == AllOps.FALLING_EDGE:
if o == AllOps.RISING_EDGE:
fn = "_onRisingEdge"
else:
fn = "_onFallingEdge"
op0 = self.as_hdl_Value(ops[0])
# pop .val
op0 = op0.ops[0]
return hdl_call(hdl_getattr(op0, fn), [])
elif o in self._cast_ops:
op0, = ops
do_cast = bool(op0._dtype.signed) != bool(op.result._dtype.signed)
op_hdl = self.as_hdl_Value(op0)
if do_cast:
if bool(op.result._dtype.signed):
sign = self.TRUE
else:
sign = self.FALSE
return hdl_call(hdl_getattr(op_hdl, "cast_sign"), [
sign,
])
else:
return op_hdl
elif o == AllOps.CONCAT:
return hdl_call(hdl_getattr(self.as_hdl_Value(ops[0]), "_concat"),
[
self.as_hdl_Value(ops[1]),
])
elif o == AllOps.EQ:
return hdl_call(hdl_getattr(self.as_hdl_Value(ops[0]), "_eq"), [
self.as_hdl_Value(ops[1]),
])
else:
o = self.op_transl_dict[o]
return HdlOp(o, [self.as_hdl_Value(o2) for o2 in ops])
def add_io_prefix(o):
s = HdlValueId("self")
s = hdl_getattr(s, "io")
return hdl_name_prefix(s, o)
