def getBaseNameScope(cls):
"""
Get root of name space
"""
s = NameScope.make_top(False)
s.update(cls._keywords_dict)
return s
def verilog_to_hwt(context):
"""
:type context: HdlContext
"""
link_module_dec_def(context)
name_scope = NameScope.make_top(False)
DiscoverDeclarations(name_scope).visit_HdlContext(context)
ResolveNames(name_scope).visit_HdlContext(context)
#wrap_module_statements_to_processes(context)
InjectProcessSensToStatements().visit_HdlContext(context)
BasicHdlSimModelTranslateVerilogOperands().visit_HdlContext(context)
VerilogTypesToHwt().visit_HdlContext(context)
return context, name_scope
def verilog_to_basic_hdl_sim_model(context):
"""
:type context: HdlContext
"""
link_module_dec_def(context)
name_scope = NameScope.make_top(False)
DiscoverDeclarations(name_scope).visit_HdlContext(context)
ResolveNames(name_scope).visit_HdlContext(context)
wrap_module_statements_to_processes(context)
BasicHdlSimModelTranslateVerilogOperands().visit_HdlContext(context)
VerilogTypesToBasicHdlSimModel().visit_HdlContext(context)
stm_outputs = discover_stm_outputs_context(context)
AddUniqueLabelsToAllProcesses(name_scope, stm_outputs).context(context)
AssignmentToUpdateAssignment().visit_HdlContext(context)
ApplyIoScopeToSignalNames().visit_HdlContext(context)
return context, stm_outputs, name_scope
def verilog_to_hwt(context):
"""
:type context: HdlContext
"""
link_module_dec_def(context)
name_scope = NameScope.make_top(False)
propopulate_verilog_builtins(name_scope)
DiscoverDeclarations(name_scope).visit_HdlContext(context)
ResolveNames(name_scope).visit_HdlContext(context)
DetectCompileTimeStatements().visit_HdlContext(context)
InjectProcessSensToStatements().visit_HdlContext(context)
BasicHdlSimModelTranslateVerilogOperands(
downto_to_slice_fn=False).visit_HdlContext(context)
VerilogTypesToHwt().visit_HdlContext(context)
AddCallOperatorForCallWithoutParenthesis().visit_HdlContext(context)
wrap_module_statements_to_processes(context)
SignalAssignmentsToCallOp().visit_HdlContext(context)
return context, name_scope
def check_file(self, name, to_hdl_cls):
"""
Load AST from json and convert it to target language
and compare it with reference file
"""
json_suffix, ref_file_suffix = self.FILE_SUFFIX[to_hdl_cls]
d = parse_hdlConvertor_json_file(os.path.join(ROOT,
name + json_suffix))
buff = StringIO()
ser = to_hdl_cls(buff)
if to_hdl_cls is ToBasicHdlSimModel:
# it is required to know outputs of each process
stm_outputs = discover_stm_outputs_context(d)
stm_outputs = rm_ToBasicHdlSimModel_io_prefix_and_tmp_vars_from_outputs(
stm_outputs)
ser.visit_HdlContext(d, stm_outputs)
else:
if to_hdl_cls is ToHwt:
# it is required to know the direction of port connections
link_module_dec_def(d)
name_scope = NameScope.make_top(False)
for kw in HWT_KEYWORDS:
name_scope.register_name(kw, LanguageKeyword())
DiscoverDeclarations(name_scope).visit_HdlContext(d)
ResolveNames(name_scope).visit_HdlContext(d)
ser.visit_HdlContext(d)
res_str = buff.getvalue()
ref_file = os.path.join(ROOT, "ref", name + ref_file_suffix)
# with open(ref_file, "w", encoding="utf-8") as f:
# f.write(res_str)
with open(ref_file, encoding="utf-8") as f:
ref = f.read()
self.assertEqual(ref, res_str)