def run_IM_cosim():
# Initiate signals
MAX_TIME = 1000000
clock = Signal(0)
MR = Signal(0, delay=10)
MW = Signal(0, delay=10)
address = Signal(intbv(0, 0, 2**32), delay=10)
WD = Signal(intbv(0, 0, 2**32), delay=10)
pyData = Signal(intbv(0, 0, 2**32))
vData = Signal(intbv(0, 0, 2**32))
# Build driver instances
clock_driver = clock_generator(clock, period=20)
addr_driver = random_signal(clock, address, seed=1)
WD_driver = random_signal(clock, WD, seed=2)
MR_driver = pulse_generator(clock, MR, delay=2)
MW_driver = pulse_generator(clock, MW, delay=3)
py_cosim = traceSignals(py_dm(clock, address, MW, MR, pyData, WD))
v_cosim = v_dm(clock, MR, MW, address, WD, vData)
read_test = match_test_report(clock,
vData,
pyData,
a_name="v:",
b_name="py:")
sim = Simulation(instances())
sim.run(MAX_TIME)
def run_ALU_cosim():
# Initiate signals
MAX_TIME = 1000000
clock = Signal(0)
reset = Signal(0)
inA = Signal(intbv(0, 0, 2**32), delay=10)
inB = Signal(intbv(0, 0, 2**32), delay=10)
ALU_control = Signal(intbv(0, 0, 2**3), delay=10)
pyData = Signal(intbv(0, 0, 2**32))
pyZero = Signal(intbv(0, 0, 2**32))
vData = Signal(intbv(0, 0, 2**32))
vZero = Signal(intbv(0, 0, 2**32))
# Build driver instances
clock_driver = clock_generator(clock, period=20)
control_driver = random_signal(clock, ALU_control, seed=1)
A_rand = random_signal(clock, inA, seed=2)
B_rand = random_signal(clock, inB, seed=3)
reset_driver = pulse_generator(clock, reset)
py_cosim = traceSignals(
py_alu(clock, reset, inA, inB, ALU_control, pyData, pyZero))
v_cosim = v_alu(clock, reset, ALU_control, inA, inB, vData, vZero)
read_test = match_test_report(clock, (vData, vZero), (pyData, pyZero),
a_name="v:",
b_name="py:")
sim = Simulation(instances())
sim.run(MAX_TIME)
from myhdl import Signal, Simulation, intbv, traceSignals
from MUX import MUX
from helpers.Clock_Generator import clock_generator
from helpers.Random_Signal import random_signal
from helpers.Pulse_Generator import pulse_generator
if (__name__ == "__main__"):
MAX_CYCLES = 1000
clk = Signal(0)
ctrl = Signal(0)
inputA = Signal(intbv(0, 0, 2**32))
inputB = Signal(intbv(0, 0, 2**32))
output = Signal(intbv(0, 0, 2**32))
clock_driver = clock_generator(clk)
ctrl_driver = pulse_generator(clk, ctrl)
inputA_driver = random_signal(inputA, clk)
inputB_driver = random_signal(inputB, clk)
MUX_driver = traceSignals(MUX(ctrl, inputA, inputB, output))
sim = Simulation(clock_driver, ctrl_driver, inputA_driver, inputB_driver,
MUX_driver)
sim.run(MAX_CYCLES)
from myhdl import Signal, Simulation, intbv, traceSignals
from PC import program_counter
from helpers.Clock_Generator import clock_generator
from helpers.Random_Signal import random_signal
from helpers.Pulse_Generator import pulse_generator
# Program Counter Testbench
# Runs the PC for max_cycles
# Gives the branch signal and a new address every 10 cycles
if (__name__ == "__main__"):
MAX_CYCLES = 1000
addr_out = Signal(intbv(0, 0, 2**32))
addr_in = Signal(intbv(0, 0, 2**32))
branch_signal = Signal(0)
clock = Signal(0)
pc_driver = traceSignals(
program_counter(clock, addr_out, addr_in, branch_signal))
clock_driver = clock_generator(clock)
rand_driver = random_signal(addr_in, clock)
pulse_driver = pulse_generator(clock, branch_signal)
sim = Simulation(clock_driver, rand_driver, pc_driver, pulse_driver)
sim.run(MAX_CYCLES)
def run_RF_cosim():
# Initiate signals
MAX_TIME = 10000
clock = Signal(0)
reset = Signal(0, delay=10)
writeSignal = Signal(0, delay=10)
pyReadA = Signal(intbv(0, 0, 2**32))
pyReadB = Signal(intbv(0, 0, 2**32))
vReadA = Signal(intbv(0, 0, 2**32))
vReadB = Signal(intbv(0, 0, 2**32))
write = Signal(intbv(0, 0, 2**32), delay=10)
rAddrA = Signal(intbv(0, 0, 2**5))
rAddrB = Signal(intbv(0, 0, 2**5))
wAddr = Signal(intbv(0, 0, 2**5), delay=10)
pyregs = []
vregs = []
for i in range(0, 32):
pyregs.append(Signal(intbv(0, 0, 2**32)))
pyregs[i].driven = not pyregs[i].driven
vregs.append(Signal(intbv(0, 0, 2**32)))
vregs[i].driven = not vregs[i].driven
# Build driver instances
clock_driver = clock_generator(clock, period=20)
reset_driver = pulse_generator(clock, reset, delay=30)
write_driver = pulse_generator(clock, writeSignal, delay=2)
wd_rand = random_signal(clock, write, seed=1)
rdAddrA_rand = random_signal(clock, rAddrA, seed=2)
rdAddrB_rand = random_signal(clock, rAddrB, seed=3)
wAddr_rand = random_signal(clock, wAddr, seed=4)
py_cosim = traceSignals(
RegisterFile(pyReadA, pyReadB, write, rAddrA, rAddrB, wAddr,
writeSignal, clock, reset, pyregs))
v_cosim = v_rf(vReadA, vReadB, write, rAddrA, rAddrB, wAddr, writeSignal,
clock, reset, vregs)
read_test = match_test_report(clock, (vReadA, vReadB), (pyReadA, pyReadB),
a_name="v:",
b_name="py:")
reg_test = match_test_report(clock,
vregs,
pyregs,
a_name="verilog",
b_name="python")
sim = Simulation(instances())
inp = ""
help = 'Enter "run <cycles>" to run the simulation "print" to show the register files, or "quit" to exit.'
prompt = "command: "
print(help)
while (inp != "quit"):
inp = input(prompt)
if inp == "show":
for x, reg in enumerate(pyregs):
print("py[%d]=%#x" % (x, reg.val), end=' ')
print()
for x, reg in enumerate(vregs):
print(" v[%d]=%#x" % (x, reg.val), end=' ')
print()
if (pyregs == vregs):
print("They match")
else:
print("They don't match")
continue
elif inp.startswith("run "):
try:
cycles = int(inp.split()[1].strip())
sim.run(cycles)
continue
except ValueError:
pass
elif inp != "quit":
print(help)
RegWrite_in = Signal(0)
MemtoReg_in = Signal(intbv(0, 0, 2**2))
D_MEM_read_data_in = Signal(intbv(0, 0, 2**32))
D_MEM_read_addr_in = Signal(intbv(0, 0, 2**32))
EX_MEM_RegisterRd_in = Signal(intbv(0, 0, 2**5))
D_MEM_read_data_out = Signal(intbv(0, 0, 2**32))
D_MEM_read_addr_out = Signal(intbv(0, 0, 2**32))
MEM_WB_RegisterRd_out = Signal(intbv(0, 0, 2**5))
RegWrite_out = Signal(0)
MemtoReg_out = Signal(intbv(0, 0, 2**2))
rst = Signal(0)
clock_driver = clock_generator(clk, 10)
reg_driver = traceSignals(
mem_wb(clk, rst, RegWrite_in, MemtoReg_in, D_MEM_read_data_in,
D_MEM_read_addr_in, EX_MEM_RegisterRd_in, D_MEM_read_data_out,
D_MEM_read_addr_out, MEM_WB_RegisterRd_out, RegWrite_out,
MemtoReg_out))
MemtoReg_in_driver = random_signal(MemtoReg_in, clk)
D_MEM_read_data_in_driver = random_signal(D_MEM_read_data_in, clk)
D_MEM_read_addr_in_driver = random_signal(D_MEM_read_addr_in, clk)
EX_MEM_RegisterRd_in_driver = random_signal(EX_MEM_RegisterRd_in, clk)
RegWrite_in_driver = pulse_generator(clk, RegWrite_in, 20)
sim = Simulation(clock_driver, reg_driver, MemtoReg_in_driver,
D_MEM_read_data_in_driver, D_MEM_read_addr_in_driver,
EX_MEM_RegisterRd_in_driver, RegWrite_in_driver)
sim.run(MAX_CYCLES)
MAX_CYCLES = 100000
#creates signal variables
BusA = Signal(intbv(0, 0, 2**32)) #output
BusB = Signal(intbv(0, 0, 2**32)) #output
BusW = Signal(intbv(0, 0, 2**32)) #input
RA = Signal(intbv(0, 0, 2**5)) #input
RB = Signal(intbv(0, 0, 2**5)) #input
RW = Signal(intbv(0, 0, 2**5)) #input
RegWr = Signal(intbv(0, 0, 2**1)) #input
clk = Signal(intbv(0, 0, 2**1)) #input
rst = Signal(0) #input
#makes an array for memory
outregs = []
for i in range(0, 32):
outregs.append(Signal(intbv(0, 0, 2**32)))
outregs[i].driven = not outregs[i].driven
#creates drivers for signals
busWAddress_driver = random_signal(clk, BusW)
readAAddress_driver = random_signal(clk, RA)
readBAddress_driver = random_signal(clk, RB)
readWAddress_driver = random_signal(clk, RW)
RegWr_driver = pulse_generator(clk, RegWr, delay=2)
reset_driver = pulse_generator(clk, rst, delay=40)
register_driver = traceSignals(
RegisterFile(BusA, BusB, BusW, RA, RB, RW, RegWr, clk, rst, outregs))
clock_driver = clock_generator(clk)
#create and run simulation
sim = Simulation(instances())
sim.run(MAX_CYCLES)
from IF_ID import if_id
from helpers.Clock_Generator import clock_generator
from helpers.Random_Signal import random_signal
from helpers.Pulse_Generator import pulse_generator
if (__name__ == "__main__"):
MAX_CYCLES = 1000
clk = Signal(0)
inst_in = Signal(intbv(0, 0, 2**32))
inst_out = Signal(intbv(0, 0, 2**32))
PC_in = Signal(intbv(0, 0, 2**32))
PC_out = Signal(intbv(0, 0, 2**32))
IF_flush = Signal(0)
IFID_write = Signal(0)
rst = Signal(0)
clock_driver = clock_generator(clk, 10)
reg_driver = traceSignals(
if_id(clk, rst, inst_in, inst_out, PC_in, PC_out, IF_flush,
IFID_write))
inst_driver = random_signal(inst_in, clk)
PC_driver = random_signal(PC_in, clk)
IF_flush_driver = pulse_generator(clk, IF_flush, 20)
IFID_write_driver = pulse_generator(clk, IFID_write)
sim = Simulation(clock_driver, reg_driver, inst_driver, PC_driver,
IF_flush_driver, IFID_write_driver)
sim.run(MAX_CYCLES)