def genptr_decl_new(f, tag, regtype, regid, regno):
if (regtype == "N"):
if (regid in {"s", "t"}):
f.write(" TCGv %s%sN = hex_new_value[insn->regno[%d]];\n" % \
(regtype, regid, regno))
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "P"):
if (regid in {"t", "u", "v"}):
f.write(" TCGv %s%sN = hex_new_pred_value[insn->regno[%d]];\n" % \
(regtype, regid, regno))
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "O"):
if (regid == "s"):
f.write(" const intptr_t %s%sN_num = insn->regno[%d];\n" % \
(regtype, regid, regno))
if (hex_common.skip_qemu_helper(tag)):
f.write(" const intptr_t %s%sN_off =\n" % \
(regtype, regid))
f.write(" ctx_future_vreg_off(ctx, %s%sN_num," % \
(regtype, regid))
f.write(" 1, true);\n")
else:
f.write(" TCGv %s%sN = tcg_constant_tl(%s%sN_num);\n" % \
(regtype, regid, regtype, regid))
else:
print("Bad register parse: ", regtype, regid)
else:
print("Bad register parse: ", regtype, regid)
def main():
hex_common.read_semantics_file(sys.argv[1])
hex_common.read_attribs_file(sys.argv[2])
hex_common.read_overrides_file(sys.argv[3])
hex_common.read_overrides_file(sys.argv[4])
hex_common.calculate_attribs()
tagregs = hex_common.get_tagregs()
tagimms = hex_common.get_tagimms()
with open(sys.argv[5], 'w') as f:
for tag in hex_common.tags:
## Skip the priv instructions
if ("A_PRIV" in hex_common.attribdict[tag]):
continue
## Skip the guest instructions
if ("A_GUEST" in hex_common.attribdict[tag]):
continue
## Skip the diag instructions
if (tag == "Y6_diag"):
continue
if (tag == "Y6_diag0"):
continue
if (tag == "Y6_diag1"):
continue
if (hex_common.skip_qemu_helper(tag)):
continue
gen_helper_function(f, tag, tagregs, tagimms)
def genptr_decl_new(f, tag, regtype, regid, regno):
if (regtype == "N"):
if (regid in {"s", "t"}):
f.write(" TCGv %s%sN = hex_new_value[insn->regno[%d]];\n" % \
(regtype, regid, regno))
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "P"):
if (regid in {"t", "u", "v"}):
f.write(" TCGv %s%sN = hex_new_pred_value[insn->regno[%d]];\n" % \
(regtype, regid, regno))
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "O"):
if (regid == "s"):
f.write(" const intptr_t %s%sN_num = insn->regno[%d];\n" % \
(regtype, regid, regno))
if (hex_common.skip_qemu_helper(tag)):
f.write(" const intptr_t %s%sN_off =\n" % \
(regtype, regid))
f.write(" test_bit(%s%sN_num, ctx->vregs_updated)\n" % \
(regtype, regid))
f.write(" ? offsetof(CPUHexagonState, ")
f.write("future_VRegs[%s%sN_num])\n" % \
(regtype, regid))
f.write(" : offsetof(CPUHexagonState, ")
f.write("zero_vector);\n")
else:
f.write(" TCGv %s%sN = tcg_const_tl(%s%sN_num);\n" % \
(regtype, regid, regtype, regid))
else:
print("Bad register parse: ", regtype, regid)
else:
print("Bad register parse: ", regtype, regid)
def genptr_free(f, tag, regtype, regid, regno):
if (regtype == "R"):
if (regid in {"dd", "ss", "tt", "xx", "yy"}):
f.write(" tcg_temp_free_i64(%s%sV);\n" % (regtype, regid))
elif (regid in {"d", "e", "x", "y"}):
f.write(" tcg_temp_free(%s%sV);\n" % (regtype, regid))
elif (regid not in {"s", "t", "u", "v"}):
print("Bad register parse: ", regtype, regid)
elif (regtype == "P"):
if (regid in {"d", "e", "x"}):
f.write(" tcg_temp_free(%s%sV);\n" % (regtype, regid))
elif (regid not in {"s", "t", "u", "v"}):
print("Bad register parse: ", regtype, regid)
elif (regtype == "C"):
if (regid in {"dd", "ss"}):
f.write(" tcg_temp_free_i64(%s%sV);\n" % (regtype, regid))
elif (regid in {"d", "s"}):
f.write(" tcg_temp_free(%s%sV);\n" % (regtype, regid))
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "M"):
if (regid != "u"):
print("Bad register parse: ", regtype, regid)
elif (regtype == "V"):
if (regid
in {"dd", "uu", "vv", "xx", "d", "s", "u", "v", "w", "x",
"y"}):
if (not hex_common.skip_qemu_helper(tag)):
f.write(" tcg_temp_free_ptr(%s%sV);\n" % \
(regtype, regid))
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "Q"):
if (regid in {"d", "e", "s", "t", "u", "v", "x"}):
if (not hex_common.skip_qemu_helper(tag)):
f.write(" tcg_temp_free_ptr(%s%sV);\n" % \
(regtype, regid))
else:
print("Bad register parse: ", regtype, regid)
else:
print("Bad register parse: ", regtype, regid)
def genptr_free_new(f, tag, regtype, regid, regno):
if (regtype == "N"):
if (regid not in {"s", "t"}):
print("Bad register parse: ", regtype, regid)
elif (regtype == "P"):
if (regid not in {"t", "u", "v"}):
print("Bad register parse: ", regtype, regid)
elif (regtype == "O"):
if (regid == "s"):
if (not hex_common.skip_qemu_helper(tag)):
f.write(" tcg_temp_free(%s%sN);\n" % \
(regtype, regid))
else:
print("Bad register parse: ", regtype, regid)
else:
print("Bad register parse: ", regtype, regid)
def gen_tcg_func(f, tag, regs, imms):
f.write("static void generate_%s(\n" % tag)
f.write(" CPUHexagonState *env,\n")
f.write(" DisasContext *ctx,\n")
f.write(" Insn *insn,\n")
f.write(" Packet *pkt)\n")
f.write('{\n')
if hex_common.need_ea(tag): gen_decl_ea_tcg(f, tag)
i = 0
## Declare all the operands (regs and immediates)
for regtype, regid, toss, numregs in regs:
genptr_decl_opn(f, tag, regtype, regid, toss, numregs, i)
i += 1
for immlett, bits, immshift in imms:
genptr_decl_imm(f, immlett)
if 'A_PRIV' in hex_common.attribdict[tag]:
f.write(' fCHECKFORPRIV();\n')
if 'A_GUEST' in hex_common.attribdict[tag]:
f.write(' fCHECKFORGUEST();\n')
## Read all the inputs
for regtype, regid, toss, numregs in regs:
if (hex_common.is_read(regid)):
genptr_src_read_opn(f, regtype, regid, tag)
if (hex_common.skip_qemu_helper(tag)):
f.write(" fGEN_TCG_%s(%s);\n" % (tag, hex_common.semdict[tag]))
else:
## Generate the call to the helper
for immlett, bits, immshift in imms:
gen_helper_decl_imm(f, immlett)
if hex_common.need_part1(tag):
f.write(" TCGv part1 = tcg_const_tl(insn->part1);\n")
if hex_common.need_slot(tag):
f.write(" TCGv slot = tcg_const_tl(insn->slot);\n")
f.write(" gen_helper_%s(" % (tag))
i = 0
## If there is a scalar result, it is the return type
for regtype, regid, toss, numregs in regs:
if (hex_common.is_written(regid)):
gen_helper_call_opn(f, tag, regtype, regid, toss, numregs, i)
i += 1
if (i > 0): f.write(", ")
f.write("cpu_env")
i = 1
for regtype, regid, toss, numregs in regs:
if (hex_common.is_read(regid)):
gen_helper_call_opn(f, tag, regtype, regid, toss, numregs, i)
i += 1
for immlett, bits, immshift in imms:
gen_helper_call_imm(f, immlett)
if hex_common.need_slot(tag): f.write(", slot")
if hex_common.need_part1(tag): f.write(", part1")
f.write(");\n")
if hex_common.need_slot(tag):
f.write(" tcg_temp_free(slot);\n")
if hex_common.need_part1(tag):
f.write(" tcg_temp_free(part1);\n")
for immlett, bits, immshift in imms:
gen_helper_free_imm(f, immlett)
## Write all the outputs
for regtype, regid, toss, numregs in regs:
if (hex_common.is_written(regid)):
genptr_dst_write_opn(f, regtype, regid, tag)
## Free all the operands (regs and immediates)
if hex_common.need_ea(tag): gen_free_ea_tcg(f)
for regtype, regid, toss, numregs in regs:
genptr_free_opn(f, regtype, regid, i, tag)
i += 1
f.write("}\n\n")
def genptr_decl(f, tag, regtype, regid, regno):
regN = "%s%sN" % (regtype, regid)
if (regtype == "R"):
if (regid in {"ss", "tt"}):
f.write(" TCGv_i64 %s%sV = tcg_temp_local_new_i64();\n" % \
(regtype, regid))
f.write(" const int %s = insn->regno[%d];\n" % \
(regN, regno))
elif (regid in {"dd", "ee", "xx", "yy"}):
genptr_decl_pair_writable(f, tag, regtype, regid, regno)
elif (regid in {"s", "t", "u", "v"}):
f.write(" TCGv %s%sV = hex_gpr[insn->regno[%d]];\n" % \
(regtype, regid, regno))
elif (regid in {"d", "e", "x", "y"}):
genptr_decl_writable(f, tag, regtype, regid, regno)
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "P"):
if (regid in {"s", "t", "u", "v"}):
f.write(" TCGv %s%sV = hex_pred[insn->regno[%d]];\n" % \
(regtype, regid, regno))
elif (regid in {"d", "e", "x"}):
genptr_decl_writable(f, tag, regtype, regid, regno)
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "C"):
if (regid == "ss"):
f.write(" TCGv_i64 %s%sV = tcg_temp_local_new_i64();\n" % \
(regtype, regid))
f.write(" const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \
(regN, regno))
elif (regid == "dd"):
genptr_decl_pair_writable(f, tag, regtype, regid, regno)
elif (regid == "s"):
f.write(" TCGv %s%sV = tcg_temp_local_new();\n" % \
(regtype, regid))
f.write(" const int %s%sN = insn->regno[%d] + HEX_REG_SA0;\n" % \
(regtype, regid, regno))
elif (regid == "d"):
genptr_decl_writable(f, tag, regtype, regid, regno)
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "M"):
if (regid == "u"):
f.write(" const int %s%sN = insn->regno[%d];\n"% \
(regtype, regid, regno))
f.write(" TCGv %s%sV = hex_gpr[%s%sN + HEX_REG_M0];\n" % \
(regtype, regid, regtype, regid))
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "V"):
if (regid in {"dd"}):
f.write(" const int %s%sN = insn->regno[%d];\n" %\
(regtype, regid, regno))
f.write(" const intptr_t %s%sV_off =\n" %\
(regtype, regid))
if (hex_common.is_tmp_result(tag)):
f.write(" ctx_tmp_vreg_off(ctx, %s%sN, 2, true);\n" % \
(regtype, regid))
else:
f.write(" ctx_future_vreg_off(ctx, %s%sN," % \
(regtype, regid))
f.write(" 2, true);\n")
if (not hex_common.skip_qemu_helper(tag)):
f.write(" TCGv_ptr %s%sV = tcg_temp_new_ptr();\n" % \
(regtype, regid))
f.write(" tcg_gen_addi_ptr(%s%sV, cpu_env, %s%sV_off);\n" % \
(regtype, regid, regtype, regid))
elif (regid in {"uu", "vv", "xx"}):
f.write(" const int %s%sN = insn->regno[%d];\n" % \
(regtype, regid, regno))
f.write(" const intptr_t %s%sV_off =\n" % \
(regtype, regid))
f.write(" offsetof(CPUHexagonState, %s%sV);\n" % \
(regtype, regid))
if (not hex_common.skip_qemu_helper(tag)):
f.write(" TCGv_ptr %s%sV = tcg_temp_new_ptr();\n" % \
(regtype, regid))
f.write(" tcg_gen_addi_ptr(%s%sV, cpu_env, %s%sV_off);\n" % \
(regtype, regid, regtype, regid))
elif (regid in {"s", "u", "v", "w"}):
f.write(" const int %s%sN = insn->regno[%d];\n" % \
(regtype, regid, regno))
f.write(" const intptr_t %s%sV_off =\n" % \
(regtype, regid))
f.write(" vreg_src_off(ctx, %s%sN);\n" % \
(regtype, regid))
if (not hex_common.skip_qemu_helper(tag)):
f.write(" TCGv_ptr %s%sV = tcg_temp_new_ptr();\n" % \
(regtype, regid))
elif (regid in {"d", "x", "y"}):
f.write(" const int %s%sN = insn->regno[%d];\n" % \
(regtype, regid, regno))
f.write(" const intptr_t %s%sV_off =\n" % \
(regtype, regid))
if (regid == "y"):
f.write(" offsetof(CPUHexagonState, vtmp);\n")
elif (hex_common.is_tmp_result(tag)):
f.write(" ctx_tmp_vreg_off(ctx, %s%sN, 1, true);\n" % \
(regtype, regid))
else:
f.write(" ctx_future_vreg_off(ctx, %s%sN," % \
(regtype, regid))
f.write(" 1, true);\n")
if (not hex_common.skip_qemu_helper(tag)):
f.write(" TCGv_ptr %s%sV = tcg_temp_new_ptr();\n" % \
(regtype, regid))
f.write(" tcg_gen_addi_ptr(%s%sV, cpu_env, %s%sV_off);\n" % \
(regtype, regid, regtype, regid))
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "Q"):
if (regid in {"d", "e", "x"}):
f.write(" const int %s%sN = insn->regno[%d];\n" % \
(regtype, regid, regno))
f.write(" const intptr_t %s%sV_off =\n" % \
(regtype, regid))
f.write(" offsetof(CPUHexagonState,\n")
f.write(" future_QRegs[%s%sN]);\n" % \
(regtype, regid))
if (not hex_common.skip_qemu_helper(tag)):
f.write(" TCGv_ptr %s%sV = tcg_temp_new_ptr();\n" % \
(regtype, regid))
f.write(" tcg_gen_addi_ptr(%s%sV, cpu_env, %s%sV_off);\n" % \
(regtype, regid, regtype, regid))
elif (regid in {"s", "t", "u", "v"}):
f.write(" const int %s%sN = insn->regno[%d];\n" % \
(regtype, regid, regno))
f.write(" const intptr_t %s%sV_off =\n" %\
(regtype, regid))
f.write(" offsetof(CPUHexagonState, QRegs[%s%sN]);\n" % \
(regtype, regid))
if (not hex_common.skip_qemu_helper(tag)):
f.write(" TCGv_ptr %s%sV = tcg_temp_new_ptr();\n" % \
(regtype, regid))
else:
print("Bad register parse: ", regtype, regid)
else:
print("Bad register parse: ", regtype, regid)
def genptr_src_read(f, tag, regtype, regid):
if (regtype == "R"):
if (regid in {"ss", "tt", "xx", "yy"}):
f.write(" tcg_gen_concat_i32_i64(%s%sV, hex_gpr[%s%sN],\n" % \
(regtype, regid, regtype, regid))
f.write(" hex_gpr[%s%sN + 1]);\n" % \
(regtype, regid))
elif (regid in {"x", "y"}):
f.write(" tcg_gen_mov_tl(%s%sV, hex_gpr[%s%sN]);\n" % \
(regtype,regid,regtype,regid))
elif (regid not in {"s", "t", "u", "v"}):
print("Bad register parse: ", regtype, regid)
elif (regtype == "P"):
if (regid == "x"):
f.write(" tcg_gen_mov_tl(%s%sV, hex_pred[%s%sN]);\n" % \
(regtype, regid, regtype, regid))
elif (regid not in {"s", "t", "u", "v"}):
print("Bad register parse: ", regtype, regid)
elif (regtype == "C"):
if (regid == "ss"):
f.write(" gen_read_ctrl_reg_pair(ctx, %s%sN, %s%sV);\n" % \
(regtype, regid, regtype, regid))
elif (regid == "s"):
f.write(" gen_read_ctrl_reg(ctx, %s%sN, %s%sV);\n" % \
(regtype, regid, regtype, regid))
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "M"):
if (regid != "u"):
print("Bad register parse: ", regtype, regid)
elif (regtype == "V"):
if (regid in {"uu", "vv", "xx"}):
f.write(" tcg_gen_gvec_mov(MO_64, %s%sV_off,\n" % \
(regtype, regid))
f.write(" vreg_src_off(ctx, %s%sN),\n" % \
(regtype, regid))
f.write(" sizeof(MMVector), sizeof(MMVector));\n")
f.write(" tcg_gen_gvec_mov(MO_64,\n")
f.write(" %s%sV_off + sizeof(MMVector),\n" % \
(regtype, regid))
f.write(" vreg_src_off(ctx, %s%sN ^ 1),\n" % \
(regtype, regid))
f.write(" sizeof(MMVector), sizeof(MMVector));\n")
elif (regid in {"s", "u", "v", "w"}):
if (not hex_common.skip_qemu_helper(tag)):
f.write(" tcg_gen_addi_ptr(%s%sV, cpu_env, %s%sV_off);\n" % \
(regtype, regid, regtype, regid))
elif (regid in {"x", "y"}):
f.write(" tcg_gen_gvec_mov(MO_64, %s%sV_off,\n" % \
(regtype, regid))
f.write(" vreg_src_off(ctx, %s%sN),\n" % \
(regtype, regid))
f.write(" sizeof(MMVector), sizeof(MMVector));\n")
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "Q"):
if (regid in {"s", "t", "u", "v"}):
if (not hex_common.skip_qemu_helper(tag)):
f.write(" tcg_gen_addi_ptr(%s%sV, cpu_env, %s%sV_off);\n" % \
(regtype, regid, regtype, regid))
elif (regid in {"x"}):
f.write(" tcg_gen_gvec_mov(MO_64, %s%sV_off,\n" % \
(regtype, regid))
f.write(" offsetof(CPUHexagonState, QRegs[%s%sN]),\n" % \
(regtype, regid))
f.write(" sizeof(MMQReg), sizeof(MMQReg));\n")
else:
print("Bad register parse: ", regtype, regid)
else:
print("Bad register parse: ", regtype, regid)