def test_SwitchContainer_try_reduce__empty(self): nl = RtlNetlist() a = nl.sig("a", BIT) s0 = Switch(a).add_cases([(hBit(0), []), (hBit(1), [])]) s0_red, io_change = s0._try_reduce() self.assertFalse(io_change) self.assertEqual(s0_red, [])
def test_SwitchContainer_try_reduce__all(self): nl = RtlNetlist() a = nl.sig("a", BIT) b = nl.sig("b", BIT) s0 = Switch(a).add_cases([(hBit(0), [ b(0), ]), (hBit(1), [ b(0), ])]) s0_red, io_change = s0._try_reduce() self.assertFalse(io_change) self.assertEqual(len(s0_red), 1) self.assertTrue(s0_red[0].isSame(b(0)))
def test_basicSwitch(self): a = self.n.sig('a', dtype=INT) b = self.n.sig('b', dtype=INT) obj = Switch(a).addCases([(i, c(i, b)) for i in range(4)]) cont, io_change = obj._try_reduce() self.assertFalse(io_change) self.assertEqual(len(cont), 1) cont = cont[0] tmpl = SwitchContainer(a, [(i, c(i, b)) for i in range(3)] + [(None, c(3, b))]) self.compareStructure(tmpl, cont)
def test_ifsInSwitch(self): n = self.n stT = HEnum('t_state', ["idle", "tsWait", "ts0Wait", "ts1Wait", "lenExtr"]) clk = n.sig('clk') rst = n.sig("rst") st = n.sig('st', stT, clk=clk, syncRst=rst, defVal=stT.idle) sd0 = n.sig('sd0') sd1 = n.sig('sd1') cntrlFifoVld = n.sig('ctrlFifoVld') cntrlFifoLast = n.sig('ctrlFifoLast') def tsWaitLogic(): return If(sd0 & sd1, c(stT.lenExtr, st)).Else(c(stT.ts1Wait, st)) obj = Switch(st)\ .Case(stT.idle, tsWaitLogic() ).Case(stT.tsWait, tsWaitLogic() ).Case(stT.ts0Wait, If(sd0, c(stT.lenExtr, st) ).Else( c(st, st) ) ).Case(stT.ts1Wait, If(sd1, c(stT.lenExtr, st) ).Else( c(st, st) ) ).Case(stT.lenExtr, If(cntrlFifoVld & cntrlFifoLast, c(stT.idle, st) ).Else( c(st, st) ) ) cont, io_change = obj._try_reduce() self.assertFalse(io_change) self.assertEqual(len(cont), 1) cont = cont[0] tmpl = """ CASE st IS WHEN idle => IF (sd0 AND sd1) = '1' THEN st_next <= lenExtr; ELSE st_next <= ts1Wait; END IF; WHEN tsWait => IF (sd0 AND sd1) = '1' THEN st_next <= lenExtr; ELSE st_next <= ts1Wait; END IF; WHEN ts0Wait => IF sd0 = '1' THEN st_next <= lenExtr; ELSE st_next <= st; END IF; WHEN ts1Wait => IF sd1 = '1' THEN st_next <= lenExtr; ELSE st_next <= st; END IF; WHEN OTHERS => IF (ctrlFifoVld AND ctrlFifoLast) = '1' THEN st_next <= idle; ELSE st_next <= st; END IF; END CASE """ self.strStructureCmp(cont, tmpl)
def test_ifsInSwitch(self): n = self.n stT = HEnum('t_state', ["idle", "tsWait", "ts0Wait", "ts1Wait", "lenExtr"]) clk = n.sig('clk') rst = n.sig("rst") st = n.sig('st', stT, clk=clk, syncRst=rst, defVal=stT.idle) sd0 = n.sig('sd0') sd1 = n.sig('sd1') cntrlFifoVld = n.sig('ctrlFifoVld') cntrlFifoLast = n.sig('ctrlFifoLast') def tsWaitLogic(): return If(sd0 & sd1, c(stT.lenExtr, st) ).Else( c(stT.ts1Wait, st) ) obj = Switch(st)\ .Case(stT.idle, tsWaitLogic() ).Case(stT.tsWait, tsWaitLogic() ).Case(stT.ts0Wait, If(sd0, c(stT.lenExtr, st) ).Else( c(st, st) ) ).Case(stT.ts1Wait, If(sd1, c(stT.lenExtr, st) ).Else( c(st, st) ) ).Case(stT.lenExtr, If(cntrlFifoVld & cntrlFifoLast, c(stT.idle, st) ).Else( c(st, st) ) ) cont, io_change = obj._try_reduce() self.assertFalse(io_change) self.assertEqual(len(cont), 1) cont = cont[0] tmpl = """ CASE st IS WHEN idle => IF (sd0 AND sd1) = '1' THEN st_next <= lenExtr; ELSE st_next <= ts1Wait; END IF; WHEN tsWait => IF (sd0 AND sd1) = '1' THEN st_next <= lenExtr; ELSE st_next <= ts1Wait; END IF; WHEN ts0Wait => IF sd0 = '1' THEN st_next <= lenExtr; ELSE st_next <= st; END IF; WHEN ts1Wait => IF sd1 = '1' THEN st_next <= lenExtr; ELSE st_next <= st; END IF; WHEN OTHERS => IF (ctrlFifoVld AND ctrlFifoLast) = '1' THEN st_next <= idle; ELSE st_next <= st; END IF; END CASE """ self.strStructureCmp(cont, tmpl)