for _src in src:
dsts = [next(d) for d in _destinations]
assignemnts.extend(connect(_src, *dsts, exclude=exclude, fit=fit))
else:
for dst in destinations:
r = _connect(src, dst, exclude=exclude, fit=fit)
if isinstance(r, HdlStatement):
assignemnts.append(r)
else:
assignemnts.extend(r)
return assignemnts
# variadic operator functions
And = _mkOp(and_)
Add = _mkOp(add)
Or = _mkOp(or_)
Xor = _mkOp(xor)
Concat = _mkOp(concatFn)
def power(base, exp) -> RtlSignalBase:
return toHVal(base)**exp
def ror(sig, howMany) -> RtlSignalBase:
"Rotate right"
if sig._dtype.bit_length() == 1:
return sig
return sig[howMany:]._concat(sig[:howMany])
def parity(bit_vector):
return _mkOp(ne)(*bit_vector)