def _concat(self, other): w = self._dtype.bit_length() other_w = other._dtype.bit_length() resWidth = w + other_w resT = vecT(resWidth) if areValues(self, other): return self._concat__val(other) else: w = self._dtype.bit_length() other_w = other._dtype.bit_length() resWidth = w + other_w resT = vecT(resWidth) # is instance of signal if isinstance(other, InterfaceBase): other = other._sig if isinstance(other._dtype, Bits): if other._dtype.signed is not None: other = other._vec() elif other._dtype == BOOL: other = other._convert(BIT) else: raise TypeError(other._dtype) if self._dtype.signed is not None: self = self._vec() return Operator.withRes(AllOps.CONCAT, [self, other], resT)\ ._convert(vecT(resWidth, signed=self._dtype.signed))
def _injectMultiplerToDtype(self): t = self._dtype factor = self._multipliedBy if t == BIT: newT = vecT(factor) elif isinstance(t, Bits): w = getWidthExpr(t) if isinstance(w, RtlSignalBase): # bouth Param or factor Value newW = w * factor elif isinstance(factor, RtlSignalBase): # w is Value newW = factor * w else: # bouth Value newW = w.clone() newW.val *= factor.val newT = vecT(newW) else: raise NotImplementedError("type:%s" % (repr(t))) self._dtype = newT
def _concat__val(self, other): w = self._dtype.bit_length() other_w = other._dtype.bit_length() resWidth = w + other_w resT = vecT(resWidth) v = self.clone() v.val = (v.val << other_w) | other.val v.vldMask = (v.vldMask << other_w) | other.vldMask v.updateTime = max(self.updateTime, other.updateTime) v._dtype = resT return v
def VectSignal(width, signed=None, masterDir=D.OUT, multipliedBy=None, alternativeNames=None, loadConfig=True): """ Create basic :class:`.Signal` interface where type is vector """ return Signal(masterDir, multipliedBy, vecT(width, signed), alternativeNames, loadConfig)
def __mul__(self, other): other = toHVal(other) assert isinstance(other._dtype, (Integer, Bits)) if areValues(self, other): return self._mul__val(other) else: resT = getMulResT(self._dtype, other._dtype) if self._dtype.signed is None: self = self._unsigned() if isinstance(other._dtype, Bits) and other._dtype.signed is None: other = other._unsigned() elif isinstance(other._dtype, Integer): pass else: raise TypeError("%s %s %s" % (repr(self), repr(AllOps.MUL), repr(other))) subResT = vecT(resT.bit_length(), self._dtype.signed) o = Operator.withRes(AllOps.MUL, [self, other], subResT) return o._convert(resT)
def _getitem__val(self, key): updateTime = max(self.updateTime, key.updateTime) keyVld = key._isFullVld() val = 0 vld = 0 if isinstance(key._dtype, Integer): if keyVld: val = selectBit(self.val, key.val) vld = selectBit(self.vldMask, key.val) return BitsVal(val, BIT, vld, updateTime=updateTime) elif key._dtype == SLICE: if keyVld: firstBitNo = key.val[1].val size = key._size() val = selectBitRange(self.val, firstBitNo, size) vld = selectBitRange(self.vldMask, firstBitNo, size) retT = vecT(size, signed=self._dtype.signed) return BitsVal(val, retT, vld, updateTime=updateTime) else: raise TypeError(key)
def ForEach(parentUnit, items, bodyFn, name=""): """ Generate for loop for static items :param parentUnit: unit where this code should be instantiated :param items: items which this "for" itering on :param bodyFn: function which fn(item, index) or fn(item) returns (statementList, ack). It's content is performed in every iteration. When ack is high loop will fall to next iteration """ items = list(items) l = len(items) if l == 0: # if there are no items there is nothing to generate return [] elif l == 1: # if there is only one item do not generate counter logic generate return _ForEach_callBody(bodyFn, items[0], 0) else: # if there is multiple items we have to generate counter logic index = parentUnit._reg(name + "for_index", vecT(log2ceil(l + 1), signed=False), defVal=0) ackSig = parentUnit._sig(name + "for_ack") statementLists = [] for i, (statementList, ack) in [(i, _ForEach_callBody(bodyFn, item, i)) for i, item in enumerate(items)]: statementLists.append(statementList + [ (ackSig**ack), ]) If(ackSig, If(index._eq(l - 1), index**0).Else(index**(index + 1))) return Switch(index)\ .addCases( enumerate(statementLists) ).Default( _ForEach_callBody(bodyFn, items[0], 0)[0] )
def getMulResT(firstT, secondT): if isinstance(secondT, Integer): return firstT # [maybe wrong] width = firstT.bit_length() + secondT.bit_length() return vecT(width, firstT.signed)
def _declr(self): self.din = Signal(dtype=vecT(self.DATA_WIDTH), masterDir=D.IN) with self._paramsShared(): self.dout = VldSynced()
def _declr(self): self.en = s() self.wait = s(masterDir=D.IN) self.data = s(dtype=vecT(self.DATA_WIDTH), alternativeNames=[''])
def _declr(self): self.addr = s(dtype=vecT(self.ADDR_WIDTH)) self.din = s(dtype=vecT(self.DATA_WIDTH)) self.dout = s(masterDir=D.IN, dtype=vecT(self.DATA_WIDTH)) self.en = s() self.we = s()
def _declr(self): self.data = s(dtype=vecT(self.DATA_WIDTH)) self.rd = s(masterDir=D.IN)
def _declr(self): self.data = s(dtype=vecT(self.DATA_WIDTH)) self.vld = s()