def _declr(self): if self.ID_WIDTH: raise NotImplementedError(self.ID_WIDTH) if self.DEST_WIDTH: raise NotImplementedError(self.DEST_WIDTH) addClkRstn(self) t = self._structT if isinstance(t, HStruct): intfCls = StructIntf elif isinstance(t, HUnion): intfCls = UnionSource else: raise TypeError(t) # input stream with self._paramsShared(): self.dataIn = self.intfCls() if self.SHARED_READY: self.dataOut_ready = Signal() # parsed data if is_only_padding(t): self.dataOut = None else: self.dataOut = intfCls(t, tuple(), self._mkFieldIntf)._m() self.parseTemplate() if self.OVERFLOW_SUPPORT: # flag which is 1 if we are behind the data which # we described by type in configuration # :note: if the data is unaligned this may be 1 in last parsed word # as well self.parsing_overflow = Signal()._m()
def _declr(self): self.clk = Signal() self.rst = Signal() self.en_mult = Signal() self.en_sum = Signal() self.input = VectSignal(self.width * self.size) self.output = VectSignal(self.width, signed=True)._m() for i in range(self.size): setattr(self, f"kernel_{i}", VectSignal(self.width)) self.multiplier = HObjList( FixedPointMultiplier( width=self.width, layer_id=self.layer_id, unit_id=self.unit_id, channel_id=self.channel_id, process_id=self.process_id, pixel_id=i, log_level=self.log_level + 1, ) for i in range(self.size)) name = f"ConvUnitL{self.layer_id}" self._name = name self._hdl_module_name = name
def _declr(self): self.data = VectSignal(self.DATA_WIDTH) self.keep = VectSignal(self.DATA_WIDTH // 8) if self.USE_STRB: self.strb = VectSignal(self.DATA_WIDTH // 8) self.relict = Signal() self.last = Signal()
def _declr(self): self.clk = Clk() self.mosi = Signal() # master out slave in self.miso = Signal(masterDir=DIRECTION.IN) # master in slave out self.cs = VectSignal(self.SLAVE_CNT) # chip select self._associatedClk = self.clk
def _declr(self): self.addr = VectSignal(self.ADDR_WIDTH) self.read = Signal() self.write = Signal() self.be = VectSignal(self.DATA_WIDTH // 8) self.dwr = VectSignal(self.DATA_WIDTH) super(Mi32AddrHs, self)._declr()
def _declr(self): with self._paramsShared(): def extData(): return VectSignal(self.DATA_WIDTH) self.clk = Clk() self.en = Signal() self.we = Signal() self.addr = VectSignal(self.ADDR_WIDTH) self.in_w_a = extData() self.in_w_b = extData() self.in_r_a = extData() self.in_r_b = extData() self.out_w_a = extData()._m() self.out_w_b = extData()._m() self.out_r_a = extData()._m() self.out_r_b = extData()._m() with self._paramsShared(): r = self.bramR = RamMultiClock() w = self.bramW = RamMultiClock() r.PORT_CNT = w.PORT_CNT = 2
def _declr(self): super()._declr() ce_t = Bits(self.REG_COUNT) # read chip enable bus self.bus2ip_rdce = Signal(dtype=ce_t) # Write chip enable bus self.bus2ip_wrce = Signal(dtype=ce_t)
def _declr(self): assert self.HAS_R or self.HAS_W, "has to have at least read or write part" self.addr = VectSignal(self.ADDR_WIDTH) DATA_WIDTH = self.DATA_WIDTH if self.HAS_W: self.din = VectSignal(DATA_WIDTH) if self.HAS_R: self.dout = VectSignal(DATA_WIDTH, masterDir=DIRECTION.IN) self.en = HandshakeSync() if (self.HAS_R and self.HAS_W) or (self.HAS_W and self.HAS_BE): # in write only mode we do not need this as well as we can use "en" if self.HAS_BE: assert DATA_WIDTH % 8 == 0, DATA_WIDTH self.we = VectSignal(DATA_WIDTH // 8) else: self.we = Signal() if self.HAS_W and self.HAS_BE: self.do_accumulate = Signal() self.do_overwrite = Signal() if self.HAS_R and self.HAS_BE: assert self.DATA_WIDTH % 8 == 0 self.dout_mask = VectSignal(self.DATA_WIDTH // 8, masterDir=DIRECTION.IN)
def _declr(self): self.a0 = Signal() self.a1 = Signal() self.a2 = Signal() self.a3 = Signal() self.a_out = VectSignal(4)._m()
def _declr(self): self.clk = Clk() self.a = Signal()._m() self.b = Signal()._m() self.c = Signal() self.d = Signal()
def _declr(self): self.a = Signal() self.b = Signal() self.c = Signal()._m() self.d = Signal()._m() self.e = Signal()
def _declr(self): # DDR read dataslv_array_2d_t self.data = VectSignal(self.DATA_WIDTH) # DDR read burst end self.end = Signal() # DDR read data valid self.valid = Signal()
def _declr(self): self.a = Signal() self.b = Signal()._m() self.child0 = ExampleChild() self.child1 = ExampleChild() self.child2 = ExampleChild()
def _declr(self): self.a = Signal() self.b = Signal()._m() # Here we instantiate our subunit and register it by assigning # to property of self it can be done in _impl as well, # but if you do it here, it offers more possibilities for parallelization self.subunit0 = SimpleUnit()
def _declr(self): addClkRstn(self) self.period = VectSignal(10) self.en = Signal() self.rstCntr = Signal() self.cntr0 = Signal()._m() self.cntr1 = Signal()._m()
def _declr(self): self.ci = Signal() # [possible improvement] you can use io = lambda : VectSignal(self.p_wordlength) as macro # so you do not have to repeat same code self.a = VectSignal(self.p_wordlength) self.b = VectSignal(self.p_wordlength) self.s = VectSignal(self.p_wordlength)._m() self.co = Signal()._m()
def _declr(self): self.ci = Signal() self.a = VectSignal(self.p_wordlength) self.b = VectSignal(self.p_wordlength) self.s = VectSignal(self.p_wordlength)._m() self.co = Signal()._m() self.fa = HObjList([FullAdder() for _ in range(self.p_wordlength)])
def _declr(self): # first parameter of Bits HDL type constructor is width, second optional is signed flag dt = Bits(self.DATA_WIDTH) # dt is now type vector with width specified by parameter DATA_WIDTH # it means it is 8bit width we specify data type for every signal self.a = Signal(dtype=dt) # you can also use shortcut VectorSignal(width) self.b = Signal(dtype=dt)._m()
def _declr(self): self.clk = Clk() self.rst = Rst() with self._associated(clk=self.clk, rst=self.rst): self.data = TristateSig() self.dir = Signal() self.stop = Signal(masterDir=DIRECTION.IN) self.next = Signal()
def _declr(self): addClkRstn(self) self.clk_cnt_initVal = VectSignal(16) self.i2c = I2c()._m() self.cntrl = I2cBitCntrlCmd() self.arbitrationLost = Signal()._m() # arbitration lost self.dout = Signal()._m()
def _declr(self): self.rst = Rst() self.inData = Signal(dtype=self.DATA_TYP) self.inClk = Clk() self.outData = Signal(dtype=self.DATA_TYP)._m() self.outClk = Clk()
def _declr(self): t = Bits(self.DATA_WIDTH, force_vector=self.FORCE_VECTOR) # connect self.t = Signal(dtype=t) # input self.i = Signal(dtype=t, masterDir=DIRECTION.IN) # output self.o = Signal(dtype=t)
def intf_for_Bits(t): if t.const: t = copy(t) t.const = False p = Signal(dtype=t, masterDir=DIRECTION.IN) else: p = RegCntrl() p.DATA_WIDTH = t.bit_length() return p
def _declr(self): t = Bits(self.DATA_WIDTH, self.forceVector) # connect self.t = Signal(dtype=t) # input self.i = Signal(dtype=t, masterDir=DIRECTION.IN) # output self.o = Signal(dtype=t)
def _declr(self): # fundamentals self.channel = VectSignal(self.CHANNEL_WIDTH) self.error = VectSignal(self.ERROR_WIDTH) Handshaked._declr(self) # packet transfer signals self.endOfPacket = Signal() self.startOfPacket = Signal()
def _declr(self): self.addr = VectSignal(self.ADDR_WIDTH) self.rd = Signal() self.wr = Signal() self.ardy = Signal(masterDir=DIRECTION.IN) self.be = VectSignal(self.DATA_WIDTH // 8) self.dwr = VectSignal(self.DATA_WIDTH) self.drd = VectSignal(self.DATA_WIDTH, masterDir=DIRECTION.IN) self.drdy = Signal(masterDir=DIRECTION.IN)
def _declr(self): self.a = Signal() self.b = Signal()._m() # there we instantiate our subunit and register it by assigning # to property of self it can be done in done in _impl as well, # but if you do it there it offers more possibilities for parallelization # and any configuration for unit has to be made before registering # in _impl self.subunit0 = SimpleUnit()
def _declr(self): addClkRstn(self) self.myIp = Signal(dtype=ipv4_t) with self._paramsShared(exclude={self.USE_STRB}): self.rx = AxiStream() with self._paramsShared(): self.tx = AxiStream()._m()
def _declr(self): self.clk = Signal() self.rst = Signal() self.en_pool = Signal() self.input = VectSignal(self.width * 4) self.output = VectSignal(self.width)._m() name = f"MaxPoolUnitL{self.layer_id}" self._name = name self._hdl_module_name = name
def _declr(self): # DDR data to write self.data = VectSignal(self.DATA_WIDTH) # DDR write burst end self.end = Signal() # DDR mask of data to write (select which bytes will be written) self.mask = VectSignal(self.DATA_WIDTH // 8) # DDR write enable self.wren = Signal() # DDR driver is ready to accept write request self.rdy = Signal(masterDir=DIRECTION.IN)
class PingResponder(Unit): """ Listen for echo request on rx axi stream interface and respond with echo response on tx interface :note: incoming checksum is not checked :attention: you have to ping "ping -s 0 <ip>" because unit ignores additional data in packet and linux by defaults adds it .. hwt-schematic:: """ def _config(self): self.DATA_WIDTH = Param(32) self.IS_BIGENDIAN = Param(True) self.USE_STRB = Param(True) def _declr(self): addClkRstn(self) self.myIp = Signal(dtype=ipv4_t) with self._paramsShared(exclude={self.USE_STRB}): self.rx = AxiStream() with self._paramsShared(): self.tx = AxiStream()._m() def req_load(self, parsed, regs, freeze): """ Load request from parser input into registers :param parsed: input interface with parsed fields of ICPM frame :param regs: registers for ICMP frame :param freeze: signal to freeze value in registers :param defVal: dictionary item from regs: default value :attention: dst and src are swapped """ dtype = regs._dtype for f in dtype.fields: name = f.name In = getattr(parsed, name) reg = getattr(regs, name) if isinstance(In, StructIntf): self.req_load(In, reg, freeze) else: if isinstance(reg, Value) or not isinstance(reg, RtlMemoryBase): # we have an exact value to use, ignore this intput In.rd(1) continue If(In.vld & ~freeze, reg(In.data) ) In.rd(~freeze) def connect_resp(self, resp, forgeIn, sendingReply): """ Connect response data on inputs of frame forge :param resp: registers with response data :param forgeIn: input interface of frame forge :param sendingRepply: flag which signalizes that data should be forged into frame and send """ t = resp._dtype if isinstance(t, Bits): forgeIn.data(resp) forgeIn.vld(sendingReply) else: for f in t.fields: name = f.name In = getattr(resp, name) # switch dst and src if name == "src": name = "dst" elif name == "dst": name = "src" Out = getattr(forgeIn, name) self.connect_resp(In, Out, sendingReply) def icmp_checksum(self, header): """ :note: we do not need to care about endianity because parser/forge will swap it for us and we can work with little endians only :return: checksum for icmp header """ # type, code, checksum = 0 return ~(header.identifier + header.seqNo ) def _impl(self): # tmp registers sendingReply = self._reg("sendingReply", defVal=0) resp = self._reg("resp", echoFrame_t) isEchoReq = self._reg("isEchoReq", defVal=0) # set fields of reply resp.icmp.type = resp.icmp.type._dtype.fromPy(ICMP_TYPE.ECHO_REPLY) resp.icmp.code = resp.icmp.code._dtype.fromPy(0) resp.icmp.checksum = self.icmp_checksum(resp.icmp) # parse input frame parsed = AxiSBuilder(self, self.rx).parse(echoFrame_t) self.req_load(parsed, resp, sendingReply) t = parsed.icmp.type If(t.vld, isEchoReq(t.data._eq(ICMP_TYPE.ECHO_REQUEST)) ) def setup_frame_forge(out): out.DATA_WIDTH.set(self.DATA_WIDTH) out.IS_BIGENDIAN.set(self.IS_BIGENDIAN) # create output frame txBuilder, forgeIn = AxiSBuilder.forge(self, echoFrame_t, AxiStream, setup_frame_forge) self.connect_resp(resp, forgeIn, sendingReply) tx = txBuilder.end self.tx(tx) # update state flags If(self.rx.last & self.rx.valid, sendingReply(self.myIp._eq(resp.ip.dst) & isEchoReq) ).Elif(tx.valid & tx.last, sendingReply(0) )