def _declr(self): addClkRst(self) self.en_mult = Signal() self.en_sum = Signal() self.input = VectSignal(self.INPUT_WIDTH * self.SIZE) self.output = VectSignal(self.width, signed=True)._m() self.kernel_abs = VectSignal(self.width) self.kernel_sig = VectSignal(self.SIZE) name = f"BinConvUnitL{self.layer_id}" self._name = name self._hdl_module_name = name
def _declr(self): addClkRst(self) self.ram0 = BramPort() self.ram1 = BramPort()._m() self.uart = Uart()._m() self.hsIn = Handshaked_withIP() self.hsOut = Handshaked_withIP()._m() self.difIn = DifferentialSig() self.axi3s0 = Axi3() self.axi3m0 = Axi3()._m() self.axi3s1 = Axi3() self.axi3m1 = Axi3()._m() for i in [self.axi3s1, self.axi3m1]: i.ADDR_USER_WIDTH.set(10)
def _declr(self): addClkRst(self) self._declr_ports() r_ports = [] w_ports = [] rw_ports = [] for p in self.port: if p.HAS_R and p.HAS_W: rw_ports.append(p) else: if p.HAS_R: r_ports.append(p) if p.HAS_W: w_ports.append(p) self._r_ports = r_ports self._w_ports = w_ports self._rw_ports = rw_ports primitive_ram_r_port_i = [] primitive_ram_w_port_i = [] primitive_ram_rw_port_i = [] if isinstance(self.PRIMITIVE_MEMORY_PORTS, int): primitive_ram_rw_port_i = list(range(self.PRIMITIVE_MEMORY_PORTS)) else: for i, p in enumerate(self.PRIMITIVE_MEMORY_PORTS): if p == READ: primitive_ram_r_port_i.append(i) elif p == WRITE: primitive_ram_w_port_i.append(i) elif p == READ_WRITE: primitive_ram_rw_port_i.append(i) else: raise NotImplementedError(p) can_be_primitive_ram = len(rw_ports) <= len(primitive_ram_rw_port_i) and \ len(r_ports) <= len(primitive_ram_r_port_i) and \ len(w_ports) <= len(primitive_ram_w_port_i) self._can_be_primitive_ram = can_be_primitive_ram if can_be_primitive_ram: self._declr_children()
def _declr(self): addClkRst(self) self.en_mult = Signal() self.en_sum = Signal() self.en_channel = Signal() self.en_batch = Signal() self.en_act = Signal() self.input = VectSignal(self.size * self.channels * self.INPUT_WIDTH) self.output = VectSignal(self.filters * self.OUTPUT_WIDTH)._m() if self.top_entity: output_width = int( self.filters / self.parallelism) * self.OUTPUT_WIDTH # instantiate empty ConvLayerPart self.conv_layer_part = HObjList( ConvLayerPart( input_width=self.size * self.channels * self.INPUT_WIDTH, output_width=output_width, layer_id=self.layer_id, process_id=i, log_level=0, ) for i in range(self.parallelism)) name = f"ConvLayerL{self.layer_id}" else: # instantiate dynamically multichannel units self.conv_layer_part = HObjList( MultiChannelConvUnit( layer_id=self.layer_id, unit_id=i, width=self.width, channels=self.channels, binary=self.binary, size=self.size, bin_input=self.bin_input, bin_output=self.bin_output, process_id=self.process_id, log_level=self.log_level + 1, ) for i in range(self.filters)) name = f"ConvLayerL{self.layer_id}P{self.process_id}" self._hdl_module_name = name self._name = name
def _declr(self): addClkRst(self) self.en = Signal() self.val = VectSignal(self.DATA_WIDTH)._m()
def _declr(self): addClkRst(self) self.ack = Signal() self.vld = Signal() self.rd = Signal()._m()
def _declr(self): addClkRst(self) self.din = Signal(dtype=BIT) self.dout = VectSignal(2)._m()
def _declr(self): addClkRst(self) self.din = Signal() self.dout = Signal()._m()
def _declr(self): addClkRst(self) self.en_mult = Signal() self.en_sum = Signal() self.en_channel = Signal() self.en_batch = Signal() self.en_act = Signal() self.input = VectSignal(self.size * self.channels * self.INPUT_WIDTH) self.output = VectSignal(self.OUTPUT_WIDTH, signed=True)._m() self.ssi_coef = VectSignal(self.INPUT_WIDTH) self.bn_coef = VectSignal(self.INPUT_WIDTH) # self.multiplier = FixedPointMultiplier( # width=self.width, # layer_id=self.layer_id, # unit_id=self.unit_id, # channel_id=self.channel_id, # process_id=self.process_id, # pixel_id=0, # log_level=self.log_level + 1, # ) conv_units_list = [] # instantiate binary conv unit if it is setted if self.binary: for i in range(self.channels): setattr(self, f'kernel_abs_{i}', VectSignal(self.width)) setattr(self, f'kernel_sig_{i}', VectSignal(self.size)) conv_unit = BinConvUnit( layer_id=self.layer_id, channel_id=i, unit_id=self.unit_id, bin_input=self.bin_input, width=self.width, size=self.size, process_id=self.process_id, log_level=self.log_level + 1, ) conv_units_list.append(conv_unit) else: for i in range(self.channels): for j in range(self.size): setattr(self, f'kernel_{i*self.size+j}', VectSignal(self.width)) conv_unit = ConvUnit( layer_id=self.layer_id, channel_id=i, unit_id=self.unit_id, bin_input=self.bin_input, width=self.width, size=self.size, process_id=self.process_id, log_level=self.log_level + 1, ) conv_units_list.append(conv_unit) self.conv_units = HObjList(conv_units_list) name = f"MultiChannelConvUnitL{self.layer_id}" self._name = name self._hdl_module_name = name
def _declr(self): addClkRst(self) self.din = BramPort_withoutClk() self.dout = BramPort_withoutClk()._m()