def Component(cls, entity, ctx): with CurrentUnitSwap(ctx, entity.origin): return cls.componentTmpl.render( indent=getIndent(ctx.indent), ports=[cls.PortItem(pi, ctx) for pi in entity.ports], generics=[cls.GenericItem(g, ctx) for g in entity.generics], entity=entity)
def Architecture(cls, arch: Architecture, ctx): with CurrentUnitSwap(ctx, arch.entity.origin): variables = [] procs = [] extraTypes = set() extraTypes_serialized = [] arch.variables.sort(key=lambda x: (x.name, x._instId)) arch.processes.sort(key=lambda x: (x.name, maxStmId(x))) arch.components.sort(key=lambda x: x.name) arch.componentInstances.sort(key=lambda x: x._name) childCtx = ctx.withIndent() for v in arch.variables: t = v._dtype # if type requires extra definition if isinstance(t, (HEnum, HArray)) and t not in extraTypes: extraTypes.add(v._dtype) extraTypes_serialized.append( cls.HdlType(t, childCtx, declaration=True)) v.name = ctx.scope.checkedName(v.name, v) serializedVar = cls.SignalItem(v, childCtx, declaration=True) variables.append(serializedVar) for p in arch.processes: procs.append(cls.HWProcess(p, childCtx)) # architecture names can be same for different entities # arch.name = scope.checkedName(arch.name, arch, isGlobal=True) uniqComponents = list( map(lambda x: x[1][0], groupedby(arch.components, lambda c: c.name))) uniqComponents.sort(key=lambda c: c.name) components = list( map(lambda c: cls.Component(c, childCtx), uniqComponents)) componentInstances = list( map(lambda c: cls.ComponentInstance(c, childCtx), arch.componentInstances)) return cls.architectureTmpl.render( indent=getIndent(ctx.indent), entityName=arch.getEntityName(), name=arch.name, variables=variables, extraTypes=extraTypes_serialized, processes=procs, components=components, componentInstances=componentInstances)
def Entity(cls, entity: Entity, ctx): with CurrentUnitSwap(ctx, entity.origin): generics, ports = cls.Entity_prepare(entity, ctx) entVhdl = cls.entityTmpl.render(indent=getIndent(ctx.indent), name=entity.name, ports=ports, generics=generics) doc = entity.__doc__ if doc and id(doc) != id(Entity.__doc__): doc = cls.comment(doc) + "\n" return doc + entVhdl else: return entVhdl
def ComponentInstance(cls, entity, ctx: VerilogSerializerCtx): with CurrentUnitSwap(ctx, entity.origin): portMaps = [] for pi in entity.ports: pm = PortMap.fromPortItem(pi) portMaps.append(pm) genericMaps = [] for g in entity.generics: gm = MapExpr(g, g._val) genericMaps.append(gm) if len(portMaps) == 0: raise SerializerException("Incomplete component instance") # [TODO] check component instance name return cls.componentInstanceTmpl.render( indent=getIndent(ctx.indent), instanceName=entity._name, entity=entity, portMaps=[cls.PortConnection(x, ctx) for x in portMaps], genericMaps=[cls.MapExpr(x, ctx) for x in genericMaps])