def serializeAsIpcore(unit, folderName=".", name=None, serializer: GenericSerializer=VhdlSerializer, targetPlatform=DummyPlatform()): from hwt.serializer.ip_packager import IpPackager p = IpPackager(unit, name=name, serializer=serializer, targetPlatform=targetPlatform) p.createPackage(folderName) return p
def serializeAsIpcore(unit, folderName=".", name=None, serializer_cls=Vhdl2008Serializer, target_platform=DummyPlatform()): """ Create an IPCore package """ from hwt.serializer.ip_packager import IpPackager p = IpPackager(unit, name=name, serializer_cls=serializer_cls, target_platform=target_platform) p.createPackage(folderName) return p
def asQuartusTcl(self, buff: List[str], version: str, component: Component, packager: IpPackager, thisIf: Interface): self.quartus_tcl_add_interface(buff, thisIf, packager) name = packager.getInterfacePhysicalName(thisIf) # self.quartus_prop("associatedClock", clock) self.quartus_prop(buff, name, "synchronousEdges", "DEASSERT") self.quartus_add_interface_port(buff, name, thisIf, "reset", packager) clk = thisIf._getAssociatedClk() if clk is not None: self.quartus_prop(buff, name, "associatedClock", packager.getInterfacePhysicalName(clk), escapeStr=False)
def postProcess(self, component: Component, packager: IpPackager, thisIf: Axi3Lite): self.endianness = "little" thisIntfName = packager.getInterfaceLogicalName(thisIf) self.addWidthParam(thisIntfName, "ADDR_WIDTH", thisIf.ADDR_WIDTH, packager) self.addWidthParam(thisIntfName, "DATA_WIDTH", thisIf.DATA_WIDTH, packager) self.addSimpleParam(thisIntfName, "PROTOCOL", "AXI4LITE") self.addSimpleParam(thisIntfName, "READ_WRITE_MODE", "READ_WRITE")
def postProcess(self, component: Component, packager: IpPackager, thisIf: Axi3Lite): self.endianness = "little" thisIntfName = packager.getInterfaceLogicalName(thisIf) self.addWidthParam(thisIntfName, "ADDR_WIDTH", thisIf.ADDR_WIDTH, packager) self.addWidthParam(thisIntfName, "DATA_WIDTH", thisIf.DATA_WIDTH, packager) self.addSimpleParam(thisIntfName, "PROTOCOL", "AXI4LITE") self.addSimpleParam(thisIntfName, "READ_WRITE_MODE", "READ_WRITE")
def postProcess(self, component: Component, packager: IpPackager, thisIf: Axi3): self.endianness = "little" thisIntfName = packager.getInterfaceLogicalName(thisIf) def param(name, val): return self.addSimpleParam(thisIntfName, name, str(val)) # [TODO] width as expression instead of int param("ADDR_WIDTH", thisIf.aw.addr._dtype.bit_length()) param("MAX_BURST_LENGTH", int(2**thisIf.aw.len._dtype.bit_length())) param("NUM_READ_OUTSTANDING", 5) param("NUM_WRITE_OUTSTANDING", 5) param("PROTOCOL", self.xilinx_protocol_name) param("READ_WRITE_MODE", "READ_WRITE") param("SUPPORTS_NARROW_BURST", 0) A_U_W = int(thisIf.ADDR_USER_WIDTH) if A_U_W: param("AWUSER_WIDTH", A_U_W) param("ARUSER_WIDTH", A_U_W)
def postProcess(self, component: Component, packager: IpPackager, thisIf: Rst_n): self.addSimpleParam(packager.getInterfaceLogicalName(thisIf), "POLARITY", "ACTIVE_LOW")
def asQuartusTcl(self, buff: List[str], version: str, component: Component, packager: IpPackager, thisIf: Interface): self.quartus_tcl_add_interface(buff, thisIf, packager) name = packager.getInterfacePhysicalName(thisIf) self.quartus_prop(buff, name, "clockRate", 0) self.quartus_add_interface_port(buff, name, thisIf, "clk", packager)
#!/usr/bin/env python3 # -*- coding: utf-8 -*- from hwt.interfaces.std import Signal from hwt.synthesizer.unit import Unit class SimpleUnit(Unit): def _declr(self): self.a = Signal() self.b = Signal()._m() def _impl(self): self.b(self.a) if __name__ == "__main__": # alias python main function from hwt.serializer.vhdl.serializer import VhdlSerializer from hwt.serializer.ip_packager import IpPackager from os.path import expanduser # create instance of Unit (unit is like verilog module) u = SimpleUnit() # create instace of IpPackager and configure it # if name is not specified name will be name of Unit class p = IpPackager(u, serializer=VhdlSerializer) # generate IP-core package p.createPackage(expanduser("~/Documents/ip_repo"))