def test_writeAndRead(self):
u = Ram_sp()
u.DATA_WIDTH.set(8)
u.ADDR_WIDTH.set(3)
self.prepareUnit(u)
u.a._ag.requests.extend([(WRITE, 0, 5), (WRITE, 1, 7), (READ, 0),
(READ, 1), (READ, 0), (READ, 1), (READ, 2)])
self.runSim(110 * Time.ns)
self.assertSequenceEqual(valuesToInts(self.model.ram_memory._val),
[5, 7, None, None, None, None, None, None])
self.assertSequenceEqual(valuesToInts(u.a._ag.readed),
[5, 7, 5, 7, None])
def test_writeAndRead(self):
u = Ram_sp()
u.DATA_WIDTH.set(8)
u.ADDR_WIDTH.set(3)
self.prepareUnit(u)
u.a._ag.requests.extend([(WRITE, 0, 5), (WRITE, 1, 7),
(READ, 0), (READ, 1),
(READ, 0), (READ, 1), (READ, 2)])
self.runSim(110 * Time.ns)
self.assertSequenceEqual(valuesToInts(self.model.ram_memory._val),
[5, 7, None, None, None, None, None, None])
self.assertSequenceEqual(valuesToInts(u.a._ag.readed),
[5, 7, 5, 7, None])
def test_writeAndRead(self):
u = RAM64X1S()
self.prepareUnit(u)
requests = [(WRITE, 0, 0), (WRITE, 1, 1), (READ, 0), (READ, 1),
(READ, 2), (READ, 3), (READ, 2)]
applyRequests(u, requests)
self.runSim(80 * Time.ns)
self.assertSequenceEqual(valuesToInts(u.o._ag.data),
[0, 0, 0, 1, 0, 0, 0, 0])
def test_writeAndRead(self):
u = RAM64X1S()
self.prepareUnit(u)
requests = [(WRITE, 0, 0), (WRITE, 1, 1),
(READ, 0), (READ, 1),
(READ, 2), (READ, 3), (READ, 2)]
applyRequests(u, requests)
self.runSim(80 * Time.ns)
self.assertSequenceEqual(valuesToInts(u.o._ag.data),
[0, 0, 0, 1, 0, 0, 0, 0])
def test_writeAndMatchTest(self):
u = Cam()
self.prepareUnit(u)
m = mask(36)
u.write._ag.data.extend([(0, 1, m), (1, 3, m), (7, 11, m)])
u.match._ag.data.extend([NOP, NOP, NOP, 1, 2, 3, 5, 11, 12])
self.runSim(160 * Time.ns)
self.assertSequenceEqual(valuesToInts(u.out._ag.data),
[1, 0, 2, 0, 128, 0])
def test_sync_allData(self):
self.setUpSync()
u = self.u
u.addr_in._ag.data.extend([0, 1, 2, 3, None, 3, 2, 1])
u.addr_out._ag.data.extend([None, 0, 1, 2, 3, None, 0, 1])
u.din._ag.data.extend([10, 11, 12, 13, 14, 15, 16, 17])
self.runSim(80 * Time.ns)
self.assertSequenceEqual(valuesToInts([v for v in self.model.ram_data._val]),
[None, 17, 16, 15])
self.assertSequenceEqual(agInts(u.dout),
[None, None, 10, 11, 12, 13, None, None])
def test_normalOp(self):
u = self.u
expected = [0, 0, 0, None, 0, 1, 2, 3, 4]
def dataInStimul(s):
yield s.wait(3 * CLK_PERIOD)
for i in range(127):
s.write(i, u.inData)
yield s.wait(CLK_PERIOD)
collected = self.runSim(dataInStimul, "normalOp")
self.assertSequenceEqual(expected, valuesToInts(collected))
def test_normalOp(self):
u = self.u
expected = [0, 0, 0, None, 0, 1, 2, 3, 4]
def dataInStimul(s):
yield s.wait(3 * CLK_PERIOD)
for i in range(127):
s.write(i, u.inData)
yield s.wait(CLK_PERIOD)
collected = self.runSim(dataInStimul, "normalOp")
self.assertSequenceEqual(expected, valuesToInts(collected))
def test_sync_allData(self):
self.setUpSync()
u = self.u
u.addr_in._ag.data.extend([0, 1, 2, 3, None, 3, 2, 1])
u.addr_out._ag.data.extend([None, 0, 1, 2, 3, None, 0, 1])
u.din._ag.data.extend([10, 11, 12, 13, 14, 15, 16, 17])
self.runSim(80 * Time.ns)
self.assertSequenceEqual(
valuesToInts([v for v in self.model.ram_data._val]),
[None, 17, 16, 15])
self.assertSequenceEqual(agInts(u.dout),
[None, None, 10, 11, 12, 13, None, None])
def test_writeAndMatchTest(self):
u = Cam()
self.prepareUnit(u)
m = mask(36)
u.write._ag.data.extend([(0, 1, m),
(1, 3, m),
(7, 11, m)])
u.match._ag.data.extend([NOP, NOP, NOP, 1, 2, 3, 5, 11, 12])
self.runSim(160 * Time.ns)
self.assertSequenceEqual(valuesToInts(u.out._ag.data),
[1, 0, 2, 0, 128, 0])
def test_invalidData(self):
u = self.u
CLK_PERIOD = 10 * Time.ns
expected = [0, 0, 0, None, None, None, None, None, None]
def dataInStimul(s):
yield s.wait(3 * CLK_PERIOD)
for _ in range(127):
yield s.wait(CLK_PERIOD)
s.write(None, u.inData)
collected = self.runSim(dataInStimul, "invalidData")
self.assertSequenceEqual(expected, valuesToInts(collected))
def test_invalidData(self):
u = self.u
CLK_PERIOD = 10 * Time.ns
expected = [0, 0, 0, None, None, None, None, None, None]
def dataInStimul(s):
yield s.wait(3 * CLK_PERIOD)
for _ in range(127):
yield s.wait(CLK_PERIOD)
s.write(None, u.inData)
collected = self.runSim(dataInStimul, "invalidData")
self.assertSequenceEqual(expected, valuesToInts(collected))
def test_randomized(self):
u = self.u
N = 8
expected = []
for i, inp in enumerate(u.dataIn):
self.randomize(inp)
d = [i * N + i2 + 1 for i2 in range(N)]
inp._ag.data.extend(d)
expected.extend(d)
self.randomize(u.dataOut)
self.runSim(self.INPUTS * N * 50 * Time.ns)
self.assertEqual(set(valuesToInts(u.dataOut._ag.data)), set(expected))
def test_randomized(self):
u = self.u
N = 8
expected = []
for i, inp in enumerate(u.dataIn):
self.randomize(inp)
d = [i * N + i2 + 1 for i2 in range(N)]
inp._ag.data.extend(d)
expected.extend(d)
self.randomize(u.dataOut)
self.runSim(self.INPUTS * N * 50 * Time.ns)
self.assertEqual(set(valuesToInts(u.dataOut._ag.data)),
set(expected))
def test_write(self):
u = self.u
axi = u.axi._ag
axi.aw.data += [(0, 0), (4, 0)]
axi.w.data += [(11, allMask), (37, allMask)]
self.runSim(250 * Time.ns)
self.assertEmpty(axi.aw.data)
self.assertEmpty(axi.w.data)
self.assertEmpty(u.axi._ag.r.data)
self.assertEqual(len(u.axi._ag.b.data), 2)
model = self.model
self.assertEqual(valuesToInts([model.reg0._oldVal, model.reg1._oldVal]),
[11, 37])
def tryInsertNotFoundAndLookupIt(s):
# wait for lookup
yield s.wait(50 * Time.ns)
_hash, key, _, found, occupied = u.lookupRes._ag.data.popleft()
data = self._rand.getrandbits(8)
self.assertValEqual(found, False)
self.assertValEqual(occupied, False)
u.insert._ag.data.append((_hash, key, data, 1))
yield s.wait(50 * Time.ns)
key2 = self._rand.getrandbits(16)
u.lookup._ag.data.extend([key, key2])
yield s.wait(50 * Time.ns)
expected0 = tuple(valuesToInts((_hash, key, data, 1, 1)))
expected1 = (14, key2, 0, 0, 0)
self.assertValSequenceEqual(u.lookupRes._ag.data,
[expected0, expected1])