def test_resources_b(self): u = ListOfInterfacesSample3b() expected = {} s = ResourceAnalyzer() toRtl(u, serializer=s) self.assertDictEqual(s.report(), expected)
def test_resources_b(self): u = ListOfInterfacesSample3b() expected = {} s = ResourceAnalyzer() toRtl(u, serializer=s) self.assertDictEqual(s.report(), expected)
def test_resources(self): u = SwitchStmUnit() expected = {(ResourceMUX, 1, 4): 1} s = ResourceAnalyzer() toRtl(u, serializer=s) r = s.report() self.assertDictEqual(r, expected)
def test_resources_SimpleIfStatement3(self): u = SimpleIfStatement3() expected = {} s = ResourceAnalyzer() toRtl(u, serializer=s) r = s.report() self.assertDictEqual(r, expected)
def test_BoolToBits(self): u = BoolToBitTest() ra = ResourceAnalyzer() toRtl(u, serializer=ra) res = ra.report() expected = { (AllOps.EQ, 4): 1, } self.assertDictEqual(res, expected)
def test_resources(self): u = SwitchStmUnit() expected = {(ResourceMUX, 1, 4): 1} s = ResourceAnalyzer() toRtl(u, serializer=s) r = s.report() self.assertDictEqual(r, expected)
def test_latch_resources(self): u = Latch() expected = { ResourceLatch: 1, } s = ResourceAnalyzer() toRtl(u, serializer=s) self.assertDictEqual(s.report(), expected)
def test_sync_resources(self): u = SimpleSyncRom() expected = { ResourceRAM(8, 4, 0, 1, 0, 0, 0, 0, 0, 0): 1, } s = ResourceAnalyzer() toRtl(u, serializer=s) self.assertDictEqual(s.report(), expected)
def test_resources_SimpleIfStatement3(self): u = SimpleIfStatement3() expected = { } s = ResourceAnalyzer() toRtl(u, serializer=s) r = s.report() self.assertDictEqual(r, expected)
def test_latch_in_switch(self): u = LatchInSwitchTest() ra = ResourceAnalyzer() toRtl(u, serializer=ra) res = ra.report() expected = { (ResourceMUX, 4, 6): 1, ResourceLatch: 4 } self.assertDictEqual(res, expected)
def test_sync_resources(self): u = SimpleSyncRom() expected = { ResourceRAM(8, 4, 0, 1, 0, 0, 0, 0, 0, 0): 1, } s = ResourceAnalyzer() toRtl(u, serializer=s) self.assertDictEqual(s.report(), expected)
def test_resources_2b(self): u = Cntr() expected = {(AllOps.ADD, 2): 1, # 1 for reset, one for en (ResourceMUX, 2, 2): 2, ResourceFF: 2} s = ResourceAnalyzer() toRtl(u, serializer=s) r = s.report() self.assertDictEqual(r, expected)
def test_resources_150b(self): u = Cntr() u.DATA_WIDTH.set(150) expected = {(AllOps.ADD, 150): 1, # 1 for reset, one for en (ResourceMUX, 150, 2): 2, ResourceFF: 150} s = ResourceAnalyzer() toRtl(u, serializer=s) r = s.report() self.assertDictEqual(r, expected)
def test_resources_2b(self): u = Cntr() expected = { (AllOps.ADD, 2): 1, # 1 for reset, one for en (ResourceMUX, 2, 2): 2, ResourceFF: 2 } s = ResourceAnalyzer() toRtl(u, serializer=s) r = s.report() self.assertDictEqual(r, expected)
def test_resources_150b(self): u = Cntr() u.DATA_WIDTH.set(150) expected = { (AllOps.ADD, 150): 1, # 1 for reset, one for en (ResourceMUX, 150, 2): 2, ResourceFF: 150 } s = ResourceAnalyzer() toRtl(u, serializer=s) r = s.report() self.assertDictEqual(r, expected)
def test_resources_SimpleIfStatement2c(self): u = SimpleIfStatement2c() expected = { (AllOps.AND, 1): 1, (AllOps.EQ, 1): 1, (ResourceMUX, 2, 2): 1, (ResourceMUX, 2, 4): 1, ResourceFF: 2, } s = ResourceAnalyzer() toRtl(u, serializer=s) r = s.report() self.assertDictEqual(r, expected)
def test_resources_SimpleIfStatement2c(self): u = SimpleIfStatement2c() expected = { (AllOps.AND, 1): 1, (AllOps.EQ, 1): 1, (ResourceMUX, 2, 2): 1, (ResourceMUX, 2, 4): 1, ResourceFF: 2, } s = ResourceAnalyzer() toRtl(u, serializer=s) r = s.report() self.assertDictEqual(r, expected)
def toSimModel(unit, targetPlatform=DummyPlatform(), dumpModelIn=None): """ Create a simulation model for unit :param unit: interface level unit which you wont prepare for simulation :param targetPlatform: target platform for this synthes :param dumpModelIn: folder to where put sim model files (otherwise sim model will be constructed only in memory) """ sim_code = toRtl(unit, targetPlatform=targetPlatform, saveTo=dumpModelIn, serializer=SimModelSerializer) if dumpModelIn is not None: d = os.path.join(os.getcwd(), dumpModelIn) dInPath = d in sys.path if not dInPath: sys.path.insert(0, d) if unit._name in sys.modules: del sys.modules[unit._name] simModule = importlib.import_module(unit._name) if not dInPath: sys.path.remove(d) else: simModule = ModuleType('simModule') # python supports only ~100 opened brackets # it exceded it throws MemoryError: s_push: parser stack overflow exec(sim_code, simModule.__dict__) return simModule.__dict__[unit._name]
def toBasicSimulatorSimModel(unit: Unit, unique_name: str, build_dir: Optional[str], target_platform=DummyPlatform(), do_compile=True): """ Create a pycocotb.basic_hdl_simulator based simulation model for specified unit and load it to python :param unit: interface level unit which you wont prepare for simulation :param unique_name: unique name for build directory and python module with simulator :param target_platform: target platform for this synthesis :param build_dir: directory to store sim model build files, if None sim model will be constructed only in memory """ if unique_name is None: unique_name = unit._getDefaultName() if build_dir is not None: build_private_dir = os.path.join(os.getcwd(), build_dir, unique_name) else: build_private_dir = None sim_code = toRtl(unit, name=unique_name, targetPlatform=target_platform, saveTo=build_private_dir, serializer=SimModelSerializer) if build_dir is not None: d = os.path.join(os.getcwd(), build_dir) dInPath = d in sys.path if not dInPath: sys.path.insert(0, d) if unique_name in sys.modules: del sys.modules[unique_name] simModule = importlib.import_module(unique_name + "." + unique_name, package='simModule_' + unique_name) if not dInPath: sys.path.pop(0) else: simModule = ModuleType('simModule_' + unique_name) # python supports only ~100 opened brackets # if exceded it throws MemoryError: s_push: parser stack overflow exec(sim_code, simModule.__dict__) model_cls = simModule.__dict__[unit._name] # can not use just function as it would get bounded to class return BasicSimConstructor(model_cls, unit)
def toHdlConversion(self, top, topName: str, saveTo: str) -> List[str]: """ :param top: object which is represenation of design :param topName: name which should be used for ipcore :param saveTo: path of directory where generated files should be stored :return: list of file namens in correct compile order """ return toRtl(top, saveTo=saveTo, name=topName, serializer=self.serializer, targetPlatform=self.targetPlatform)
def toVerilatorSimModel(unit: Unit, unique_name: str, build_dir: Optional[str], target_platform=DummyPlatform(), do_compile=True): """ Create a verilator based simulation model for specified unit and load it to Python :param unit: interface level unit which you wont prepare for simulation :param unique_name: unique name for build directory and python module with simulator :param target_platform: target platform for this synthesis :param build_dir: directory to store sim model build files, if None temporary folder is used and then deleted :param do_compile: if false reuse existing build if exists [TODO] """ if build_dir is None: build_dir = "tmp/%s" % unique_name # with tempdir(suffix=unique_name) as build_dir: sim_verilog = toRtl(unit, targetPlatform=target_platform, saveTo=build_dir, serializer=VerilogForVerilatorSerializer) accessible_signals = collect_signals(unit) used_names = {x[0] for x in accessible_signals} assert len(used_names) == len(accessible_signals), \ "All signal has to have unique names" if do_compile: verilatorCompile(sim_verilog, build_dir) sim_so = generatePythonModuleWrapper(unit._name, unique_name, build_dir, accessible_signals) else: sim_so = None file_pattern = './**/{0}.*.so'.format(unique_name) for filename in iglob(file_pattern, recursive=True): assert sim_so is None, ("Can not resolve simulation library", sim_so, filename) sim_so = filename # load compiled library into python sim_module = loadPythonCExtensionFromFile(sim_so, unique_name) sim_cls = getattr(sim_module, unique_name) return sim_cls
def test_SubunitWithWrongDataT(self): class InternUnit(Unit): def _declr(self): dt = Bits(64) self.a = Signal(dtype=dt) self.b = Signal(dtype=dt)._m() def _impl(self): self.b(self.a) class OuterUnit(Unit): def _declr(self): dt = Bits(32) self.a = Signal(dtype=dt) self.b = Signal(dtype=dt) self.iu = InternUnit() def _impl(self): self.iu.a(self.a) self.b(self.iu.b) self.assertRaises(TypeConversionErr, lambda: toRtl(OuterUnit))
def test_SubunitWithWrongDataT(self): class InternUnit(Unit): def _declr(self): dt = Bits(64) self.a = Signal(dtype=dt) self.b = Signal(dtype=dt)._m() def _impl(self): self.b(self.a) class OuterUnit(Unit): def _declr(self): dt = Bits(32) self.a = Signal(dtype=dt) self.b = Signal(dtype=dt) self.iu = InternUnit() def _impl(self): self.iu.a(self.a) self.b(self.iu.b) self.assertRaises(TypeConversionErr, lambda: toRtl(OuterUnit))
def saveHdlFiles(self, srcDir): path = os.path.join(srcDir, self.name) try: os.makedirs(path) except OSError: # wipe if exists shutil.rmtree(path) os.makedirs(path) files = self.hdlFiles self.hdlFiles = toRtl(self.topUnit, saveTo=path, name=self.name, serializer=self.serializer, targetPlatform=self.targetPlatform) for srcF in files: dst = os.path.join( path, os.path.relpath(srcF, srcDir).replace('../', '')) os.makedirs(os.path.dirname(dst), exist_ok=True) shutil.copy(srcF, dst) self.hdlFiles.append(dst)
self.DATA_WIDTH = int(self.DATA_WIDTH) vldAll = mask(self.DATA_WIDTH // 8) dout = self.dataOut DATA_LEN = len(self.DATA) wordIndex_w = int(math.log2(DATA_LEN) + 1) wordIndex = self._reg("wordIndex", Bits(wordIndex_w), defVal=0) Switch(wordIndex)\ .addCases([(i, dout.data(d)) for i, d in enumerate(self.DATA)])\ .Default(dout.data(None)) dout.last(wordIndex._eq(DATA_LEN - 1)) If(wordIndex < DATA_LEN, dout.strb(vldAll), dout.valid(1) ).Else( dout.strb(None), dout.valid(0) ) If(self.dataRd(), self.nextWordIndexLogic(wordIndex) ) if __name__ == "__main__": from hwt.synthesizer.utils import toRtl print(toRtl(AxiSStoredBurst))
""" def _declr(self): self.addr = VectSignal(2) self.dout = VectSignal(8)._m() def _impl(self): rom = self._sig("rom_data", Bits(8)[4], defVal=[1, 2, 3, 4]) self.dout(rom[self.addr]) class SimpleSyncRom(SimpleRom): """ .. hwt-schematic:: """ def _declr(self): super()._declr() self.clk = Clk() def _impl(self): rom = self._sig("rom_data", Bits(8)[4], defVal=[1, 2, 3, 4]) If(self.clk._onRisingEdge(), self.dout(rom[self.addr]) ) if __name__ == "__main__": # alias python main function from hwt.synthesizer.utils import toRtl # there is more of synthesis methods. toRtl() returns formated vhdl string print(toRtl(SimpleSyncRom()))
def test_hwt(self): s = toRtl(Showcase0(), serializer=HwtSerializer) showcase0_hwt = readContent("showcase0.hwt.py") self.assertEqual(s, showcase0_hwt)
# t = HUnion( # (uint32_t, "a"), # (int32_t, "b") # ) t = HUnion( (HStruct( (uint64_t, "itemA0"), (uint64_t, "itemA1") ), "frameA"), (HStruct( (uint32_t, "itemB0"), (uint32_t, "itemB1"), (uint32_t, "itemB2"), (uint32_t, "itemB3") ), "frameB") ) u = AxiS_frameParser(t) u.DATA_WIDTH.set(64) return u if __name__ == "__main__": from hwt.synthesizer.utils import toRtl u = _example_AxiS_frameParser() print( toRtl(u) )
self.a = Signal() self.c = Signal()._m() def _impl(self): self.b = Signal() self.b(self.a) self.c(self.b) class SimpleWithNonDirectIntConncetionTC(SimTestCase): def test_passData(self): u = SimpleWithNonDirectIntConncetion() self.prepareUnit(u) d = [0, 1, 0, 1, 0] u.a._ag.data.extend(d) self.runSim(50 * Time.ns) self.assertValSequenceEqual(u.c._ag.data, d) if __name__ == "__main__": import unittest suite = unittest.TestSuite() # suite.addTest(SimpleWithNonDirectIntConncetionTC('test_passData')) suite.addTest(unittest.makeSuite(SimpleWithNonDirectIntConncetionTC)) runner = unittest.TextTestRunner(verbosity=3) runner.run(suite) from hwt.synthesizer.utils import toRtl print(toRtl(SimpleWithNonDirectIntConncetion()))
# 1 0b1001111, # 2 0b0010010, # 3 0b0000110, # 4 0b1001100, # 5 0b0100100, # 6 0b0100000, # 7 0b0001111, # 8 0b0000000, # 9 0b0000100, ] Switch(self.dataIn) \ .addCases(enumerate([self.dataOut(v) for v in dec])) \ .Default( # display off when value is out of range self.dataOut(0b1111111) ) if __name__ == "__main__": from hwt.synthesizer.utils import toRtl print(toRtl(Segment7()))
def test_add_to_slice_vhdl(self): s = toRtl(TernaryInConcatExample(), serializer=VhdlSerializer) self.assertEqual(s, TernaryInConcatExample_asVhdl)
self.rst = Rst() self.inData = Signal(dtype=self.DATA_TYP) self.inClk = Clk() self.outData = Signal(dtype=self.DATA_TYP)._m() self.outClk = Clk() def _impl(self): def reg(name, clk): return self._reg(name, self.DATA_TYP, clk=clk, rst=self.rst, defVal=0) inReg = reg("inReg", self.inClk) outReg0 = reg("outReg0", self.outClk) outReg1 = reg("outReg1", self.outClk) inReg(self.inData) outReg0(inReg) outReg1(outReg0) self.outData(outReg1) if __name__ == "__main__": from hwt.synthesizer.utils import toRtl print(toRtl(ClkSynchronizer))
SimpleComentedUnit3.__doc__ = "dynamically generated, for example loaded from file or builded from unit content" simpleComentedUnit3Expected = \ """ --dynamically generated, for example loaded from file or builded from unit content library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ENTITY SimpleComentedUnit3 IS PORT (a: IN STD_LOGIC; b: OUT STD_LOGIC ); END SimpleComentedUnit3; ARCHITECTURE rtl OF SimpleComentedUnit3 IS BEGIN b <= a; END ARCHITECTURE rtl; """ if __name__ == "__main__": print(toRtl(SimpleComentedUnit)) print(toRtl(SimpleComentedUnit2)) print(toRtl(SimpleComentedUnit3))
0b1001111, # 2 0b0010010, # 3 0b0000110, # 4 0b1001100, # 5 0b0100100, # 6 0b0100000, # 7 0b0001111, # 8 0b0000000, # 9 0b0000100, ] Switch(self.dataIn) \ .addCases(enumerate([self.dataOut(v) for v in dec])) \ .Default( # display off when value is out of range self.dataOut(0b1111111) ) if __name__ == "__main__": from hwt.synthesizer.utils import toRtl print(toRtl(Segment7()))
def test_accessingSubunitInternalIntf(self): u = AccessingSubunitInternalIntf() with self.assertRaises(AssertionError): toRtl(u)
def test_unusedSubunit2(self): u = UnusedSubunit2() with self.assertRaises(NoDriverErr): toRtl(u)
def test_multipleDriversOfChildNet2(self): u = MultipleDriversOfChildNet2() with self.assertRaises(MultipleDriversErr): toRtl(u)
def test_ParametrizationExample(self): toRtl(ParametrizationExample())
isLastBit = clkBuilder.timer(("isLastBitTick", 10), enableSig=rxd_vld, rstSig=~en) If( en, If( rxd_vld, RxD_data(Concat(rxd, RxD_data[9:1])), # shift data from left If( startBitWasNotStartbit, en(0), first(1), ).Else( en(~isLastBit), first(isLastBit), ))).Elif( RxD_sync._eq(START_BIT), # potential start bit detected, begin scanning sequence en(1), ) startBitWasNotStartbit(first & rxd_vld & (rxd != START_BIT)) self.dataOut.vld(isLastBit & RxD_data[0]._eq(START_BIT) & rxd._eq(STOP_BIT)) self.dataOut.data(RxD_data[9:1]) if __name__ == "__main__": from hwt.synthesizer.utils import toRtl print(toRtl(UartRx()))
propagateClk(self) PORT_CNT = int(self.PORT_CNT) fa = self.firstA sa = self.secondA If(self.select_sig, self.ram0.a(fa), self.ram1.a(sa) ).Else( self.ram0.a(sa), self.ram1.a(fa) ) if PORT_CNT == 2: fb = self.firstB sb = self.secondB If(self.select_sig, self.ram0.b(fb), self.ram1.b(sb), ).Else( self.ram0.b(sb), self.ram1.b(fb) ) elif PORT_CNT > 2: raise NotImplementedError() if __name__ == "__main__": from hwt.synthesizer.utils import toRtl print(toRtl(FlipRam))
def test_vhdl(self): s = toRtl(Showcase0(), serializer=VhdlSerializer) showcase0_vhdl = readContent("showcase0.vhd") self.assertEqual(s, showcase0_vhdl)
internB(self.a[1]) self.b[0](internA) self.b[1](internB) class IndexingInernJoin(Unit): """ .. hwt-schematic:: """ def _declr(self): self.a = Signal() self.b = Signal() self.c = Signal()._m() self.d = Signal()._m() def _impl(self): intern = self._sig("internSig", Bits(2)) intern[0](self.a) intern[1](self.b) connect(intern[0], self.c) connect(intern[1], self.d) if __name__ == "__main__": # alias python main function from hwt.synthesizer.utils import toRtl # there is more of synthesis methods. toRtl() returns formated vhdl string print(toRtl(IndexingInernSplit()))
def test_verilog(self): s = toRtl(Showcase0(), serializer=VerilogSerializer) showcase0_verilog = readContent("showcase0.v") self.assertEqual(s, showcase0_verilog)
(uint32_t[32], None), # type can be any type (HStruct((uint16_t, "data4a"), (uint16_t, "data4b"), (uint32_t, "data4c")), "data4"), ) # type flattening can be specified by shouldEnterFn parameter # target interface can be overriden by _mkFieldInterface function # There are other bus endpoints, for example: # IpifEndpoint, I2cEndpoint, AvalonMmEndpoint and others # decoded interfaces for data type will be same just bus interface # will difer u = AxiLiteEndpoint(t) # configuration u.ADDR_WIDTH.set(8) u.DATA_WIDTH.set(32) return u if __name__ == "__main__": from hwt.synthesizer.utils import toRtl from hwt.serializer.vhdl.serializer import VhdlSerializer u = _example_AxiLiteEndpoint() print(toRtl(u, serializer=VhdlSerializer)) print(u.bus) print(u.decoded.data3) print(u.decoded.data4)
def test_systemc(self): s = toRtl(Showcase0(), serializer=SystemCSerializer) showcase0_systemc = readContent("showcase0.cpp") self.assertEqual(s, showcase0_systemc)
def test_invalidTypeConnetion(self): u = InvalidTypeConnetion() with self.assertRaises(TypeConversionErr): toRtl(u)
""" .. hwt-schematic:: """ def _declr(self): self.addr = VectSignal(2) self.dout = VectSignal(8)._m() def _impl(self): rom = self._sig("rom_data", Bits(8)[4], defVal=[1, 2, 3, 4]) self.dout(rom[self.addr]) class SimpleSyncRom(SimpleRom): """ .. hwt-schematic:: """ def _declr(self): super()._declr() self.clk = Clk() def _impl(self): rom = self._sig("rom_data", Bits(8)[4], defVal=[1, 2, 3, 4]) If(self.clk._onRisingEdge(), self.dout(rom[self.addr])) if __name__ == "__main__": # alias python main function from hwt.synthesizer.utils import toRtl # there is more of synthesis methods. toRtl() returns formated vhdl string print(toRtl(SimpleSyncRom()))
defVal=hBit(None)._concat(self.INIT)) a_in = s("a_in", Bits(6)) d_in = s("d_in") we_in = s("we_in") wclk_in(self.wclk ^ self.IS_WCLK_INVERTED) we_in(self.we) a_in(Concat(self.a5, self.a4, self.a3, self.a2, self.a1, self.a0)) d_in(self.d) # ReadBehavior self.o(mem[a_in]) # WriteBehavior If(wclk_in._onRisingEdge() & we_in, mem[a_in](d_in) ) RAMnX1S.__name__ = "RAM%dX1S" % DATA_WIDTH return RAMnX1S # exclude from serialization because it is part of sources provided from FPGA vendor RAM64X1S = serializeExclude(mkLutRamCls(64)) if __name__ == "__main__": from hwt.synthesizer.utils import toRtl u = RAM64X1S() print(toRtl(u))
def test_inconsistentIntfDirection(self): u = InconsistentIntfDirection() with self.assertRaises(IntfLvlConfErr): toRtl(u)
self.DATA_WIDTH = Param(8) self.USE_STRB = Param(True) def _declr(self): addClkRstn(self) with self._paramsShared(): self.a0 = AxiStream() self.b0 = AxiStream()._m() self.u0 = Simple2withNonDirectIntConnection() self.u1 = Simple2withNonDirectIntConnection() def _impl(self): propagateClkRstn(self) self.u0.a(self.a0) self.u1.a(self.u0.c) self.b0(self.u1.c) class UnitToUnitConnectionTC(SimpleSubunit2TC): def setUp(self): SimTestCase.setUp(self) self.u = UnitToUnitConnection() self.prepareUnit(self.u) if __name__ == "__main__": from hwt.synthesizer.utils import toRtl u = UnitToUnitConnection() print(toRtl(u))
def test_multipleDriversOfChildNet(self): u = MultipleDriversOfChildNet() with self.assertRaises((MultipleDriversErr, NoDriverErr)): toRtl(u)