def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.drivers = HObjList(AxiRDatapumpIntf()
for _ in range(int(self.DRIVER_CNT)))
self.rDatapump = AxiRDatapumpIntf()._m()
self.DRIVER_INDEX_WIDTH = log2ceil(self.DRIVER_CNT).val
f = self.orderInfoFifo = HandshakedFifo(Handshaked)
f.DEPTH.set(self.MAX_TRANS_OVERLAP)
f.DATA_WIDTH.set(self.DRIVER_INDEX_WIDTH)
def _declr(self):
addClkRstn(self)
# addr of start of array
self.base = VectSignal(self.ADDR_WIDTH)
# input index of item to get
self.index = Handshaked()
self.index.DATA_WIDTH.set(log2ceil(self.ITEMS))
# output item from array
self.item = Handshaked()._m()
self.item.DATA_WIDTH.set(self.ITEM_WIDTH)
self.ITEMS_IN_DATA_WORD = int(self.DATA_WIDTH) // int(self.ITEM_WIDTH)
with self._paramsShared():
# interface for communication with datapump
self.rDatapump = AxiRDatapumpIntf()._m()
self.rDatapump.MAX_LEN.set(1)
if self.ITEMS_IN_DATA_WORD > 1:
assert isPow2(self.ITEMS_IN_DATA_WORD)
f = self.itemSubIndexFifo = HandshakedFifo(Handshaked)
f.DATA_WIDTH.set(log2ceil(self.ITEMS_IN_DATA_WORD))
f.DEPTH.set(self.MAX_TRANS_OVERLAP)
def _declr(self):
addClkRstn(self)
with self._paramsShared():
# read interface for datapump
# interface which sending requests to download addr of next block
self.rDatapump = AxiRDatapumpIntf()._m()
self.rDatapump.MAX_LEN.set(
1) # because we are downloading only addres of next block
# write interface for datapump
self.wDatapump = AxiWDatapumpIntf()._m()
self.wDatapump.MAX_LEN.set(self.BUFFER_CAPACITY // 2)
assert self.BUFFER_CAPACITY <= self.ITEMS_IN_BLOCK
# interface for items which should be written into list
self.dataIn = Handshaked()
# interface to control internal register
a = self.baseAddr = RegCntrl()
a._replaceParam(a.DATA_WIDTH, self.ADDR_WIDTH)
self.rdPtr = RegCntrl()
self.wrPtr = RegCntrl()
for ptr in [self.rdPtr, self.wrPtr]:
ptr._replaceParam(ptr.DATA_WIDTH, self.PTR_WIDTH)
f = self.dataFifo = HandshakedFifo(Handshaked)
f.EXPORT_SIZE.set(True)
f.DATA_WIDTH.set(self.DATA_WIDTH)
f.DEPTH.set(self.BUFFER_CAPACITY)
self.ALIGN_BITS = log2ceil(self.DATA_WIDTH // 8).val
def _declr(self):
addClkRstn(self)
with self._paramsShared():
# interface which sending requests to download data
# and interface which is collecting all data and only data with specified id are processed
self.rDatapump = AxiRDatapumpIntf()._m()
self.rDatapump.MAX_LEN.set(self.BUFFER_CAPACITY // 2 - 1)
self.dataOut = Handshaked()._m()
# (how much of items remains in block)
self.inBlockRemain = VectSignal(log2ceil(self.ITEMS_IN_BLOCK + 1))._m()
# interface to control internal register
a = self.baseAddr = RegCntrl()
a._replaceParam(a.DATA_WIDTH, self.ADDR_WIDTH)
self.rdPtr = RegCntrl()
self.wrPtr = RegCntrl()
for ptr in [self.rdPtr, self.wrPtr]:
ptr._replaceParam(ptr.DATA_WIDTH, self.PTR_WIDTH)
f = self.dataFifo = HandshakedFifo(Handshaked)
f.EXPORT_SIZE.set(True)
f.DATA_WIDTH.set(self.DATA_WIDTH)
f.DEPTH.set(self.BUFFER_CAPACITY)
def _declr(self):
super()._declr() # add clk, rst, axi addr channel and req channel
with self._paramsShared():
self.r = Axi4_r()
self.driver = AxiRDatapumpIntf()
self.errorRead = Signal()._m()
f = self.sizeRmFifo = HandshakedFifo(TransEndInfo)
f.DEPTH.set(self.MAX_TRANS_OVERLAP)
def _declr(self):
self.PAGE_OFFSET_WIDTH = log2ceil(self.PAGE_SIZE).val
self.LVL1_PAGE_TABLE_INDX_WIDTH = log2ceil(
self.LVL1_PAGE_TABLE_ITEMS).val
self.LVL2_PAGE_TABLE_INDX_WIDTH = int(self.ADDR_WIDTH -
self.LVL1_PAGE_TABLE_INDX_WIDTH -
self.PAGE_OFFSET_WIDTH)
self.LVL2_PAGE_TABLE_ITEMS = 2**int(self.LVL2_PAGE_TABLE_INDX_WIDTH)
assert self.LVL1_PAGE_TABLE_INDX_WIDTH > 0, self.LVL1_PAGE_TABLE_INDX_WIDTH
assert self.LVL2_PAGE_TABLE_INDX_WIDTH > 0, self.LVL2_PAGE_TABLE_INDX_WIDTH
assert self.LVL2_PAGE_TABLE_ITEMS > 1, self.LVL2_PAGE_TABLE_ITEMS
# public interfaces
addClkRstn(self)
with self._paramsShared():
self.rDatapump = AxiRDatapumpIntf()._m()
self.rDatapump.MAX_LEN.set(1)
i = self.virtIn = Handshaked()
i._replaceParam(i.DATA_WIDTH, self.VIRT_ADDR_WIDTH)
i = self.physOut = Handshaked()._m()
i._replaceParam(i.DATA_WIDTH, self.ADDR_WIDTH)
self.segfault = Signal()._m()
self.lvl1Table = BramPort_withoutClk()
# internal components
self.lvl1Storage = RamSingleClock()
self.lvl1Storage.PORT_CNT.set(1)
self.lvl1Converter = RamAsHs()
for u in [self.lvl1Table, self.lvl1Converter, self.lvl1Storage]:
u.DATA_WIDTH.set(self.ADDR_WIDTH)
u.ADDR_WIDTH.set(self.LVL1_PAGE_TABLE_INDX_WIDTH)
with self._paramsShared():
self.lvl2get = ArrayItemGetter()
self.lvl2get.ITEM_WIDTH.set(self.ADDR_WIDTH)
self.lvl2get.ITEMS.set(self.LVL2_PAGE_TABLE_ITEMS)
self.lvl2indxFifo = HandshakedFifo(Handshaked)
self.lvl2indxFifo.DEPTH.set(self.MAX_OVERLAP // 2)
self.lvl2indxFifo.DATA_WIDTH.set(self.LVL2_PAGE_TABLE_INDX_WIDTH)
self.pageOffsetFifo = HandshakedFifo(Handshaked)
self.pageOffsetFifo.DEPTH.set(self.MAX_OVERLAP)
self.pageOffsetFifo.DATA_WIDTH.set(self.PAGE_OFFSET_WIDTH)
def _declr(self):
addClkRstn(self)
self.dataOut = StructIntf(self._structT, self._mkFieldIntf)._m()
g = self.get = Handshaked(
) # data signal is addr of structure to download
g._replaceParam(g.DATA_WIDTH, self.ADDR_WIDTH)
self.parseTemplate()
with self._paramsShared():
# interface for communication with datapump
self.rDatapump = AxiRDatapumpIntf()._m()
self.rDatapump.MAX_LEN.set(self.maxWordIndex() + 1)
with self._paramsShared(exclude={self.ID_WIDTH}):
self.parser = AxiS_frameParser(self._structT,
tmpl=self._tmpl,
frames=self._frames)
self.parser.SYNCHRONIZE_BY_LAST.set(False)
if self.SHARED_READY:
self.ready = Signal()
def _config(self):
self.DRIVER_CNT = Param(2)
self.MAX_TRANS_OVERLAP = Param(16)
AxiRDatapumpIntf._config(self)
def _config(self):
self.ID = Param(0)
AxiRDatapumpIntf._config(self)
self.USE_STRB.set(False)
self.READ_ACK = Param(False)
self.SHARED_READY = Param(False)
def _config(self):
self.DRIVER_CNT = Param(2)
self.MAX_TRANS_OVERLAP = Param(16)
AxiRDatapumpIntf._config(self)
def _config(self):
self.ID = Param(0)
AxiRDatapumpIntf._config(self)
self.USE_STRB.set(False)
self.READ_ACK = Param(False)
self.SHARED_READY = Param(False)