def _declr(self):
AxiInterconnectCommon._declr(self, has_r=False, has_w=True)
masters_for_slave = AxiInterconnectMatrixCrossbar._masters_for_slave(
self.MASTERS, len(self.SLAVES))
# fifo for master index for each slave so slave knows
# which master did read and where is should send it
order_m_index_for_s_data = HObjList()
order_m_index_for_s_b = HObjList()
for connected_masters in masters_for_slave:
if len(connected_masters) > 1:
f_w = HandshakedFifo(Handshaked)
f_b = HandshakedFifo(Handshaked)
for _f in [f_w, f_b]:
_f.DEPTH = self.MAX_TRANS_OVERLAP
_f.DATA_WIDTH = log2ceil(len(self.MASTERS))
else:
f_w, f_b = None, None
order_m_index_for_s_data.append(f_w)
order_m_index_for_s_b.append(f_b)
self.order_m_index_for_s_data = order_m_index_for_s_data
self.order_m_index_for_s_b = order_m_index_for_s_b
# fifo for slave index for each master
# so master knows where it should expect the data
order_s_index_for_m_data = HObjList()
order_s_index_for_m_b = HObjList()
for connected_slaves in self.MASTERS:
if len(connected_slaves) > 1:
f_w = HandshakedFifo(Handshaked)
f_b = HandshakedFifo(Handshaked)
for f in [f_w, f_b]:
f.DEPTH = self.MAX_TRANS_OVERLAP
f.DATA_WIDTH = log2ceil(len(self.SLAVES))
else:
f_w, f_b = None, None
order_s_index_for_m_data.append(f_w)
order_s_index_for_m_b.append(f_b)
self.order_s_index_for_m_data = order_s_index_for_m_data
self.order_s_index_for_m_b = order_s_index_for_m_b
AXI = self.intfCls
with self._paramsShared():
self.addr_crossbar = AxiInterconnectMatrixAddrCrossbar(AXI.AW_CLS)
with self._paramsShared():
c = self.data_crossbar = AxiInterconnectMatrixCrossbar(AXI.W_CLS)
c.INPUT_CNT = len(self.MASTERS)
W_OUTPUTS = [set() for _ in self.SLAVES]
for m_i, accessible_slaves in enumerate(self.MASTERS):
for s_i in accessible_slaves:
W_OUTPUTS[s_i].add(m_i)
c.OUTPUTS = W_OUTPUTS
with self._paramsShared():
c = self.b_crossbar = AxiInterconnectMatrixCrossbarB(AXI.B_CLS)
c.INPUT_CNT = len(self.SLAVES)
c.OUTPUTS = self.MASTERS
def setUpClass(cls):
cls.u = u = AxiInterconnectMatrixAddrCrossbar(Axi4.AR_CLS)
u.MASTERS = ({0}, {0}, {1}, {1}, {0, 1})
u.SLAVES = (
(0x0000, 0x1000),
(0x1000, 0x1000),
)
u.ADDR_WIDTH = log2ceil(0x2000 - 1)
cls.compileSim(u)
def _declr(self):
AxiInterconnectCommon._declr(self, has_r=True, has_w=False)
masters_for_slave = AxiInterconnectMatrixCrossbar._masters_for_slave(
self.MASTERS, len(self.SLAVES))
# fifo for master index for each slave so slave knows
# which master did read and where is should send it
order_m_index_for_s_data = HObjList()
for connected_masters in masters_for_slave:
if len(connected_masters) > 1:
f = HandshakedFifo(Handshaked)
f.DEPTH = self.MAX_TRANS_OVERLAP
f.DATA_WIDTH = log2ceil(len(self.MASTERS))
else:
f = None
order_m_index_for_s_data.append(f)
self.order_m_index_for_s_data = order_m_index_for_s_data
# fifo for slave index for each master
# so master knows where it should expect the data
order_s_index_for_m_data = HObjList()
for connected_slaves in self.MASTERS:
if len(connected_slaves) > 1:
f = HandshakedFifo(Handshaked)
f.DEPTH = self.MAX_TRANS_OVERLAP
f.DATA_WIDTH = log2ceil(len(self.SLAVES))
else:
f = None
order_s_index_for_m_data.append(f)
self.order_s_index_for_m_data = order_s_index_for_m_data
with self._paramsShared():
self.addr_crossbar = AxiInterconnectMatrixAddrCrossbar(
self.intfCls.AR_CLS)
with self._paramsShared():
c = self.data_crossbar = AxiInterconnectMatrixCrossbar(
self.intfCls.R_CLS)
c.INPUT_CNT = len(self.SLAVES)
c.OUTPUTS = self.MASTERS