def check_consystency(self, u):
synthesised(u)
c = u._ctx
for s in c.signals:
for e in s.endpoints:
if isinstance(e, HdlStatement):
self.assertIs(e.parentStm, None, (s, e))
self.assertIn(e, c.statements)
for d in s.drivers:
if isinstance(d, HdlStatement):
self.assertIs(d.parentStm, None, (s, d))
self.assertIn(d, c.statements)
for stm in c.statements:
self.assertIs(stm.parentStm, None)
def test_SimpleUnit2(self):
from hwtLib.examples.simpleAxiStream import SimpleUnitAxiStream
u = SimpleUnitAxiStream()
u._loadDeclarations()
def ex(i):
return self.assertTrue(i._isExtern)
ex(u.a)
ex(u.a.data)
ex(u.a.last)
ex(u.a.ready)
ex(u.a.strb)
ex(u.a.valid)
ex(u.b)
ex(u.b.data)
ex(u.b.last)
ex(u.b.ready)
ex(u.b.strb)
ex(u.b.valid)
u = synthesised(u)
for pn in ['a_data', 'a_last', 'a_strb', 'a_valid', 'b_ready']:
self.assertDirIn(u, pn)
for pn in ['a_ready', 'b_data', 'b_last', 'b_strb', 'b_valid']:
self.assertDirOut(u, pn)
def test_SimpleUnit2(self):
from hwtLib.examples.simpleAxiStream import SimpleUnitAxiStream
u = SimpleUnitAxiStream()
u._loadDeclarations()
def ex(i): return self.assertTrue(i._isExtern)
ex(u.a)
ex(u.a.data)
ex(u.a.last)
ex(u.a.ready)
ex(u.a.strb)
ex(u.a.valid)
ex(u.b)
ex(u.b.data)
ex(u.b.last)
ex(u.b.ready)
ex(u.b.strb)
ex(u.b.valid)
u = synthesised(u)
for pn in ['a_data', 'a_last', 'a_strb', 'a_valid', 'b_ready']:
self.assertDirIn(u, pn)
for pn in ['a_ready', 'b_data', 'b_last', 'b_strb', 'b_valid']:
self.assertDirOut(u, pn)
def test_SimpleSubUnit2(self):
from hwtLib.examples.hierarchy.simpleSubunit2 import SimpleSubunit2
u = SimpleSubunit2()
u = synthesised(u)
for pn in ['a0_data', 'a0_last', 'a0_strb', 'a0_valid', 'b0_ready']:
self.assertDirIn(u, pn)
for pn in ['a0_ready', 'b0_data', 'b0_last', 'b0_strb', 'b0_valid']:
self.assertDirOut(u, pn)
def test_SimpleSubUnit2(self):
from hwtLib.examples.hierarchy.simpleSubunit2 import SimpleSubunit2
u = SimpleSubunit2()
u = synthesised(u)
for pn in ['a0_data', 'a0_last', 'a0_strb', 'a0_valid', 'b0_ready']:
self.assertDirIn(u, pn)
for pn in ['a0_ready', 'b0_data', 'b0_last', 'b0_strb', 'b0_valid']:
self.assertDirOut(u, pn)
def test_EmptyUnit(self):
class Eu(EmptyUnit):
def _declr(self):
self.a = Signal()
self.b = Signal()._m()
u = Eu()
u = synthesised(u)
e = u._ctx.ent
a = self.getPort(e, 'a')
b = self.getPort(e, 'b')
self.assertEqual(a.direction, D.IN)
self.assertEqual(b.direction, D.OUT)
def test_EmptyUnit(self):
class Eu(EmptyUnit):
def _declr(self):
self.a = Signal()
self.b = Signal()._m()
u = Eu()
u = synthesised(u)
e = u._entity
a = self.getPort(e, 'a')
b = self.getPort(e, 'b')
self.assertEqual(a.direction, D.IN)
self.assertEqual(b.direction, D.OUT)
def test_SimpleUnit2_iLvl(self):
"""
Check interface directions pre and after synthesis
"""
from hwtLib.examples.simpleAxiStream import SimpleUnitAxiStream
u = SimpleUnitAxiStream()
u._loadDeclarations()
m = self.assertIsM
s = self.assertIsS
# u.a._resolveDirections()
# u.b._resolveDirections()
#
#
# # inside
# m(u.a)
# m(u.a.data)
# m(u.a.last)
# s(u.a.ready)
# m(u.a.valid)
# m(u.a.strb)
#
# # inside
# m(u.b)
# m(u.b.data)
# m(u.b.last)
# s(u.b.ready)
# m(u.b.valid)
# m(u.b.strb)
u = synthesised(u)
# outside
s(u.a)
s(u.a.data)
s(u.a.last)
m(u.a.ready)
s(u.a.valid)
s(u.a.strb)
m(u.b)
m(u.b.data)
m(u.b.last)
s(u.b.ready)
m(u.b.valid)
m(u.b.strb)
def test_SimpleUnit2_iLvl(self):
"""
Check interface directions pre and after synthesis
"""
from hwtLib.examples.simpleAxiStream import SimpleUnitAxiStream
u = SimpleUnitAxiStream()
u._loadDeclarations()
m = self.assertIsM
s = self.assertIsS
# u.a._resolveDirections()
# u.b._resolveDirections()
#
#
# # inside
# m(u.a)
# m(u.a.data)
# m(u.a.last)
# s(u.a.ready)
# m(u.a.valid)
# m(u.a.strb)
#
# # inside
# m(u.b)
# m(u.b.data)
# m(u.b.last)
# s(u.b.ready)
# m(u.b.valid)
# m(u.b.strb)
u = synthesised(u)
# outside
s(u.a)
s(u.a.data)
s(u.a.last)
m(u.a.ready)
s(u.a.valid)
s(u.a.strb)
m(u.b)
m(u.b.data)
m(u.b.last)
s(u.b.ready)
m(u.b.valid)
m(u.b.strb)
def test_signalInstances(self):
from hwtLib.examples.simple import SimpleUnit
bram = SimpleUnit()
bram = synthesised(bram)
self.assertIsNot(bram.a, bram.b, 'instances are properly instantiated')
port_a = list(where(bram._ctx.ent.ports, lambda x: x.name == "a"))
port_b = list(where(bram._ctx.ent.ports, lambda x: x.name == "b"))
self.assertEqual(len(port_a), 1, 'entity has single port a')
port_a = port_a[0]
self.assertEqual(len(port_b), 1, 'entity has single port b')
port_b = port_b[0]
self.assertEqual(len(bram._ctx.ent.ports), 2,
'entity has right number of ports')
self.assertEqual(port_a.direction, D.IN,
'port a has src that means it should be input')
self.assertEqual(port_b.direction, D.OUT,
'port b has no src that means it should be output')
def test_signalInstances(self):
from hwtLib.examples.simple import SimpleUnit
bram = SimpleUnit()
bram = synthesised(bram)
self.assertIsNot(bram.a, bram.b, 'instances are properly instantiated')
port_a = list(where(bram._entity.ports, lambda x: x.name == "a"))
port_b = list(where(bram._entity.ports, lambda x: x.name == "b"))
self.assertEqual(len(port_a), 1, 'entity has single port a')
port_a = port_a[0]
self.assertEqual(len(port_b), 1, 'entity has single port b')
port_b = port_b[0]
self.assertEqual(len(bram._entity.ports), 2,
'entity has right number of ports')
self.assertEqual(port_a.direction, D.IN,
'port a has src that means it should be input')
self.assertEqual(port_b.direction, D.OUT,
'port b has no src that means it should be output')
def test_EmptyUnitWithCompositePort(self):
class Dummy(EmptyUnit):
def _declr(self):
self.a = Axi4()
self.b = Axi4()._m()
u = Dummy()
u = synthesised(u)
self.assertTrue(u.a.ar.addr._isExtern)
e = u._ctx.ent
a_ar_addr = self.getPort(e, 'a_ar_addr')
self.assertEqual(a_ar_addr.direction, D.IN)
a_ar_ready = self.getPort(e, 'a_ar_ready')
self.assertEqual(a_ar_ready.direction, D.OUT)
b_ar_addr = self.getPort(e, 'b_ar_addr')
self.assertEqual(b_ar_addr.direction, D.OUT)
b_ar_ready = self.getPort(e, "b_ar_ready")
self.assertEqual(b_ar_ready.direction, D.IN)
def test_EmptyUnitWithCompositePort(self):
class Dummy(EmptyUnit):
def _declr(self):
self.a = Axi4()
self.b = Axi4()._m()
u = Dummy()
u = synthesised(u)
self.assertTrue(u.a.ar.addr._isExtern)
e = u._entity
a_ar_addr = self.getPort(e, 'a_ar_addr')
self.assertEqual(a_ar_addr.direction, D.IN)
a_ar_ready = self.getPort(e, 'a_ar_ready')
self.assertEqual(a_ar_ready.direction, D.OUT)
b_ar_addr = self.getPort(e, 'b_ar_addr')
self.assertEqual(b_ar_addr.direction, D.OUT)
b_ar_ready = self.getPort(e, "b_ar_ready")
self.assertEqual(b_ar_ready.direction, D.IN)
