def main():
rom = ila.MemValues(16, 8, 0)
rom[0x800] = 0xA4
rom[0x801] = 0x00
inputs = {
'ACC': 0xC8,
'B': 0x97,
'DPH': 0x0,
'DPL': 0x0,
'IE': 0x0,
'IP': 0x0,
'IRAM': ila.MemValues(8, 8, 0xff),
'P0': 0x0,
'P1': 0x0,
'P2': 0x0,
'P3': 0x0,
'PC': 0x800,
'PCON': 0x0,
'PSW': 0x0,
'ROM': rom,
'SBUF': 0x0,
'SCON': 0x0,
'SP': 0x0,
'TCON': 0x0,
'TH0': 0x0,
'TH1': 0x0,
'TL0': 0x0,
'TL1': 0x0,
'TMOD': 0x0,
'XRAM_DATA_IN': 0xff
}
print inputs
outputs = eval8051(inputs)
print outputs
def createMems(self):
self.mem = self.model.mem('mem', instruction_format.MEM_ADDRESS_BITS,
instruction_format.MEM_BITS)
self.model.set_next('mem', self.mem)
self.mem_init_value = ila.MemValues(
instruction_format.MEM_ADDRESS_BITS, instruction_format.MEM_BITS,
0x0)
self.mem_init_value[0x4] = 0x0000000011c00000
self.mem_init_value[0xc] = 0x0000000011c00000
#self.mem_init_value[0x40] = 0x11c00000
self.model.set_init('mem', self.model.const(self.mem_init_value))
def getStates(self):
f = open(self.outFile, 'r')
line = f.readline()
assert (line == ".AES_OP_START\n")
line = f.readline()
while (line != ".AES_OP_END\n"):
wordList = line.split()
if (wordList[0] == "aes_state"):
self.aes_state = int(wordList[1], 16)
elif (wordList[0] == "aes_addr"):
self.aes_addr = int(wordList[1], 16)
elif (wordList[0] == "aes_len"):
self.aes_len = int(wordList[1], 16)
elif (wordList[0] == "aes_keysel"):
self.aes_keysel = int(wordList[1], 16)
elif (wordList[0] == "aes_ctr"):
self.aes_ctr = int(wordList[1], 16)
elif (wordList[0] == "aes_key0"):
self.aes_key0 = int(wordList[1], 16)
elif (wordList[0] == "aes_key1"):
self.aes_key1 = int(wordList[1], 16)
elif (wordList[0] == "data_out"):
self.data_out = int(wordList[1], 16)
elif (wordList[0] == "byte_cnt"):
self.byte_cnt = int(wordList[1], 16)
elif (wordList[0] == "oped_byte_cnt"):
self.oped_byte_cnt = int(wordList[1], 16)
elif (wordList[0] == "blk_cnt"):
self.blk_cnt = int(wordList[1], 16)
elif (wordList[0] == "rd_data"):
self.rd_data = int(wordList[1], 16)
elif (wordList[0] == "enc_data"):
self.enc_data = int(wordList[1], 16)
elif (wordList[0] == "xram"):
self.xram = ila.MemValues(16, 8, 0x0)
line = f.readline()
wordList = line.split()
while (wordList[0] != "default:"):
addr = int(wordList[0], 16)
data = int(wordList[1], 16)
self.xram[addr] = data
line = f.readline()
wordList = line.split()
defVal = int(wordList[1], 16)
self.xram.default = defVal
else:
assert (False)
line = f.readline()
f.close()
def bar(d):
print d
ram = d['iram']
ram_ = ila.MemValues(8, 8, ram.default)
print ram
print ram_
for (ad, da) in ram.values:
ram_[ad] = da
addr = d['addr']
print ram_, addr, ram[addr]
if addr != 0:
ram_[addr] = ram_[addr]+1
print ram_
return { "bar": ram_ }
def extract(self, s_in):
cmd = s_in['cmd']
cmdaddr = s_in['cmdaddr']
cmddata = s_in['cmddata']
self.sha_state = s_in['sha_state']
self.sha_rdaddr = s_in['sha_rdaddr']
self.sha_wraddr = s_in['sha_wraddr']
self.sha_len = s_in['sha_len']
self.bytes_read = self.get(s_in, 'sha_bytes_read', 0)
self.rd_data = self.get(s_in, 'sha_rd_data', 0)
self.hs_data = self.get(s_in, 'sha_hs_data', 0)
self.xram = self.get(s_in, 'XRAM', ila.MemValues(16, 8, 0x0))
return cmd, cmdaddr, cmddata
def gen_uclid5(hexfile, enable_ps, filename):
(model, rom) = import_8051_ila(enable_ps)
# set ROM initial value.
data = readhex(hexfile)
romvalue = ila.MemValues(16, 8, 0xff)
for a, d in enumerate(data):
# print '%04X -> %02X' % (a, d)
romvalue[a] = d
romconst = model.const(romvalue)
model.set_init('ROM', romconst)
model.set_next('ROM', rom)
stage_print('Set ROM initial value.')
# setup uclid converter.
uclid5 = model.toUclid5("test")
uclid5.initVar('ROM')
uclid5.initVar('PC')
rom = model.getmem('ROM')
pc = model.getreg('PC')
pc_next = model.get_next('PC')
inst_next = rom[pc]
if filename is None:
init_pcs = uclid5.getExprValues(pc)
init_states = [(p, tuple([])) for p in init_pcs]
init_state_names = [
state_to_name(pc_val, tuple([])) for pc_val in init_pcs
]
state_map, state_edges, ret_set = get_cfg(uclid5, rom, pc, pc_next,
inst_next, init_states,
romconst)
with open('state_graph.obj', 'wt') as f:
pickle.dump(init_state_names, f)
pickle.dump(state_map, f)
pickle.dump(state_edges, f)
pickle.dump(ret_set, f)
else:
with open(filename, 'rt') as f:
init_state_names = pickle.load(f)
state_map = pickle.load(f)
state_edges = pickle.load(f)
ret_set = pickle.load(f)
reprs = merge_states(init_state_names, state_edges)
for k in sorted(reprs.keys()):
print '%-20s -> %-20s' % (k, reprs[k])
def extract(self, s_in):
cmd = s_in['cmd']
cmdaddr = s_in['cmdaddr']
cmddata = s_in['cmddata']
self.aes_state = s_in['aes_state']
self.aes_addr = s_in['aes_addr']
self.aes_len = s_in['aes_len']
self.aes_ctr = s_in['aes_ctr']
self.aes_key0 = s_in['aes_key0']
self.uaes_ctr = self.get(s_in, 'uaes_ctr', 0)
self.blk_cnt = self.get(s_in, 'blk_cnt', 0)
self.rd_data = self.get(s_in, 'rd_data', 0)
self.enc_data = self.get(s_in, 'enc_data', 0)
self.xram = self.get(s_in, 'XRAM', ila.MemValues(16, 8, 0x0))
return cmd, cmdaddr, cmddata
def extractIRAM(regs):
numCounts = defaultdict(int)
for i in xrange(0, 256):
numCounts[regs[i]] += 1
maxCnt = 0
maxKey = 0
for k, c in numCounts.iteritems():
if c > maxCnt:
maxCnt = c
maxKey = k
ram = ila.MemValues(8, 8, maxKey)
for i in xrange(0, 256):
if regs[i] != maxKey:
ram[i] = regs[i]
return ram
def _load_state(self, Sin): #return Sout
# fake the effect of interrupt !
masks = [0xffffff00, 0xffff00ff, 0xff00ffff, 0x00ffffff]
Sout = {}
with open(outFile) as outf:
# load x0-x31
for idx in range(33):
line = outf.readline().split()
assert (line[0] in GPRList)
Sout[line[0]] = int(line[1], 16)
assert (outf.readline().startswith('.CSR_BEGIN'))
line = outf.readline()
while not line.startswith('.CSR_END'):
#CSRname = line.split()[0]
#CSRval = line.split()[1]
line = outf.readline()
#if CSRname not in CSRList:
# continue
#Sout[CSRname] = int(CSRval, 16)
# check all have been assigned
#for name in CSRList:
# assert(name in Sout)
# now load memory
line = outf.readline().split()
byteSize = int(line[0])
default = int(line[1], 16)
outMem = ila.MemValues(32, 32, default)
for idx in range(byteSize):
line = outf.readline().split()
byteAddr = int(line[0], 16)
wordAddr = byteAddr / 4
byteData = int(line[1], 16)
originalVal = outMem[wordAddr]
pos = (byteAddr - wordAddr * 4) * 8
mask = masks[byteAddr - wordAddr * 4]
updateData = (originalVal & mask) | ((byteData & 0xff) << pos)
outMem[wordAddr] = updateData
Sout['mem'] = outMem
return Sout
# fake the effect of interrupt
"""
def getStates(self):
f = open(self.outFile, 'r')
line = f.readline()
assert (line == ".AES_OP_START\n")
line = f.readline()
while (line != ".AES_OP_END\n"):
wordList = line.split()
if (wordList[0] == "aes_state"):
self.aes_state = int(wordList[1], 16)
elif (wordList[0] == "aes_addr"):
self.aes_addr = int(wordList[1], 16)
elif (wordList[0] == "aes_len"):
self.aes_len = int(wordList[1], 16)
elif (wordList[0] == "aes_ctr"):
self.aes_ctr = int(wordList[1], 16)
elif (wordList[0] == "aes_key0"):
self.aes_key0 = int(wordList[1], 16)
elif (wordList[0] == "blk_cnt"):
self.blk_cnt = int(wordList[1], 16)
elif (wordList[0] == "rd_data"):
self.rd_data = int(wordList[1], 16)
elif (wordList[0] == "uaes_ctr"):
self.uaes_ctr = int(wordList[1], 16)
elif (wordList[0] == "enc_data"):
self.enc_data = int(wordList[1], 16)
elif (wordList[0] == "XRAM"): # need some changes
self.xram = ila.MemValues(16, 8, 0x0)
nopair = int(wordList[1], 10)
defVal = int(wordList[2], 16)
self.xram.default = defVal
for idx in range(nopair):
line = f.readline()
wordList = line.split()
addr = int(wordList[0], 16)
data = int(wordList[1], 16)
self.xram[addr] = data
elif wordList[0] in ['cmd', 'cmdaddr', 'cmddata']:
pass
else:
print wordList[0]
assert (False)
line = f.readline()
f.close()
def __init__(self):
self.aes_state = 0
self.aes_addr = 0
self.aes_len = 0
self.aes_ctr = 0
self.aes_key0 = 0
self.data_out = 0
self.byte_cnt = 0
self.aes_time = 0
self.blk_cnt = 0
self.oped_byte_cnt = 0
self.rd_data = 0
self.enc_data = 0
self.xram = ila.MemValues(16, 8, 0x0)
self.inFile = 'assign.in'
self.outFile = 'result.out'
def __init__(self):
self.aes_state = 0
self.aes_addr = 0
self.aes_len = 0
self.aes_ctr = 0
self.aes_key0 = 0
self.data_out = 0
self.byte_cnt = 0
self.aes_time = 0
self.blk_cnt = 0
self.oped_byte_cnt = 0
self.rd_data = 0
self.enc_data = 0
self.xram = ila.MemValues(16, 8, 0x0)
self.CAnno = 'C/Cinst.c'
self.Cinst = CInstrument.CInstrument('C/AES_CTR_TOP.c', self.CAnno)
self.outFile = 'Cresult.out'
def genboogie(hexfile, enable_ps):
model = ila.Abstraction("oc8051")
# fetch and decode.
uc = uc8051()
model.fetch_expr = uc.op0 # s/hand for uc.rom[uc.pc]
model.decode_exprs = [uc.op0 == i for i in xrange(0x0, 0x100)]
# program counter
pc = model.reg('PC', 16)
# code memory
rom = model.mem('ROM', 16, 8)
# IRAM
iram = model.mem('IRAM', 8, 8)
# main SFRs
acc = model.reg('ACC', 8)
b = model.reg('B', 8)
psw = model.reg('PSW', 8)
sp = model.reg('SP', 8)
dpl = model.reg('DPL', 8)
dph = model.reg('DPH', 8)
# ports
p0 = model.reg('P0', 8)
p1 = model.reg('P1', 8)
p2 = model.reg('P2', 8)
p3 = model.reg('P3', 8)
# misc SFRs
pcon = model.reg('PCON', 8)
tcon = model.reg('TCON', 8)
tmod = model.reg('TMOD', 8)
tl0 = model.reg('TL0', 8)
tl1 = model.reg('TH0', 8)
tl1 = model.reg('TL1', 8)
th1 = model.reg('TH1', 8)
scon = model.reg('SCON', 8)
sbuf = model.reg('SBUF', 8)
ie = model.reg('IE', 8)
ip = model.reg('IP', 8)
# XRAM
#xram_data_in = model.reg('XRAM_DATA_IN', 8) FIXME
#xram_data_in = model.inp('XRAM_DATA_IN', 8)
xram_data_out = model.reg('XRAM_DATA_OUT', 8)
xram_addr = model.reg('XRAM_ADDR', 16)
# get synthesized states
regs = [
'PC', 'ACC', 'B', 'PSW', 'SP',
'DPL', 'DPH',
'P0', 'P1', 'P2', 'P3',
'PCON', 'TCON', 'TMOD', 'TL0',
'TH0', 'TL1', 'TH1', 'SCON',
'SBUF', 'IE', 'IP', 'XRAM_DATA_OUT',
'XRAM_ADDR'
]
states = regs + ['IRAM']
for s in states:
ast = model.importOne('asts/%s_%s' % (s, 'en' if enable_ps else 'dis'))
model.set_next(s, ast)
for r in regs:
reg = model.getreg(r)
zero = model.const(0, reg.type.bitwidth)
model.set_init(r, zero)
print 'Finished importing 8051 ASTs.'
data = readhex(hexfile)
romvalue = ila.MemValues(16, 8, 0xff)
for a, d in enumerate(data):
#print '0x%04x -> 0x%02x' % (a, d)
romvalue[a] = d
romconst = model.const(romvalue)
model.set_init('ROM', romconst)
model.set_next('ROM', rom)
print 'Set ROM initial value.'
model.toBoogie("test")
pc_next = ila.ite((op == 0) | (op == 1), pc + 1, pc + 2)
return regs_next, pc_next
if __name__ == '__main__':
sys = ila.Abstraction('alu')
alu = alu_sim()
rom = sys.mem('rom', alu.ROM_ADDR_WIDTH, alu.OPCODE_WIDTH)
pc = sys.reg('pc', alu.ROM_ADDR_WIDTH)
regs = [sys.reg('r' + str(i), alu.REG_SIZE) for i in xrange(alu.NUM_REGS)]
gm_regs_next, pc_next = aluexpr(rom, pc, regs)
for i in xrange(alu.NUM_REGS):
sys.set_next('r' + str(i), gm_regs_next[i])
sys.set_next('pc', pc_next)
sys.set_next('rom', rom)
prop = sys.bit('prop')
opcode = rom[pc]
prop_nxt = prop & (opcode == 0x0)
sys.set_next('prop', prop_nxt)
sys.set_init('prop', sys.bool(True))
sys.set_init('pc', sys.const(0x0, alu.ROM_ADDR_WIDTH))
rom_init = ila.MemValues(alu.ROM_ADDR_WIDTH, alu.OPCODE_WIDTH, 0x0)
rom_init[0xa] = 0x1
sys.set_init('rom', sys.const(rom_init))
golden = ila.Abstraction('golden')
g_prop = golden.bit('prop')
golden.set_next('prop', golden.bool(True))
golden.set_init('prop', golden.bool(True))
print ila.bmc(11, sys, prop, 1, golden, g_prop)
def ptx_next_state(self, state):
mem = state['mem']
pc = state['pc']
instruction = mem[pc / 4]
print instruction
#pc += 4
#state['pc'] = pc
opcode = self.OPCODE_MASK & instruction
opcode = opcode >> instruction_format.OPCODE_BIT_BOT
dst = self.DST_MASK & instruction
dst = dst >> instruction_format.DST_BIT_BOT
src0 = self.SRC0_MASK & instruction
src0 = src0 >> instruction_format.SRC0_BIT_BOT
src1 = self.SRC1_MASK & instruction
src1 = src1 >> instruction_format.SRC1_BIT_BOT
base = self.BASE_MASK & instruction
base = base >> instruction_format.BASE_BIT_BOT
pred = self.P_REG_MASK & instruction
pred = pred >> self.P_REG_BIT
bra = (self.BRA_MASK & instruction) >> instruction_format.IMM_BIT_BOT
test_program = []
general_reg_book_file = 'general_reg_book'
general_reg_book_obj = open(general_reg_book_file)
general_reg_book = pickle.load(general_reg_book_obj)
for general_reg in general_reg_book:
test_program.append('mov.s32 ' + general_reg + ',' +
str(state[general_reg]) + '; ')
reg_book_file = 'reg_book'
reg_book_obj = open(reg_book_file, 'r')
reg_book = pickle.load(reg_book_obj)
instruction_book_file = 'instruction_book'
instruction_book_obj = open(instruction_book_file, 'r')
instruction_book = instruction_book_obj.readlines()
long_int_reg_book_file = 'long_int_reg_book'
long_int_reg_book_obj = open(long_int_reg_book_file, 'r')
long_int_reg_book = pickle.load(long_int_reg_book_obj)
long_int_reg_book_obj.close()
reg_book = general_reg_book + long_int_reg_book
#if ((opcode != self.OPCODE_MUL) & (opcode != self.OPCODE_ADD) & (opcode != self.OPCODE_SUB)):
if ((opcode != self.OPCODE_ADD) & (opcode != self.OPCODE_SUB) &
(opcode != self.OPCODE_BRA) & (opcode != self.OPCODE_BAR) &
(opcode != self.OPCODE_LD) & (opcode != self.OPCODE_ST) &
(opcode != self.OPCODE_MOV) & (opcode != self.OPCODE_MUL)):
state['pc'] = state['pc'] + 4
return state
if (opcode == self.OPCODE_BRA):
if base:
if pred >= len(reg_book):
return status
pred_reg_text = reg_book[pred]
if pred_reg_text not in general_reg_book:
return status
pred_reg_data = state[pred_reg_text]
if pred_reg_data:
pc += bra
state['pc'] = pc
else:
pc += bra
state['pc'] = pc
return state
'''
if (opcode == self.OPCODE_BAR):
bar_state = state['bar_state']
bar_spec = ptxILA.barSpec();
bar_counter_enter = state['bar_counter_enter']
bar_counter_exit = state['bar_counter_exit']
if (bar_state == bar_spec.BAR_FINISH):
state['pc'] = state['pc'] + 4
sim_program_line = ''
sim_program_line += 'mov.u32 %r1, ' + str(bar_state) + ';'
sim_program_line += 'mov.u32 %r23, ' + str(bar_counter_enter) + ';'
sim_program_line += 'mov.u32 %r24, ' + str(bar_counter_exit) + '; \n'
example_sim_program_file = 'tbar.ptx'
example_sim_program_obj = open(example_sim_program_file, 'r')
example_sim_program = example_sim_program_obj.readlines()
sim_program = []
bar_program_hole = 42
for i in range(len(example_sim_program)):
if i == bar_program_hole:
sim_program.append(sim_program_line)
else:
sim_program.append(example_sim_program[i])
example_sim_program_obj.close()
sim_program_file = 'tbar.ptx'
sim_program_obj = open(sim_program_file, 'w')
for sim_line in sim_program:
sim_program_obj.write(sim_line)
sim_program_obj.close()
(status, output) = commands.getstatusoutput('./dryrun_bar.out')
print status
print output
(status, output) = commands.getstatusoutput('sbatch parallel_bar.cmd')
print status
print output
output_word = output.split()
taskTag = output_word[3]
time.sleep(5)
(status, output) = commands.getstatusoutput('cat slurm-' + taskTag + '.out')
while(status == 256):
time.sleep(5)
(status, output) = commands.getstatusoutput('cat slurm-' + taskTag + '.out')
[bar_state, bar_counter_enter, bar_counter_exit] = output.split()
bar_state = int(bar_state)
bar_counter_enter = int(bar_counter_enter)
bar_counter_exit = int(bar_counter_exit)
if (bar_counter_enter < 0):
bar_counter_enter = -bar_counter_enter
bar_counter_enter = (1<<31) - bar_counter_enter + (1<<31)
if (bar_counter_exit < 0):
bar_counter_exit = -bar_counter_exit
bar_counter_exit = (1<<31) - bar_counter_exit + (1<<31)
state['bar_state'] = bar_state
state['bar_counter_enter'] = bar_counter_enter
state['bar_counter_exit'] = bar_counter_exit
return state
'''
if (opcode == self.OPCODE_BAR):
bar_state = state['bar_state']
#bar_counter_enter = state['bar_counter_enter']
#bar_counter_exit = state['bar_counter_exit']
bar_spec = ptxILA.barSpec()
bar_counter_enter = state['bar_counter_enter']
bar_counter_exit = state['bar_counter_exit']
if bar_state == bar_spec.BAR_INIT:
bar_state = bar_spec.BAR_ENTER
elif bar_state == bar_spec.BAR_FINISH:
state['pc'] = state['pc'] + 4
bar_state = bar_spec.BAR_INIT
elif bar_state == bar_spec.BAR_ENTER:
if (bar_counter_exit == 0):
bar_counter_enter = bar_counter_enter + 1
if bar_counter_enter == bar_spec.THREAD_NUM:
bar_state = bar_spec.BAR_EXIT
bar_counter_exit = bar_spec.THREAD_NUM
else:
if bar_counter_enter > bar_spec.THREAD_NUM:
state['bar_state'] = bar_spec.BAR_WAIT
return state
bar_state = bar_spec.BAR_WAIT
elif bar_state == bar_spec.BAR_WAIT:
if bar_counter_enter == bar_spec.THREAD_NUM:
bar_state = bar_spec.BAR_EXIT
elif bar_state == bar_spec.BAR_EXIT:
bar_counter_exit -= 1
bar_state = bar_spec.BAR_FINISH
if bar_counter_exit < 0:
state['bar_state'] = bar_spec.BAR_FINISH
if (bar_counter_exit < 0):
bar_counter_exit = -bar_counter_exit
bar_counter_exit = (
1 << (bar_spec.BAR_COUNTER_EXIT_BITS -
1)) - bar_counter_exit + (
1 << (bar_spec.BAR_COUNTER_EXIT - 1))
state['bar_counter_exit'] = bar_counter_exit
return state
if bar_counter_exit == 0:
bar_counter_enter = 0
state['bar_state'] = bar_state
state['bar_counter_enter'] = bar_counter_enter
state['bar_counter_exit'] = bar_counter_exit
return state
'''
if (bar_micro_flag):
bar_counter_enter = state['bar_counter_enter']
bar_counter_exit = state['bar_counter_exit']
if bar_state == bar_spec.BAR_ENTER:
if (bar_counter_exit == 0):
bar_counter_enter = bar_counter_enter + 1
if bar_counter_enter == bar_spec.THREAD_NUM:
bar_state = bar_spec.BAR_EXIT
bar_counter_exit = bar_spec.THREAD_NUM
else:
bar_state = bar_spec.BAR_WAIT
elif bar_state == bar_spec.BAR_WAIT:
if bar_counter_enter == bar_spec.THREAD_NUM:
bar_state = bar_spec.BAR_EXIT
elif bar_state == bar_spec.BAR_EXIT:
bar_counter_exit -= 1
bar_state = bar_spec.BAR_FINISH
if bar_counter_exit == 0:
bar_counter_enter = 0
state['bar_state'] = bar_state
state['bar_counter_enter'] = bar_counter_enter
state['bar_counter_exit'] = bar_counter_exit
else:
if bar_state == bar_spec.BAR_INIT:
bar_state = bar_spec.BAR_ENTER
elif bar_state == bar_spec.BAR_FINISH:
bar_state = bar_spec.BAR_INIT
state['pc'] = state['pc'] + 4
state['bar_state'] = bar_state
#state['bar_counter_enter'] = bar_counter_enter
#state['bar_counter_exit'] = bar_counter_exit
return state
'''
pc = pc + 4
state['pc'] = pc
op_text = instruction_book[opcode]
op_text = op_text[:(len(op_text) - 1)]
def find_addr(laddr):
for mem_key in mem_map.keys():
if (mem_map[mem_key][1]) >= laddr:
start_addr = mem_map[mem_key][0]
dmem_name = mem_key
return [dmem_name, start_addr]
if opcode == self.OPCODE_LD:
mem = state['dmem']
default = mem.default
values = mem.values
addr = []
value = []
for (a, v) in values:
addr.append(a * 4)
value.append(v)
dest_text = reg_book[dst]
self.ldAddr = (self.ldIMM_MASK
& instruction) >> instruction_format.IMM_BIT_BOT
self.ldAddr = (self.ldAddr) << 2
print 'load_addr' + str(self.ldAddr)
[dmem_name, start_addr] = find_addr(self.ldAddr)
item = (self.ldAddr - start_addr) >> 2
pre_ld_program = ''
pre_ld_program += '.reg .b64 %r_sim_ld<3>; .reg .b32 %r_ssim_ld;'
for i in range(len(addr)):
pre_addr = addr[i]
[pre_mem_name, pre_start_addr] = find_addr(pre_addr)
pre_item = (pre_addr - pre_start_addr) >> 2
pre_ld_program += 'ld.param.u64 %r_sim_ld1, [' + pre_mem_name + ']; '
pre_ld_program += 'cvta.to.global.u64 %r_sim_ld2, %r_sim_ld1; '
pre_ld_program += 'mov.u32 %r_ssim_ld, ' + str(pre_item) + '; '
pre_ld_program += 'mul.wide.s32 %r_sim_ld1, %r_ssim_ld, 4; '
pre_ld_program += 'add.s64 %r_sim_ld2, %r_sim_ld1, %r_sim_ld2; '
pre_ld_program += 'mov.u32 %r_ssim_ld, ' + str(value[i]) + '; '
pre_ld_program += 'st.global.b32 [%r_sim_ld2], %r_ssim_ld; '
pre_ld_program += '\n'
ld_program = ''
ld_program += 'ld.param.u64 %r_sim_ld1, [' + dmem_name + ']; '
ld_program += 'cvta.to.global.u64 %r_sim_ld2, %r_sim_ld1; '
ld_program += 'mov.u32 %r_ssim_ld, ' + str(item) + '; '
ld_program += 'mul.wide.s32 %r_sim_ld1, %r_ssim_ld, 4; '
ld_program += 'add.s64 %r_sim_ld2, %r_sim_ld1, %r_sim_ld2; '
ld_program += 'ld.global.b32 ' + dest_text + ',[%r_sim_ld2]; '
ld_program += 'mov.s32 %r9, ' + dest_text + '; '
example_sim_program_file = 't266.ptx'
example_sim_program_obj = open(example_sim_program_file, 'r')
example_sim_program = example_sim_program_obj.readlines()
sim_program = []
for test_program_line in test_program:
ld_program = test_program_line + ld_program
for i in range(len(example_sim_program)):
if i == self.EXAMPLE_PROGRAM_HOLE:
sim_program.append(ld_program + '\n')
elif i == self.PRE_LD_HOLE:
sim_program.append(pre_ld_program)
else:
sim_program.append(example_sim_program[i])
example_sim_program_obj.close()
sim_program_file = 't266.ptx'
sim_program_obj = open(sim_program_file, 'w')
for sim_program_line in sim_program:
sim_program_obj.write(sim_program_line)
sim_program_obj.close()
(status, output) = commands.getstatusoutput('./dryrun.out')
print status
print output
(status, output) = commands.getstatusoutput('sbatch parallel.cmd')
print status
print output
output_word = output.split()
taskTag = output_word[3]
time.sleep(5)
(status, output) = commands.getstatusoutput('cat slurm-' +
taskTag + '.out')
while (status == 256):
time.sleep(5)
(status, output) = commands.getstatusoutput('cat slurm-' +
taskTag + '.out')
poutput = int(output)
if (poutput < 0):
poutput = -poutput
poutput = (1 <<
(instruction_format.REG_BITS - 1)) - poutput + (
1 << (instruction_format.REG_BITS - 1))
print 'poutput: ' + str(poutput)
state[dest_text] = poutput
if self.ldAddr not in addr:
state[dest_text] = default
return state
if opcode == self.OPCODE_ST:
dmem = state['dmem']
dest_text = reg_book[dst]
st_value = state[dest_text]
self.stAddr = (self.stIMM_MASK
& instruction) >> instruction_format.IMM_BIT_BOT
self.stAddr = self.stAddr << 2
print 'store_addr' + str(self.stAddr)
outMem = ila.MemValues(instruction_format.MEM_ADDRESS_BITS,
instruction_format.DMEM_BITS, dmem.default)
for (a, v) in dmem.values:
outMem[a] = v
outMem[self.stAddr] = st_value
state['dmem'] = outMem
return state
if (opcode == self.OPCODE_MOV):
dst_text = reg_book[dst]
if (src0 >= len(reg_book)) | (dst >= len(reg_book)):
return state
if dst_text not in general_reg_book:
return state
src0_text = reg_book[src0]
if src0_text not in general_reg_book:
return state
if base:
return state
src0_data = state[src0_text]
test_program.append(op_text + '.s32 ' + dst_text + ',' +
src0_text + ';')
test_program.append('mov.s32 %r9, ' + dst_text + ';')
single_op_program = ''
for t in test_program:
single_op_program += t
single_op_program += '\n'
example_sim_program_file = 't266.ptx'
example_sim_program_obj = open(example_sim_program_file, 'r')
example_sim_program = example_sim_program_obj.readlines()
sim_program = []
for i in range(len(example_sim_program)):
if i == self.EXAMPLE_PROGRAM_HOLE:
sim_program.append(single_op_program)
else:
sim_program.append(example_sim_program[i])
example_sim_program_obj.close()
sim_program_obj = open(example_sim_program_file, 'w')
for sim_line in sim_program:
sim_program_obj.write(sim_line)
sim_program_obj.close()
(status, output) = commands.getstatusoutput('./dryrun.out')
print status
print output
(status, output) = commands.getstatusoutput('sbatch parallel.cmd')
print status
print output
output_word = output.split()
taskTag = output_word[3]
time.sleep(5)
(status, output) = commands.getstatusoutput('cat slurm-' +
taskTag + '.out')
while (status == 256):
time.sleep(5)
(status, output) = commands.getstatusoutput('cat slurm-' +
taskTag + '.out')
poutput = int(output)
if (poutput < 0):
poutput = -poutput
poutput = (1 <<
(instruction_format.REG_BITS - 1)) - poutput + (
1 << (instruction_format.REG_BITS - 1))
nxt_state = poutput
state[dst_text] = nxt_state
return state
dst_text = reg_book[dst]
if (src0 >= len(reg_book)) | (src1 >= len(reg_book)) | (dst >=
len(reg_book)):
return state
if dst_text not in reg_book:
return state
src0_text = reg_book[src0]
src1_text = reg_book[src1]
if (src0_text not in reg_book) | (src1_text not in reg_book):
return state
if (base):
return state
src0_data = state[src0_text]
src1_data = state[src1_text]
test_program.append(op_text + '.s32 ' + dst_text + ', ' + src0_text +
', ' + src1_text + ';')
print(op_text + ' ' + dst_text + ', ' + src0_text + ', ' + src1_text)
if dst_text in general_reg_book:
test_program.append('mov.s32 %r9, ' + dst_text + ';')
print test_program[-1]
example_sim_program_file = 't266.ptx'
example_sim_program_obj = open(example_sim_program_file, 'r')
example_sim_program = example_sim_program_obj.readlines()
sim_program = []
sim_program_first_part = 0
for i in range(len(example_sim_program)):
if i != self.EXAMPLE_PROGRAM_HOLE:
sim_program.append(example_sim_program[i])
elif i == (self.EXAMPLE_PROGRAM_HOLE + 1):
if dst_text not in general_reg_book:
sim_program.append('st.local.u32 [%rd8], %rd0;\n')
else:
sim_program.append('st.local.u32 [%rd8], %r9;\n')
else:
sim_program += test_program
sim_program += '\n'
example_sim_program_obj.close()
sim_program_obj = open(example_sim_program_file, 'w')
for sim_line in sim_program:
sim_program_obj.write(sim_line)
sim_program_obj.close()
(status, output) = commands.getstatusoutput('./dryrun.out')
print status
print output
(status, output) = commands.getstatusoutput('sbatch parallel.cmd')
print status
print output
output_word = output.split()
taskTag = output_word[3]
time.sleep(5)
(status,
output) = commands.getstatusoutput('cat slurm-' + taskTag + '.out')
while (status == 256):
time.sleep(5)
(status, output) = commands.getstatusoutput('cat slurm-' +
taskTag + '.out')
poutput = int(output)
if (poutput < 0):
poutput = -poutput
poutput = (1 << (instruction_format.REG_BITS - 1)) - poutput + (
1 << (instruction_format.REG_BITS - 1))
nxt_state = poutput
(status, output) = commands.getstatusoutput('rm a_dlin*')
(status, output) = commands.getstatusoutput('rm ' + 'slurm-' +
taskTag + '.out')
state[dst_text] = nxt_state
return state
def main():
sys = ila.Abstraction("test")
iram = sys.mem('iram', 8, 8)
addr = sys.reg('addr', 8)
print iram, iram.type
data = iram[addr]
addrp = sys.reg('addrp', 8)
datap = iram[addrp]
t = sys.bool(True)
f = sys.bool(False)
assert sys.areEqual((addr != addrp) | (data == datap), t)
print data, data.type
datap = data+1
print datap, datap.type
iramp = ila.store(iram, addr, data+1)
print iramp, iramp.type
assert sys.areEqual(iramp[addr], data+1)
assert not sys.areEqual(data, data+1)
m = ila.MemValues(8, 8, 0xff)
print m
for i in xrange(0x80, 0x90):
m[i] = i-0x80
print m
for i in xrange(0x0, 0x100):
if i >= 0x80 and i < 0x90:
assert m[i] == i-0x80
else:
assert m[i] == 0xff
print m
m1 = sys.const(m)
assert m.default == 0xff
m.default = 0x0
print m
assert m[0] == 0
print m.values
m2 = sys.const(m)
# assert not sys.areEqual(m1[addr], m2[addr])
ante = ((addr >= 0x80) & (addr < 0x90))
conseq = (m1[addr] == m2[addr])
assert sys.areEqual(ila.implies(ante, conseq), t)
assert not sys.areEqual(conseq, t)
r1 = iram[addr]+1
r2 = iram[addr]+iram[addr+1]
r = ila.choice('r', r1, r2)
print sys.syn_elem("foo", r, foo)
def bar(d):
print d
ram = d['iram']
ram_ = ila.MemValues(8, 8, ram.default)
print ram
print ram_
for (ad, da) in ram.values:
ram_[ad] = da
addr = d['addr']
print ram_, addr, ram[addr]
if addr != 0:
ram_[addr] = ram_[addr]+1
print ram_
return { "bar": ram_ }
r1 = ila.store(iram, addr, iram[addr]+1)
r2 = ila.store(iram, addr, iram[addr]+2)
r3 = ila.ite(addr != 0, r1, iram)
rp = ila.choice('rp', r1, r2, r3)
expr = sys.syn_elem("bar", rp, bar)
assert sys.areEqual(expr, r3)
ila.setloglevel(3, "")
data = sys.const(0xdeadbeef, 32)
print data
iramp = ila.storeblk(iram, addrp, data)
d0 = iramp[addrp]
d1 = iramp[addrp+1]
d2 = iramp[addrp+2]
d3 = iramp[addrp+3]
datablk = ila.loadblk(iramp, addrp, 4)
assert sys.areEqual(datablk, data)
assert sys.areEqual(datablk, ila.concat([d3, d2, d1, d0]))
assert sys.areEqual(ila.concat(d0, d1), sys.const(0xefbe, 16))
assert sys.areEqual(ila.concat(d2, d3), sys.const(0xadde, 16))
def simulate(self, s_in):
cmd = s_in['cmd']
cmdaddr = s_in['cmdaddr']
cmddata = s_in['cmddata']
self.aes_state = s_in['aes_state']
self.aes_addr = s_in['aes_addr']
self.aes_len = s_in['aes_len']
self.aes_keysel = s_in['aes_keysel']
self.aes_ctr = s_in['aes_ctr']
self.aes_key0 = s_in['aes_key0']
self.aes_key1 = s_in['aes_key1']
self.byte_cnt = s_in['byte_cnt']
self.rd_data = self.get(s_in, 'rd_data', 0)
self.enc_data = self.get(s_in, 'enc_data', 0)
self.xram = self.get(s_in, 'XRAM', ila.MemValues(16, 8, 0x0))
# default dataout.
dataout = 0
# execute command.
started = False
if cmd == RD:
found, data = self.read(cmdaddr)
if found:
dataout = data
elif cmd == WR and self.aes_state == 0:
if cmdaddr == 0xff00:
if cmddata == 1:
self.aes_state = 1
self.byte_cnt = 0
started = True
else:
self.write(cmdaddr, cmddata)
# do the operations.
if not started and self.aes_state == 1:
self.rd_data = 0
for i in xrange(16):
addr = (self.aes_addr + i + self.byte_cnt) & 0xffff
byte = self.xram[addr]
self.rd_data |= byte << (i * 8)
self.aes_state = 2
elif not started and self.aes_state == 2:
aes_key = self.aes_key0 if self.aes_keysel == 0 else self.aes_key1
aes_bytes_in = bytes(''.join(as_chars(self.rd_data, 16)))
aes_ctr = lambda: bytes(''.join(as_chars(self.aes_ctr, 16)))
aes_key = bytes(''.join(as_chars(aes_key, 16)))
aes = AESFactory.new(key=aes_key,
mode=AESFactory.MODE_CTR,
counter=aes_ctr)
self.enc_data = to_num(aes.encrypt(aes_bytes_in), 16)
self.aes_state = 3
pass
elif not started and self.aes_state == 3:
for i in xrange(16):
addr = (self.aes_addr + i + self.byte_cnt) & 0xffff
byte = (self.enc_data >> (i * 8)) & 0xff
self.xram[addr] = byte
self.byte_cnt = (self.byte_cnt + 16) & 0xffff
if self.byte_cnt < self.aes_len:
self.aes_state = 1
else:
self.aes_state = 0
s_out = self.s_dict()
s_out['dataout'] = dataout
return s_out
def gen_uclid5(hexfile, enable_ps, filename):
(model, rom, regs, memories, next_exprs) = import_8051_ila(enable_ps)
# set ROM initial value.
data = readhex(hexfile)
romvalue = ila.MemValues(16, 8, 0xff)
for a, d in enumerate(data):
# print '%04X -> %02X' % (a, d)
romvalue[a] = d
romconst = model.const(romvalue)
model.set_init('ROM', romconst)
model.set_next('ROM', rom)
next_exprs['ROM'] = model.get_next('ROM')
stage_print('Set ROM initial value.')
# setup uclid converter.
uclid5 = model.toUclid5("test")
uclid5.initVar('ROM')
uclid5.initVar('PC')
rom = model.getmem('ROM')
pc = model.getreg('PC')
pc_next = model.get_next('PC')
inst_next = rom[pc]
if filename is None:
init_pcs = uclid5.getExprValues(pc)
init_states = [(p, tuple([])) for p in init_pcs]
init_state_names = [
state_to_name(pc_val, tuple([])) for pc_val in init_pcs
]
state_map, state_edges, ret_set, state_to_nexts = get_cfg(
uclid5, rom, pc, pc_next, inst_next, init_states, romconst,
next_exprs)
if not os.path.exists(hexfile + '_asts'):
os.makedirs(hexfile + '_asts')
for state in state_to_nexts.keys():
for reg in state_to_nexts[state].keys():
f = open(hexfile + '_asts/%s-%s' % (reg, state), 'w')
model.exportOne(state_to_nexts[state][reg],
hexfile + '_asts/%s-%s' % (reg, state))
with open('state_graph.obj', 'wt') as f:
pickle.dump(init_state_names, f)
pickle.dump(state_map, f)
pickle.dump(state_edges, f)
pickle.dump(ret_set, f)
else:
with open(filename, 'rt') as f:
init_state_names = pickle.load(f)
state_map = pickle.load(f)
state_edges = pickle.load(f)
ret_set = pickle.load(f)
state_to_nexts = {}
states = regs + memories
for state in state_map.keys():
state_nexts = {}
for s in states:
state_nexts[s] = model.importOne(hexfile + '_asts/%s-%s' %
(s, state))
state_to_nexts[state] = state_nexts
(reprs, blocks) = merge_states(init_state_names, state_edges)
generateUclid5Program(
hexfile.split('.')[0], model, uclid5, regs, memories, data,
(state_map, state_edges, ret_set, state_to_nexts, blocks))
for k in sorted(reprs.keys()):
print '%-20s -> %-20s' % (k, reprs[k])
