def bench_quant_core():
"""wrapper used for conversion purpose"""
# instantiatiom of divider, clock and reset
inst = quantizer_core(clock, reset, quant_output_stream,
quant_input_stream, color_component)
inst_clock = clock_driver(clock)
inst_reset = reset_on_start(reset, clock)
@instance
def tbstim():
"""dummy tests to convert the module"""
yield clock.posedge
print("Conversion done!!")
raise StopSimulation
return tbstim, inst, inst_clock, inst_reset
def bench_quant_core():
"""wrapper used for conversion purpose"""
# instantiatiom of divider, clock and reset
inst = quantizer_core(clock, reset, quant_output_stream,
quant_input_stream, color_component)
inst_clock = clock_driver(clock)
inst_reset = reset_on_start(reset, clock)
@instance
def tbstim():
"""dummy tests to convert the module"""
yield clock.posedge
print ("Conversion done!!")
raise StopSimulation
return tbstim, inst, inst_clock, inst_reset
def bench_quant_core():
"""instantiation of quantizer core module and clock signals"""
inst = quantizer_core(
clock, reset, quant_output_stream,
quant_input_stream, color_component)
inst_clock = clock_driver(clock)
@instance
def tbstim():
"""We send the inputs from here"""
# reset the module before sending inputs
yield pulse_reset(reset, clock)
# select Cb or Cr component
color = component.y2_space
# process the component selected
yield quant_block_process(
clock, color_component, color, quant_in, quant_rom,
quant_input_stream, quant_output_stream, max_addr)
yield clock.posedge
print ("====================================")
# select Y1 or Y2 component
color = component.cb_space
# process the component selected
yield quant_block_process(
clock, color_component, color, quant_in, quant_rom,
quant_input_stream, quant_output_stream, max_addr)
yield clock.posedge
raise StopSimulation
return tbstim, inst, inst_clock
def bench_quant_core():
"""instantiation of quantizer core module and clock signals"""
inst = quantizer_core(clock, reset, quant_output_stream,
quant_input_stream, color_component)
inst_clock = clock_driver(clock)
@instance
def tbstim():
"""We send the inputs from here"""
# reset the module before sending inputs
yield pulse_reset(reset, clock)
# select Cb or Cr component
color = component.y2_space
# process the component selected
yield quant_block_process(clock, color_component, color, quant_in,
quant_rom, quant_input_stream,
quant_output_stream, max_addr)
yield clock.posedge
print("====================================")
# select Y1 or Y2 component
color = component.cb_space
# process the component selected
yield quant_block_process(clock, color_component, color, quant_in,
quant_rom, quant_input_stream,
quant_output_stream, max_addr)
yield clock.posedge
raise StopSimulation
return tbstim, inst, inst_clock