def test_alu_and( dump_vcd, test_verilog ):
run_test_vector_sim( AluRTL(), [
('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*'),
[ 0x00000000, 0x00000000, 2, 0x00000000, '?', '?', '?' ],
[ 0x0ffaa660, 0x00012304, 2, 0x00002200, '?', '?', '?' ],
[ 0x00132050, 0xd6620040, 2, 0x00020040, '?', '?', '?' ],
[ 0xfff0a440, 0x00004450, 2, 0x00000440, '?', '?', '?' ],
[ 0xffffffff, 0xffffffff, 2, 0xffffffff, '?', '?', '?' ],
], dump_vcd, test_verilog )
def test_alu_xor( dump_vcd, test_verilog ):
run_test_vector_sim( AluRTL(), [
('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*'),
[ 0x00000000, 0x00000000, 4, 0x00000000, '?', '?', '?' ],
[ 0x0ffaa660, 0x00012304, 4, 0x0ffb8564, '?', '?', '?' ],
[ 0x00132050, 0xd6620040, 4, 0xd6712010, '?', '?', '?' ],
[ 0xfff0a440, 0x00004450, 4, 0xfff0e010, '?', '?', '?' ],
[ 0xffffffff, 0xffffffff, 4, 0x00000000, '?', '?', '?' ],
], dump_vcd, test_verilog )
def test_alu_fn_ltu( dump_vcd, test_verilog ):
run_test_vector_sim( AluRTL(), [
('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*'),
[ 0x00000000, 0x00000000, 14, 0x00000000, '?', '?', 0 ],
[ 0x0ffaa660, 0x00012304, 14, 0x00000000, '?', '?', 0 ],
[ 0x00132050, 0xd6620040, 14, 0x00000000, '?', '?', 1 ],
[ 0xfff0a440, 0x00004450, 14, 0x00000000, '?', '?', 0 ],
[ 0xfeeeeaa3, 0xf4650000, 14, 0x00000000, '?', '?', 0 ],
], dump_vcd, test_verilog )
def test_alu_jalr( dump_vcd, test_verilog ):
run_test_vector_sim( AluRTL(), [
('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*'),
[ 0x00000000, 0x00000000, 10, 0x00000000, '?', '?', '?' ],
[ 0x0ffaa660, 0x00000304, 10, 0x0ffaa964, '?', '?', '?' ],
[ 0x00132050, 0x00000045, 10, 0x00132094, '?', '?', '?' ],
[ 0xfff0a440, 0x00000fff, 10, 0xfff0b43e, '?', '?', '?' ],
[ 0xfeeeeaa3, 0x000004de, 10, 0xfeeeef80, '?', '?', '?' ],
], dump_vcd, test_verilog )
def test_alu_add( dump_vcd, test_verilog ):
run_test_vector_sim( AluRTL(), [
('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*'),
[ 0x00000000, 0x00000000, 0, 0x00000000, '?', '?', '?' ],
[ 0x0ffaa660, 0x00012304, 0, 0x0ffbc964, '?', '?', '?' ],
#pos-neg
[ 0x00132050, 0xd6620040, 0, 0xd6752090, '?', '?', '?' ],
[ 0xfff0a440, 0x00004450, 0, 0xfff0e890, '?', '?', '?' ],
# neg-neg
[ 0xfeeeeaa3, 0xf4650000, 0, 0xf353eaa3, '?', '?', '?' ],
], dump_vcd, test_verilog )
def test_alu_sub( dump_vcd, test_verilog ):
run_test_vector_sim( AluRTL(), [
('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*'),
[ 0x00000000, 0x00000000, 1, 0x00000000, '?', '?', '?' ],
[ 0x0ffaa660, 0x00012304, 1, 0x0ff9835c, '?', '?', '?' ],
#pos-neg
[ 0x00000001, 0xffffffff, 1, 0x00000002, '?', '?', '?' ],
#neg-pos
[ 0xffff8000, 0x7fffffff, 1, 0x7fff8001, '?', '?', '?' ],
[ 0xfff0a440, 0x00004450, 1, 0xfff05ff0, '?', '?', '?' ],
# neg-neg
[ 0xfeeeeaa3, 0xf4650000, 1, 0x0a89eaa3, '?', '?', '?' ],
], dump_vcd, test_verilog )
def test_alu_sll( dump_vcd, test_verilog ):
run_test_vector_sim( AluRTL(), [
('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*'),
[ 0x00000000, 0x00000000, 7, 0x00000000, '?', '?', '?' ],
[ 0x00000001, 0x00000001, 7, 0x00000002, '?', '?', '?' ],
[ 0xfffffffd, 0x00000007, 7, 0xfffffe80, '?', '?', '?' ],
[ 0x00000000, 0x0000000e, 7, 0x00000000, '?', '?', '?' ],
[ 0x80000000, 0x00000000, 7, 0x80000000, '?', '?', '?' ],
[ 0x80000000, 0x0000000e, 7, 0x00000000, '?', '?', '?' ],
[ 0x00007fff, 0x00000000, 7, 0x00007fff, '?', '?', '?' ],
[ 0x0fffffff, 0x00000000, 7, 0x0fffffff, '?', '?', '?' ],
[ 0x7fffffff, 0x0000000e, 7, 0xffffc000, '?', '?', '?' ],
[ 0x00008001, 0x0000000b, 7, 0x04000800, '?', '?', '?' ],
[ 0xffff7fff, 0x0000000c, 7, 0xf7fff000, '?', '?', '?' ],
[ 0x00000000, 0x00000001, 7, 0x00000000, '?', '?', '?' ],
[ 0x000003e8, 0x00000001, 7, 0x000007d0, '?', '?', '?' ],
[ 0xffffff9c, 0x00000001, 7, 0xffffff38, '?', '?', '?' ],
], dump_vcd, test_verilog )
def test_alu_srl( dump_vcd, test_verilog ):
run_test_vector_sim( AluRTL(), [
('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*'),
[ 0x00000000, 0x00000000, 6, 0x00000000, '?', '?', '?' ],
[ 0x00000001, 0x00000001, 6, 0x00000000, '?', '?', '?' ],
[ 0xfffffffd, 0x00000007, 6, 0x01ffffff, '?', '?', '?' ],
[ 0x00000000, 0x0000000e, 6, 0x00000000, '?', '?', '?' ],
[ 0x80000000, 0x00000000, 6, 0x80000000, '?', '?', '?' ],
[ 0x80000000, 0x0000000e, 6, 0x00020000, '?', '?', '?' ],
[ 0x00007fff, 0x00000000, 6, 0x00007fff, '?', '?', '?' ],
[ 0x0fffffff, 0x00000000, 6, 0x0fffffff, '?', '?', '?' ],
[ 0x7fffffff, 0x0000000e, 6, 0x0001ffff, '?', '?', '?' ],
[ 0x00008001, 0x0000000b, 6, 0x00000010, '?', '?', '?' ],
[ 0xffff7fff, 0x0000000c, 6, 0x000ffff7, '?', '?', '?' ],
[ 0x00000000, 0x00000001, 6, 0x00000000, '?', '?', '?' ],
[ 0x000003e8, 0x00000001, 6, 0x000001f4, '?', '?', '?' ],
[ 0xffffff9c, 0x00000001, 6, 0x7fffffce, '?', '?', '?' ],
], dump_vcd, test_verilog )
def test_alu_sra( dump_vcd, test_verilog ):
run_test_vector_sim( AluRTL(), [
('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*'),
[ 0x00000000, 0x00000000, 5, 0x00000000, '?', '?', '?' ],
[ 0x00000001, 0x00000001, 5, 0x00000000, '?', '?', '?' ],
[ 0xfffffffd, 0x00000007, 5, 0xffffffff, '?', '?', '?' ],
[ 0x00000000, 0x0000000e, 5, 0x00000000, '?', '?', '?' ],
[ 0x80000000, 0x00000000, 5, 0x80000000, '?', '?', '?' ],
[ 0x80000000, 0x0000000e, 5, 0xfffe0000, '?', '?', '?' ],
[ 0x00007fff, 0x00000000, 5, 0x00007fff, '?', '?', '?' ],
[ 0x0fffffff, 0x00000000, 5, 0x0fffffff, '?', '?', '?' ],
[ 0x7fffffff, 0x0000000e, 5, 0x0001ffff, '?', '?', '?' ],
[ 0x80000000, 0x0000000c, 5, 0xfff80000, '?', '?', '?' ],
[ 0x7fffffff, 0x0000000c, 5, 0x0007ffff, '?', '?', '?' ],
[ 0x00000000, 0x00000001, 5, 0x00000000, '?', '?', '?' ],
[ 0x000003e8, 0x00000001, 5, 0x000001f4, '?', '?', '?' ],
[ 0xffffff9c, 0x00000001, 5, 0xffffffce, '?', '?', '?' ],
], dump_vcd, test_verilog )