def __init__(self, *, reset_addr, clk_freq, rom_addr, rom_size, ram_addr,
ram_size, uart_addr, uart_divisor, uart_pins, timer_addr,
timer_width):
self._arbiter = wishbone.Arbiter(addr_width=30,
data_width=32,
granularity=8,
features={"cti", "bte"})
self._decoder = wishbone.Decoder(addr_width=30,
data_width=32,
granularity=8,
features={"cti", "bte"})
self.cpu = MinervaCPU(reset_address=reset_addr)
self._arbiter.add(self.cpu.ibus)
self._arbiter.add(self.cpu.dbus)
self.rom = SRAMPeripheral(size=rom_size, writable=False)
self._decoder.add(self.rom.bus, addr=rom_addr)
self.ram = SRAMPeripheral(size=ram_size)
self._decoder.add(self.ram.bus, addr=ram_addr)
self.uart = AsyncSerialPeripheral(divisor=uart_divisor, pins=uart_pins)
self._decoder.add(self.uart.bus, addr=uart_addr)
self.timer = TimerPeripheral(width=timer_width)
self._decoder.add(self.timer.bus, addr=timer_addr)
self.intc = GenericInterruptController(width=len(self.cpu.ip))
self.intc.add_irq(self.timer.irq, 0)
self.intc.add_irq(self.uart.irq, 1)
self.memory_map = self._decoder.bus.memory_map
self.clk_freq = clk_freq
def __init__(self, *,
uart_pins, ddr_pins,
ddrphy_addr, dramcore_addr,
ddr_addr):
self._arbiter = wishbone.Arbiter(addr_width=30, data_width=32, granularity=8,
features={"cti", "bte"})
self._decoder = wishbone.Decoder(addr_width=30, data_width=32, granularity=8,
features={"cti", "bte"})
freq = 100e6
self.crg = ECPIX5CRG()
self.cpu = MinervaCPU(reset_address=0)
self._arbiter.add(self.cpu.ibus)
self._arbiter.add(self.cpu.dbus)
self.intc = GenericInterruptController(width=len(self.cpu.ip))
self.rom = SRAMPeripheral(size=4096, writable=False)
with open("firmware/main.bin", "rb") as f:
words = iter(lambda: f.read(self.cpu.data_width // 8), b'')
bios = [int.from_bytes(w, self.cpu.byteorder) for w in words]
self.rom.init = bios
self._decoder.add(self.rom.bus, addr=0)
self.ram = SRAMPeripheral(size=4096)
self._decoder.add(self.ram.bus, addr=0x1000)
self.uart = AsyncSerialPeripheral(divisor=int(freq//115200), pins=uart_pins)
self._decoder.add(self.uart.bus, addr=0x2000)
self.ddrphy = DomainRenamer("dramsync")(ECP5DDRPHY(ddr_pins))
self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr)
ddrmodule = MT41K256M16(freq, "1:2")
self.dramcore = DomainRenamer("dramsync")(gramCore(
phy=self.ddrphy,
geom_settings=ddrmodule.geom_settings,
timing_settings=ddrmodule.timing_settings,
clk_freq=freq))
self._decoder.add(self.dramcore.bus, addr=dramcore_addr)
self.drambone = DomainRenamer("dramsync")(gramWishbone(self.dramcore))
self._decoder.add(self.drambone.bus, addr=ddr_addr)
self.memory_map = self._decoder.bus.memory_map
self.clk_freq = freq
def __init__(self, clock_frequency=int(60e6)):
"""
Parameters:
clock_frequency -- The frequency of our `sync` domain, in MHz.
"""
self.clk_freq = clock_frequency
self._main_rom = None
self._main_ram = None
self._uart_baud = None
# Keep track of our created peripherals and interrupts.
self._submodules = []
self._irqs = {}
self._next_irq_index = 0
# By default, don't attach any debug hardware; or build a BIOS.
self._auto_debug = False
self._build_bios = False
#
# Create our core hardware.
# We'll create this hardware early, so it can be used for e.g. code generation without
# fully elaborating our design.
#
# Create our CPU.
self.cpu = MinervaCPU(with_debug=False)
# Create our interrupt controller.
self.intc = GenericInterruptController(width=32)
# Create our bus decoder and set up our memory map.
self.bus_decoder = wishbone.Decoder(addr_width=30,
data_width=32,
granularity=8,
features={"cti", "bte"})
self.memory_map = self.bus_decoder.bus.memory_map