Python dump_lim_graph示例

示例#1

文件： VerilogPipelineMultiFPGA.py 项目： HackLinux/HAsim-RV32I

  def __init__(self, moduleList):

    #build interface first 
    WrapperGen(moduleList)
    Iface(moduleList)

    # Floor planner can influence the BSV build, and must therefore
    # run first.
    Floorplanner(moduleList)

    BSV(moduleList)
    if (not moduleList.getAWBParam('bsv_tool', 'BUILD_LOGS_ONLY')):
      Verilog(moduleList, True)
    else:
      li_module.dump_lim_graph(moduleList)

示例#2

文件： FPGAPlatformPipeline.py 项目： HackLinux/HAsim-RV32I

  def __init__(self, moduleList):
    WrapperGen(moduleList)
    Iface(moduleList)

    # Floor planner can influence the backend flow steps, and must
    # therefore run first.
    Floorplanner(moduleList)

    BSV(moduleList)
    FPGAProgram(moduleList)
    MCD(moduleList)
    Synthesize(moduleList)

    if (not moduleList.getAWBParam('bsv_tool', 'BUILD_LOGS_ONLY')):
      PostSynthesize(moduleList)
    else:
      li_module.dump_lim_graph(moduleList)

示例#3

文件： FPGAPlatformPipeline.py 项目： HackLinux/HAsim-RV32I

    def __init__(self, moduleList):
        WrapperGen(moduleList)
        Iface(moduleList)

        # Floor planner can influence the BSV build, and must therefore
        # run first.
        if (not moduleList.getAWBParam('bsv_tool', 'BUILD_LOGS_ONLY')):
            Floorplanner(moduleList)

        BSV(moduleList)
        FPGAProgram(moduleList)
        Synthesize(moduleList)

        if (not moduleList.getAWBParam('bsv_tool', 'BUILD_LOGS_ONLY')):
            PostSynthesize(moduleList)
        else:
            li_module.dump_lim_graph(moduleList)

        if (moduleList.getAWBParam('software_tool', 'BUILD_FIRST_PASS_SOFTWARE')):
            Software(moduleList)