def __init__(self, platform, spiflash="spiflash_1x", **kwargs): if 'integrated_rom_size' not in kwargs: kwargs['integrated_rom_size']=0x8000 if 'integrated_sram_size' not in kwargs: kwargs['integrated_sram_size']=0x8000 clk_freq = int(100e6) SoCSDRAM.__init__(self, platform, clk_freq, with_uart=False, **kwargs) self.submodules.crg = _CRG(platform) self.crg.cd_sys.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(clk_freq)) uart_interfaces = [RS232PHYInterface() for i in range(2)] self.submodules.uart = UART(uart_interfaces[0]) self.submodules.bridge = WishboneStreamingBridge(uart_interfaces[1], self.clk_freq) self.add_wb_master(self.bridge.wishbone) self.submodules.uart_phy = RS232PHY(platform.request("serial"), self.clk_freq, 115200) self.submodules.uart_multiplexer = RS232PHYMultiplexer(uart_interfaces, self.uart_phy) self.comb += self.uart_multiplexer.sel.eq(platform.request("user_sw", 0)) # Basic peripherals self.submodules.info = info.Info(platform, self.__class__.__name__) self.submodules.oled = oled.OLED(platform.request("oled")) # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) self.add_constant("READ_LEVELING_BITSLIP", 3) self.add_constant("READ_LEVELING_DELAY", 14) sdram_module = MT41K256M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings( with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True)) # spi flash spiflash_pads = platform.request(spiflash) spiflash_pads.clk = Signal() self.specials += Instance("STARTUPE2", i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0, i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1) spiflash_dummy = { "spiflash_1x": 9, "spiflash_4x": 11, } self.submodules.spiflash = spi_flash.SpiFlash( spiflash_pads, dummy=spiflash_dummy[spiflash], div=2) self.add_constant("SPIFLASH_PAGE_SIZE", 256) self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000) self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]), self.spiflash.bus) self.add_memory_region( "spiflash", self.mem_map["spiflash"], 16*1024*1024) self.add_interrupt("uart")
def __init__(self, platform, **kwargs): clk_freq = 50 * 1000000 SoCSDRAM.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x4000, **kwargs) self.submodules.crg = _CRG(platform, clk_freq) self.submodules.dna = dna.DNA() # front panel (ATX) self.submodules.front_panel = FrontPanelGPIO(platform, clk_freq) self.comb += self.crg.reset.eq(self.front_panel.reset) # sdram self.submodules.ddrphy = s6ddrphy.S6QuarterRateDDRPHY( platform.request("ddram"), rd_bitslip=0, wr_bitslip=4, dqs_ddr_alignment="C0") sdram_module = MT41J128M16(self.clk_freq, "1:4") controller_settings = ControllerSettings(with_bandwidth=True) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) self.comb += [ self.ddrphy.clk8x_wr_strb.eq(self.crg.clk8x_wr_strb), self.ddrphy.clk8x_rd_strb.eq(self.crg.clk8x_rd_strb), ] self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / clk_freq)
def __init__(self, platform, **kwargs): clk_freq = int(100e6) SoCSDRAM.__init__(self, platform, clk_freq, l2_size=32, integrated_rom_size=0x8000, integrated_sram_size=0x8000, ident="Arty DMA Test SoC", ident_version=True, reserve_nmi_interrupt=False, **kwargs) self.submodules.crg = CRG(platform) self.submodules.dna = dna.DNA() self.submodules.xadc = xadc.XADC() self.crg.cd_sys.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(100e6)) # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) sdram_module = MT41J128M16(self.clk_freq, "1:4") self.add_constant("READ_LEVELING_BITSLIP", 3) self.add_constant("READ_LEVELING_DELAY", 14) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings( with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True))
def __init__(self, platform, **kwargs): clk_freq = 100 * 1000000 SoCSDRAM.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x8000, ident="NeTV2 LiteX Base SoC", **kwargs) self.submodules.crg = _CRG(platform) # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) self.add_constant("A7DDRPHY_BITSLIP", 2) self.add_constant("A7DDRPHY_DELAY", 8) sdram_module = MT41J128M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings( with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True)) # sdram bist generator_port = self.sdram.crossbar.get_port(mode="write") self.submodules.generator = LiteDRAMBISTGenerator(generator_port) checker_port = self.sdram.crossbar.get_port(mode="read") self.submodules.checker = LiteDRAMBISTChecker(checker_port)
def __init__(self, **kwargs): if 'integrated_rom_size' not in kwargs: kwargs['integrated_rom_size'] = 0x8000 if 'integrated_sram_size' not in kwargs: kwargs['integrated_sram_size'] = 0x8000 clk_freq = (83 + Fraction(1, 3)) * 1000 * 1000 platform = pipistrello.Platform() SoCSDRAM.__init__(self, platform, clk_freq, **kwargs) self.submodules.crg = _CRG(platform, clk_freq) self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / clk_freq) bios_size = 0x8000 # sdram sdram_module = MT46H32M16(self.clk_freq, "1:2") self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY( platform.request("ddram"), sdram_module.memtype, rd_bitslip=1, wr_bitslip=3, dqs_ddr_alignment="C1") self.add_csr("ddrphy") controller_settings = ControllerSettings(with_bandwidth=True) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) self.comb += [ self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb), ]
def __init__(self, platform, csr_data_width=8, **kwargs): dict_set_max(kwargs, 'integrated_rom_size', 0x8000) dict_set_max(kwargs, 'integrated_sram_size', 0x8000) clk_freq = int(100e6) SoCSDRAM.__init__(self, platform, clk_freq, csr_data_width=csr_data_width, **kwargs) self.submodules.crg = _CRG(platform) self.crg.cd_sys.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(clk_freq)) # Basic peripherals self.submodules.info = info.Info(platform, self.__class__.__name__) self.add_csr("info") self.submodules.cas = cas.ControlAndStatus(platform, clk_freq) self.add_csr("cas") bios_size = 0x8000 # sdram sdram_module = K4B2G1646F(self.clk_freq, "1:4") self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) self.add_csr("ddrphy") controller_settings = ControllerSettings(with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings)
def __init__(self, platform, **kwargs): clk_freq = (31 + Fraction(1, 4)) * 1000 * 1000 SoCSDRAM.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x4000, **kwargs) self.submodules.crg = _CRG(platform, clk_freq) # sdram sdram_module = MT46H32M16(self.clk_freq, "1:2") self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY( platform.request("ddram"), sdram_module.memtype, rd_bitslip=2, wr_bitslip=3, dqs_ddr_alignment="C1") controller_settings = ControllerSettings(with_bandwidth=True) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) self.comb += [ self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb), ]
def __init__(self, platform, **kwargs): # Need a larger integrated ROM to fit the BIOS with TFTP support. dict_set_max(kwargs, 'integrated_rom_size', 0x10000) clk_freq = (31 + Fraction(1, 4))*1000*1000 SoCSDRAM.__init__(self, platform, clk_freq, **kwargs) self.submodules.crg = _CRG(platform, clk_freq) # sdram if not self.integrated_main_ram_size: sdram_module = MT46H32M16(clk_freq, "1:2") self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY( platform.request("ddram"), sdram_module.memtype, rd_bitslip=2, wr_bitslip=3, dqs_ddr_alignment="C1" ) self.add_csr("ddrphy") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings( with_bandwidth=True) ) self.comb += [ self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb), ]
def __init__(self, platform, **kwargs): clk_freq = 100 * 1000000 SoCSDRAM.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x8000, **kwargs) self.submodules.crg = _CRG(platform) self.submodules.dna = dna.DNA() self.submodules.xadc = xadc.XADC() self.submodules.oled = oled.OLED(platform.request("oled")) # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) self.add_constant("A7DDRPHY_BITSLIP", 2) self.add_constant("A7DDRPHY_DELAY", 8) sdram_module = MT41K256M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings( with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True))
def __init__(self, platform, **kwargs): cpu_reset_address = self.mem_map["spiflash"] + platform.gateware_size clk_freq = (83 + Fraction(1, 3)) * 1000 * 1000 SoCSDRAM.__init__( self, platform, clk_freq, #integrated_rom_size=0x8000, integrated_rom_size=None, integrated_sram_size=0x4000, uart_baudrate=(19200, 115200)[int(os.environ.get('JIMMO', '0'))], cpu_reset_address=cpu_reset_address, **kwargs) self.submodules.crg = _CRG(platform, clk_freq) self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / clk_freq) # Basic peripherals self.submodules.info = info.Info(platform, self.__class__.__name__) self.submodules.cas = cas.ControlAndStatus(platform, clk_freq) # spi flash self.submodules.spiflash = spi_flash.SpiFlashSingle( platform.request("spiflash"), dummy=platform.spiflash_read_dummy_bits, div=platform.spiflash_clock_div) self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size) self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size) self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=platform.spiflash_total_size) bios_size = 0x8000 self.add_constant("ROM_DISABLE", 1) self.add_memory_region("rom", cpu_reset_address, bios_size) self.flash_boot_address = self.mem_map[ "spiflash"] + platform.gateware_size + bios_size # sdram sdram_module = MT46H32M16(self.clk_freq, "1:2") self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY( platform.request("ddram"), sdram_module.memtype, rd_bitslip=1, wr_bitslip=3, dqs_ddr_alignment="C1") controller_settings = ControllerSettings(with_bandwidth=True) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) self.comb += [ self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb), ]
def __init__(self, platform, spiflash="spiflash_1x", **kwargs): clk_freq = int(100e6) SoCSDRAM.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x8000, **kwargs) self.submodules.crg = _CRG(platform) self.crg.cd_sys.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(clk_freq)) # Basic peripherals self.submodules.info = info.Info(platform, self.__class__.__name__) self.submodules.leds = led.ClassicLed( Cat(platform.request("user_led", i) for i in range(4))) self.submodules.rgb_leds = led.RGBLed(platform.request("rgb_leds")) # spi flash spiflash_pads = platform.request(spiflash) spiflash_pads.clk = Signal() self.specials += Instance("STARTUPE2", i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0, i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1) spiflash_dummy = { "spiflash_1x": 9, "spiflash_4x": 11, } self.submodules.spiflash = spi_flash.SpiFlash( spiflash_pads, dummy=spiflash_dummy[spiflash], div=2) self.add_constant("SPIFLASH_PAGE_SIZE", 256) self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000) self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]), self.spiflash.bus) self.add_memory_region("spiflash", self.mem_map["spiflash"] | self.shadow_base, 16 * 1024 * 1024) # sdram sdram_module = MT41K128M16(self.clk_freq, "1:4") self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) self.add_constant("READ_LEVELING_BITSLIP", 3) self.add_constant("READ_LEVELING_DELAY", 14) controller_settings = ControllerSettings(with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings)
def __init__(self, platform, **kwargs): dict_set_max(kwargs, 'integrated_rom_size', 0x8000) dict_set_max(kwargs, 'integrated_sram_size', 0x4000) kwargs['uart_baudrate'] = 230400 sys_clk_freq = int(75 * 1000 * 1000) # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / sys_clk_freq) # Basic peripherals ------------------------------------------------------------------------ self.submodules.info = info.Info(platform, self.__class__.__name__) self.add_csr("info") self.submodules.cas = cas.ControlAndStatus(platform, sys_clk_freq) self.add_csr("cas") # Memory mapped SPI Flash ------------------------------------------------------------------ self.submodules.spiflash = spi_flash.SpiFlashSingle( platform.request("spiflash"), dummy=platform.spiflash_read_dummy_bits, div=platform.spiflash_clock_div) self.add_csr("spiflash") self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size) self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size) self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=platform.spiflash_total_size) bios_size = 0x8000 self.flash_boot_address = self.mem_map[ "spiflash"] + platform.gateware_size + bios_size self.add_constant("FLASH_BOOT_ADDRESS", self.flash_boot_address) # SDRAM ------------------------------------------------------------------------------------ sdram_module = MT47H32M16(self.sys_clk_freq, "1:2") self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY( platform.request("ddram"), sdram_module.memtype, rd_bitslip=0, wr_bitslip=4, dqs_ddr_alignment="C0") controller_settings = ControllerSettings(with_bandwidth=True) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) self.comb += [ self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb), ]
def __init__(self, platform, **kwargs): dict_set_max(kwargs, 'integrated_rom_size', 0x8000) dict_set_max(kwargs, 'integrated_sram_size', 0x4000) sys_clk_freq = (31 + Fraction(1, 4)) * 1000 * 1000 # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR2 SDRAM ------------------------------------------------------------------------------- if True: sdram_module = MT46H32M16(sys_clk_freq, "1:2") self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY( platform.request("ddram"), memtype=sdram_module.memtype, rd_bitslip=2, wr_bitslip=3, dqs_ddr_alignment="C1") self.add_csr("ddrphy") controller_settings = ControllerSettings(with_bandwidth=True) self.register_sdram(self.ddrphy, geom_settings=sdram_module.geom_settings, timing_settings=sdram_module.timing_settings, controller_settings=controller_settings) self.comb += [ self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb), ] # Basic peripherals ------------------------------------------------------------------------ # info module self.submodules.info = info.Info(platform, self.__class__.__name__) self.add_csr("info") # control and status module #self.submodules.cas = cas.ControlAndStatus(platform, sys_clk_freq) self.add_csr("cas") # Add debug interface if the CPU has one --------------------------------------------------- if hasattr(self.cpu, "debug_bus"): self.register_mem(name="vexriscv_debug", address=0xf00f0000, interface=self.cpu.debug_bus, size=0x100) # Memory mapped SPI Flash ------------------------------------------------------------------ # TODO: Add SPI Flash support here. # Support for soft-emulation for full Linux support ---------------------------------------- if self.cpu_type == "vexriscv" and self.cpu_variant == "linux": size = 0x4000 self.submodules.emulator_ram = wishbone.SRAM(size) self.register_mem("emulator_ram", self.mem_map["emulator_ram"], self.emulator_ram.bus, size)
def __init__(self, platform, **kwargs): clk_freq = (83 + Fraction(1, 3)) * 1000 * 1000 SoCSDRAM.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x4000, with_uart=False, **kwargs) self.submodules.crg = _CRG(platform, clk_freq) self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / clk_freq) self.submodules.info = info.Info(platform, "pipi", self.__class__.__name__[:8]) # self.submodules.fx2_reset = gpio.GPIOOut(platform.request("fx2_reset")) # self.submodules.fx2_hack = i2c_hack.I2CShiftReg(platform.request("opsis_eeprom")) self.submodules.suart = shared_uart.SharedUART(self.clk_freq, 115200) self.suart.add_uart_pads(platform.request('fx2_serial')) self.submodules.uart = self.suart.uart self.submodules.spiflash = spi_flash.SpiFlash( platform.request("spiflash4x"), dummy=platform.spiflash_read_dummy_bits, div=platform.spiflash_clock_div) self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size) self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size) self.flash_boot_address = self.mem_map[ "spiflash"] + platform.gateware_size self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=platform.spiflash_total_size) # sdram sdram_module = MT46H32M16(self.clk_freq, "1:2") self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY( platform.request("ddram"), sdram_module.memtype, rd_bitslip=1, wr_bitslip=3, dqs_ddr_alignment="C1") controller_settings = ControllerSettings(with_bandwidth=True) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) self.comb += [ self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb), ]
def __init__(self, platform, **kwargs): clk_freq = 75 * 1000000 SoCSDRAM.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x4000, with_uart=True, **kwargs) self.submodules.crg = _CRG(platform, clk_freq) self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / clk_freq) self.submodules.info = info.Info(platform, "atlys", self.__class__.__name__[:8]) self.submodules.spiflash = spi_flash.SpiFlash( platform.request("spiflash4x"), dummy=platform.spiflash_read_dummy_bits, div=platform.spiflash_clock_div) self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size) self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size) self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=platform.spiflash_total_size) bios_size = 0x8000 self.flash_boot_address = self.mem_map[ "spiflash"] + platform.gateware_size + bios_size #self.submodules.cas = cas.ControlAndStatus(platform, clk_freq) # sdram sdram_module = P3R1GE4JGF(self.clk_freq, "1:2") self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY( platform.request("ddram"), sdram_module.memtype, rd_bitslip=0, wr_bitslip=4, dqs_ddr_alignment="C0") controller_settings = ControllerSettings(with_bandwidth=True) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) self.comb += [ self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb), ]
def __init__(self, platform, **kwargs): if kwargs.get('cpu_type', None) == 'mor1kx': dict_set_max(kwargs, 'integrated_rom_size', 0x10000) else: dict_set_max(kwargs, 'integrated_rom_size', 0x8000) dict_set_max(kwargs, 'integrated_sram_size', 0x8000) sys_clk_freq = (31 + Fraction(1, 4)) * 1000 * 1000 # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / sys_clk_freq) # DDR2 SDRAM ------------------------------------------------------------------------------- if True: sdram_module = MT46H32M16(sys_clk_freq, "1:2") self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY( platform.request("ddram"), memtype=sdram_module.memtype, rd_bitslip=2, wr_bitslip=3, dqs_ddr_alignment="C1") self.add_csr("ddrphy") controller_settings = ControllerSettings(with_bandwidth=True) self.register_sdram(self.ddrphy, geom_settings=sdram_module.geom_settings, timing_settings=sdram_module.timing_settings, controller_settings=controller_settings) self.comb += [ self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb), ] # Basic peripherals ------------------------------------------------------------------------ # info module self.submodules.info = info.Info(platform, self.__class__.__name__) self.add_csr("info") # control and status module #self.submodules.cas = cas.ControlAndStatus(platform, sys_clk_freq) self.add_csr("cas") # Add debug interface if the CPU has one --------------------------------------------------- if hasattr(self.cpu, "debug_bus"): self.register_mem(name="vexriscv_debug", address=0xf00f0000, interface=self.cpu.debug_bus, size=0x100)
def __init__(self, platform, **kwargs): if 'integrated_rom_size' not in kwargs: kwargs['integrated_rom_size'] = 0x8000 if 'integrated_sram_size' not in kwargs: kwargs['integrated_sram_size'] = 0x4000 clk_freq = (83 + Fraction(1, 3)) * 1000 * 1000 SoCSDRAM.__init__(self, platform, clk_freq, **kwargs) self.submodules.crg = _CRG(platform, clk_freq) self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / clk_freq) self.submodules.info = info.Info(platform, self.__class__.__name__) self.submodules.spiflash = spi_flash.SpiFlash( platform.request("spiflash4x"), dummy=platform.spiflash_read_dummy_bits, div=platform.spiflash_clock_div) self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size) self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size) self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=platform.spiflash_total_size) bios_size = 0x8000 self.flash_boot_address = self.mem_map[ "spiflash"] + platform.gateware_size + bios_size self.add_constant("FLASH_BOOT_ADDRESS", self.flash_boot_address) # sdram sdram_module = MT46H32M16(self.clk_freq, "1:2") self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY( platform.request("ddram"), sdram_module.memtype, rd_bitslip=1, wr_bitslip=3, dqs_ddr_alignment="C1") controller_settings = ControllerSettings(with_bandwidth=True) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) self.comb += [ self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb), ]
def __init__(self, platform, **kwargs): kwargs['cpu_type'] = None clk_freq = 100 * 1000000 SoCSDRAM.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x8000, ident="NeTV2 LiteX Base SoC", with_uart=False, **kwargs) self.add_cpu_or_bridge( UARTWishboneBridge(platform.request("serial"), self.clk_freq, baudrate=115200)) self.add_wb_master(self.cpu_or_bridge.wishbone) self.submodules.crg = _CRG(platform) self.submodules.dna = dna.DNA() self.submodules.xadc = xadc.XADC() # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) self.add_constant("A7DDRPHY_BITSLIP", 2) self.add_constant("A7DDRPHY_DELAY", 8) sdram_module = MT41J128M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings( with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True)) # sdram bist ddr_generator_port = self.sdram.crossbar.get_port(mode="write") self.submodules.ddr_generator = LiteDRAMBISTGenerator( ddr_generator_port) ddr_checker_port = self.sdram.crossbar.get_port(mode="read") self.submodules.ddr_checker = LiteDRAMBISTChecker(ddr_checker_port) # led blink counter = Signal(32) self.sync += counter.eq(counter + 1) self.comb += platform.request("user_led", 0).eq(counter[26])
def __init__(self, platform, **kwargs): clk_freq = int(100e6) SoCSDRAM.__init__( self, platform, clk_freq, integrated_rom_size=0x5000, integrated_sram_size=0x4000, #shadow_base=0x00000000, ident="NeTV2 LiteX Base SoC", reserve_nmi_interrupt=False, cpu_type="vexriscv", cpu_variant="debug", **kwargs) self.comb += self.uart.reset.eq(self.cpu_or_bridge.debug_reset) self.submodules.crg = CRG(platform) # self.submodules.dna = dna.DNA() self.submodules.xadc = xadc.XADC() self.crg.cd_sys.clk.attr.add("keep") platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(100e6)) # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) sdram_module = MT41J128M16(self.clk_freq, "1:4") self.add_constant("READ_LEVELING_BITSLIP", 3) self.add_constant("READ_LEVELING_DELAY", 14) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings( with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True)) # common led self.sys_led = Signal() self.pcie_led = Signal() self.comb += platform.request("fpga_led0", 0).eq( self.sys_led ^ self.pcie_led) #TX0 green self.comb += platform.request("fpga_led1", 0).eq(0) #TX0 red # sys led sys_counter = Signal(32) self.sync += sys_counter.eq(sys_counter + 1) self.comb += self.sys_led.eq(sys_counter[26])
def __init__(self, platform, **kwargs): clk_freq = int(100e6) SoCSDRAM.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x8000, ident="NeTV2 LiteX Base SoC", **kwargs) self.submodules.crg = _CRG(platform) self.crg.cd_sys.clk.attr.add("keep") #self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(clk_freq)) # Basic peripherals self.submodules.info = info.Info(platform, self.__class__.__name__) # sdram sdram_module = MT41J128M16(self.clk_freq, "1:4") self.submodules.ddrphy = a7ddrphy.A7DDRPHY( platform.request("ddram")) self.add_constant("A7DDRPHY_BITSLIP", 2) self.add_constant("A7DDRPHY_DELAY", 8) controller_settings = ControllerSettings( with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) # common led self.sys_led = Signal() self.pcie_led = Signal() self.comb += platform.request("user_led", 0).eq(self.sys_led ^ self.pcie_led) #checker_port = self.sdram.crossbar.get_port(mode="read") #self.submodules.checker = LiteDRAMBISTChecker(checker_port) # led blink #counter = Signal(32) #self.sync.clk125 += counter.eq(counter + 1) #self.comb += platform.request("user_led", 0).eq(counter[26]) # sys led sys_counter = Signal(32) self.sync += sys_counter.eq(sys_counter + 1) self.comb += self.sys_led.eq(sys_counter[26])
def __init__(self, platform, **kwargs): if 'integrated_rom_size' not in kwargs: kwargs['integrated_rom_size'] = 0x8000 if 'integrated_sram_size' not in kwargs: kwargs['integrated_sram_size'] = 0x8000 clk_freq = int(50e6) SoCSDRAM.__init__(self, platform, clk_freq, **kwargs) self.submodules.crg = _CRG(platform) self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / clk_freq) self.submodules.info = info.Info(platform, self.__class__.__name__) self.submodules.cas = cas.ControlAndStatus(platform, clk_freq) gmii_rst_n = platform.request("gmii_rst_n") self.comb += [gmii_rst_n.eq(1)] if self.cpu_type == "vexriscv" and self.cpu_variant == "linux": size = 0x4000 self.submodules.emulator_ram = wishbone.SRAM(size) self.register_mem("emulator_ram", self.mem_map["emulator_ram"], self.emulator_ram.bus, size) # sdram sdram_module = MT47H32M16(self.clk_freq, "1:2") self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY( platform.request("ddram_b"), sdram_module.memtype, rd_bitslip=0, wr_bitslip=4, dqs_ddr_alignment="C0") controller_settings = ControllerSettings(with_bandwidth=True) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) self.comb += [ self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb), ]
def __init__(self, platform, spiflash="spiflash_1x", **kwargs): if kwargs.get('cpu_type', None) == 'mor1kx': dict_set_max(kwargs, 'integrated_rom_size', 0x10000) else: dict_set_max(kwargs, 'integrated_rom_size', 0x8000) dict_set_max(kwargs, 'integrated_sram_size', 0x4000) sys_clk_freq = 50 * 1000000 # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if True: sdram_module = MT41J128M16(self.clk_freq, "1:4") self.submodules.ddrphy = s6ddrphy.S6QuarterRateDDRPHY( platform.request("ddram"), rd_bitslip=0, wr_bitslip=4, dqs_ddr_alignment="C0") controller_settings = ControllerSettings(with_bandwidth=True) self.add_csr("ddrphy") self.register_sdram(self.ddrphy, geom_settings=sdram_module.geom_settings, timing_settings=sdram_module.timing_settings, controller_settings=controller_settings) self.comb += [ self.ddrphy.clk8x_wr_strb.eq(self.crg.clk8x_wr_strb), self.ddrphy.clk8x_rd_strb.eq(self.crg.clk8x_rd_strb), ] # Basic peripherals ------------------------------------------------------------------------ self.submodules.info = info.Info(platform, self.__class__.__name__) self.add_csr("info") self.submodules.cas = cas.ControlAndStatus(platform, sys_clk_freq) self.add_csr("cas")
def __init__(self, platform, csr_data_width=8, **kwargs): if 'integrated_rom_size' not in kwargs: kwargs['integrated_rom_size'] = 0x8000 if 'integrated_sram_size' not in kwargs: kwargs['integrated_sram_size'] = 0x8000 clk_freq = int(100e6) SoCSDRAM.__init__(self, platform, clk_freq, csr_data_width=csr_data_width, **kwargs) self.submodules.crg = _CRG(platform) self.crg.cd_sys.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(clk_freq)) # Basic peripherals self.submodules.info = info.Info(platform, self.__class__.__name__) self.submodules.cas = cas.ControlAndStatus(platform, clk_freq) if self.cpu_type == "vexriscv" and self.cpu_variant == "linux": size = 0x4000 self.submodules.emulator_ram = wishbone.SRAM(size) self.register_mem("emulator_ram", self.mem_map["emulator_ram"], self.emulator_ram.bus, size) bios_size = 0x8000 # sdram sdram_module = K4B2G1646F(self.clk_freq, "1:4") self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) controller_settings = ControllerSettings(with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings)
def __init__(self, platform, **kwargs): if 'integrated_rom_size' not in kwargs: kwargs['integrated_rom_size']=0x8000 if 'integrated_sram_size' not in kwargs: kwargs['integrated_sram_size']=0x8000 clk_freq = (31 + Fraction(1, 4))*1000*1000 SoCSDRAM.__init__(self, platform, clk_freq, **kwargs) self.submodules.crg = _CRG(platform, clk_freq) if self.cpu_type == "vexriscv" and self.cpu_variant == "linux": size = 0x4000 self.submodules.emulator_ram = wishbone.SRAM(size) self.register_mem("emulator_ram", self.mem_map["emulator_ram"], self.emulator_ram.bus, size) # sdram if not self.integrated_main_ram_size: sdram_module = MT46H32M16(clk_freq, "1:2") self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY( platform.request("ddram"), sdram_module.memtype, rd_bitslip=2, wr_bitslip=3, dqs_ddr_alignment="C1" ) self.add_csr("ddrphy") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings( with_bandwidth=True) ) self.comb += [ self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb), ]
def __init__(self, platform, **kwargs): clk_freq = int(100e6) SoCSDRAM.__init__(self, platform, clk_freq, integrated_rom_size=0x6000, integrated_sram_size=0x4000, #shadow_base=0x00000000, ident="NeTV2 LiteX Reversing SoC", reserve_nmi_interrupt=False, **kwargs) self.submodules.crg = CRG(platform) self.submodules.dna = dna.DNA() self.crg.cd_sys.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(100e6)) # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) sdram_module = MT41J128M16(self.clk_freq, "1:4") self.add_constant("READ_LEVELING_BITSLIP", 3) self.add_constant("READ_LEVELING_DELAY", 14) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings(with_bandwidth=True, cmd_buffer_depth=8, with_refresh=False)) # common led self.sys_led = Signal() self.pcie_led = Signal() self.comb += platform.request("user_led", 0).eq(self.sys_led ^ self.pcie_led) # sys led sys_counter = Signal(32) self.sync += sys_counter.eq(sys_counter + 1) self.comb += self.sys_led.eq(sys_counter[26])
def __init__(self, platform, **kwargs): clk_freq = 50 * 1000000 if 'expansion' in kwargs: tofe_board_name = kwargs.get('expansion') del kwargs['expansion'] else: tofe_board_name = None SoCSDRAM.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x4000, with_uart=True, **kwargs) self.submodules.crg = _CRG(platform, clk_freq) self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / clk_freq) # sdram sdram_module = MT41J128M16(self.clk_freq, "1:4") self.submodules.ddrphy = s6ddrphy.S6QuarterRateDDRPHY( platform.request("ddram"), rd_bitslip=0, wr_bitslip=4, dqs_ddr_alignment="C0") controller_settings = ControllerSettings(with_bandwidth=True) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) self.comb += [ self.ddrphy.clk8x_wr_strb.eq(self.crg.clk8x_wr_strb), self.ddrphy.clk8x_rd_strb.eq(self.crg.clk8x_rd_strb), ]
def __init__(self, platform, **kwargs): if kwargs.get('cpu_type', None) == "mor1kx": dict_set_max(kwargs, 'integrated_rom_size', 0x10000) else: dict_set_max(kwargs, 'integrated_rom_size', 0x8000) dict_set_max(kwargs, 'integrated_sram_size', 0x8000) sys_clk_freq = 50*1000000 if 'expansion' in kwargs: tofe_board_name = kwargs.get('expansion') del kwargs['expansion'] else: tofe_board_name = None # disable uart kwargs['with_uart'] = False # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq) # Add specialized uart --------------------------------------------------------------------- self.submodules.suart = shared_uart.SharedUART(self.clk_freq, 115200) self.suart.add_uart_pads(platform.request('fx2_serial')) self.submodules.uart = self.suart.uart self.add_csr("uart") self.add_interrupt("uart") # DDR3 SDRAM ------------------------------------------------------------------------------- if True: sdram_module = MT41J128M16(sys_clk_freq, "1:4") self.submodules.ddrphy = s6ddrphy.S6QuarterRateDDRPHY( platform.request("ddram"), rd_bitslip = 0, wr_bitslip = 4, dqs_ddr_alignment="C0") self.add_csr("ddrphy") controller_settings = ControllerSettings( with_bandwidth=True) self.register_sdram( self.ddrphy, geom_settings = sdram_module.geom_settings, timing_settings = sdram_module.timing_settings, controller_settings=controller_settings) self.comb += [ self.ddrphy.clk8x_wr_strb.eq(self.crg.clk8x_wr_strb), self.ddrphy.clk8x_rd_strb.eq(self.crg.clk8x_rd_strb), ] # Basic peripherals ------------------------------------------------------------------------ # info module self.submodules.info = info.Info(platform, self.__class__.__name__) self.add_csr("info") # control and status module #self.submodules.cas = cas.ControlAndStatus(platform, sys_clk_freq) self.add_csr("cas") # opsis specific i2c module self.submodules.opsis_i2c = opsis_i2c.OpsisI2C(platform) self.add_csr("opsis_i2c") # front panel (ATX) module self.submodules.front_panel = FrontPanelGPIO(platform, sys_clk_freq) self.comb += self.crg.reset.eq(self.front_panel.reset) self.add_csr("front_panel") # Expansion boards ------------------------------------------------------------------------- if tofe_board_name: if tofe_board_name == 'lowspeedio': self.submodules.tofe = tofe.TOFEBoard(tofe_board_name)(platform, self.suart) else: self.submodules.tofe = tofe.TOFEBoard(tofe_board_name)(platform) # Add debug interface if the CPU has one --------------------------------------------------- if hasattr(self.cpu, "debug_bus"): self.register_mem( name="vexriscv_debug", address=0xf00f0000, interface=self.cpu.debug_bus, size=0x100) # Memory mapped SPI Flash ------------------------------------------------------------------ self.submodules.spiflash = spi_flash.SpiFlash( platform.request("spiflash4x"), dummy=platform.spiflash_read_dummy_bits, div=platform.spiflash_clock_div, endianness=self.cpu.endianness) self.add_csr("spiflash") self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size) self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size) self.add_constant("SPIFLASH_TOTAL_SIZE", platform.spiflash_total_size) self.add_wb_slave( self.mem_map["spiflash"], self.spiflash.bus, platform.spiflash_total_size) self.add_memory_region( "spiflash", self.mem_map["spiflash"], platform.spiflash_total_size) bios_size = 0x8000 self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size+bios_size define_flash_constants(self)
def __init__(self, platform, **kwargs): clk_freq = 50 * 1000000 if 'tofe_board' in kwargs: tofe_board_name = kwargs.get('tofe_board') del kwargs['tofe_board'] else: tofe_board_name = None SoCSDRAM.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x4000, with_uart=False, **kwargs) self.submodules.crg = _CRG(platform, clk_freq) self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / clk_freq) self.submodules.info = info.Info(platform, "opsis", self.__class__.__name__[:8]) self.submodules.opsis_i2c = opsis_i2c.OpsisI2C(platform) self.submodules.suart = shared_uart.SharedUART(self.clk_freq, 115200) self.suart.add_uart_pads(platform.request('fx2_serial')) self.submodules.uart = self.suart.uart self.submodules.spiflash = spi_flash.SpiFlash( platform.request("spiflash4x"), dummy=platform.spiflash_read_dummy_bits, div=platform.spiflash_clock_div) self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size) self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size) self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=platform.spiflash_total_size) bios_size = 0x8000 self.flash_boot_address = self.mem_map[ "spiflash"] + platform.gateware_size + bios_size # front panel (ATX) self.submodules.front_panel = FrontPanelGPIO(platform, clk_freq) self.comb += self.crg.reset.eq(self.front_panel.reset) # sdram sdram_module = MT41J128M16(self.clk_freq, "1:4") self.submodules.ddrphy = s6ddrphy.S6QuarterRateDDRPHY( platform.request("ddram"), rd_bitslip=0, wr_bitslip=4, dqs_ddr_alignment="C0") controller_settings = ControllerSettings(with_bandwidth=True) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) self.comb += [ self.ddrphy.clk8x_wr_strb.eq(self.crg.clk8x_wr_strb), self.ddrphy.clk8x_rd_strb.eq(self.crg.clk8x_rd_strb), ] if tofe_board_name: if tofe_board_name == 'lowspeedio': self.submodules.tofe = tofe.TOFEBoard(tofe_board_name)( platform, self.suart) else: self.submodules.tofe = tofe.TOFEBoard(tofe_board_name)( platform)
def __init__(self, platform, **kwargs): dict_set_max(kwargs, 'integrated_rom_size', 0x8000) dict_set_max(kwargs, 'integrated_sram_size', 0x4000) sys_clk_freq = (83 + Fraction(1, 3)) * 1000 * 1000 # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / sys_clk_freq) # DDR2 SDRAM ------------------------------------------------------------------------------- if True: sdram_module = MT46H32M16(sys_clk_freq, "1:2") self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY( platform.request("ddram"), memtype=sdram_module.memtype, rd_bitslip=1, wr_bitslip=3, dqs_ddr_alignment="C1") self.add_csr("ddrphy") controller_settings = ControllerSettings(with_bandwidth=True) self.register_sdram(self.ddrphy, geom_settings=sdram_module.geom_settings, timing_settings=sdram_module.timing_settings, controller_settings=controller_settings) self.comb += [ self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb), ] # Basic peripherals ------------------------------------------------------------------------ # info module self.submodules.info = info.Info(platform, self.__class__.__name__) self.add_csr("info") # control and status module #self.submodules.cas = cas.ControlAndStatus(platform, sys_clk_freq) self.add_csr("cas") # Add debug interface if the CPU has one --------------------------------------------------- if hasattr(self.cpu, "debug_bus"): self.register_mem(name="vexriscv_debug", address=0xf00f0000, interface=self.cpu.debug_bus, size=0x100) # Memory mapped SPI Flash ------------------------------------------------------------------ self.submodules.spiflash = spi_flash.SpiFlash( platform.request("spiflash4x"), dummy=platform.spiflash_read_dummy_bits, div=platform.spiflash_clock_div, endianness=self.cpu.endianness) self.add_csr("spiflash") self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size) self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size) self.add_constant("SPIFLASH_TOTAL_SIZE", platform.spiflash_total_size) self.add_wb_slave(self.mem_map["spiflash"], self.spiflash.bus, platform.spiflash_total_size) self.add_memory_region("spiflash", self.mem_map["spiflash"], platform.spiflash_total_size) bios_size = 0x8000 self.flash_boot_address = self.mem_map[ "spiflash"] + platform.gateware_size + bios_size define_flash_constants(self) # Support for soft-emulation for full Linux support ---------------------------------------- if self.cpu_type == "vexriscv" and self.cpu_variant == "linux": size = 0x4000 self.submodules.emulator_ram = wishbone.SRAM(size) self.register_mem("emulator_ram", self.mem_map["emulator_ram"], self.emulator_ram.bus, size)
def __init__(self, platform, spiflash="spiflash_1x", **kwargs): if kwargs.get('cpu_type', None) == 'mor1kx': dict_set_max(kwargs, 'integrated_rom_size', 0x10000) else: dict_set_max(kwargs, 'integrated_rom_size', 0x8000) dict_set_max(kwargs, 'integrated_sram_size', 0x8000) sys_clk_freq = int(100e6) # disable uart kwargs['with_uart'] = False # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) self.crg.cd_sys.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if True: sdram_module = MT41K256M16(sys_clk_freq, "1:4") self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype=sdram_module.memtype, nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.add_constant("READ_LEVELING_BITSLIP", 3) self.add_constant("READ_LEVELING_DELAY", 14) self.register_sdram(self.ddrphy, geom_settings=sdram_module.geom_settings, timing_settings=sdram_module.timing_settings, controller_settings=ControllerSettings( with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True)) # Extended UART ---------------------------------------------------------------------------- uart_interfaces = [RS232PHYInterface() for i in range(2)] self.submodules.uart = UART(uart_interfaces[0]) self.submodules.bridge = Stream2Wishbone(uart_interfaces[1], sys_clk_freq) self.add_wb_master(self.bridge.wishbone) self.add_csr("uart") self.add_interrupt("uart") self.submodules.uart_phy = RS232PHY(platform.request("serial"), self.clk_freq, 115200) self.submodules.uart_multiplexer = RS232PHYMultiplexer( uart_interfaces, self.uart_phy) self.comb += self.uart_multiplexer.sel.eq( platform.request("user_sw", 0)) self.add_csr("uart_phy") # Basic peripherals ------------------------------------------------------------------------ self.submodules.info = info.Info(platform, self.__class__.__name__) self.add_csr("info") # self.submodules.cas = cas.ControlAndStatus(platform, sys_clk_freq) # self.add_csr("cas") self.submodules.oled = oled.OLED(platform.request("oled")) self.add_csr("oled") # Add debug interface if the CPU has one --------------------------------------------------- if hasattr(self.cpu, "debug_bus"): self.register_mem(name="vexriscv_debug", address=0xf00f0000, interface=self.cpu.debug_bus, size=0x100) # Memory mapped SPI Flash ------------------------------------------------------------------ spiflash_pads = platform.request(spiflash) spiflash_pads.clk = Signal() self.specials += Instance("STARTUPE2", i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0, i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1) spiflash_dummy = { "spiflash_1x": 9, "spiflash_4x": 11, } self.submodules.spiflash = spi_flash.SpiFlash( spiflash_pads, dummy=spiflash_dummy[spiflash], div=platform.spiflash_clock_div, endianness=self.cpu.endianness) self.add_csr("spiflash") self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size) self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size) self.add_constant("SPIFLASH_TOTAL_SIZE", platform.spiflash_total_size) self.add_wb_slave(self.mem_map["spiflash"], self.spiflash.bus, platform.spiflash_total_size) self.add_memory_region("spiflash", self.mem_map["spiflash"], platform.spiflash_total_size) bios_size = 0x8000 self.flash_boot_address = self.mem_map[ "spiflash"] + platform.gateware_size + bios_size self.add_constant("FLASH_BOOT_ADDRESS", self.flash_boot_address)