def test_fifo_default_thresholds(self):
# Verify FIFO with default threshold.
# Defaults: read_threshold=0, write_threshold=depth
read_threshold, write_threshold = (0, 128)
write_port = LiteDRAMNativeWritePort(address_width=32, data_width=32)
read_port = LiteDRAMNativeReadPort(address_width=32, data_width=32)
fifo = LiteDRAMFIFO(data_width=32,
base=0,
depth=write_threshold,
write_port=write_port,
read_port=read_port)
def generator():
yield write_port.cmd.ready.eq(1)
yield write_port.wdata.ready.eq(1)
for i in range(write_threshold):
yield fifo.sink.valid.eq(1)
yield fifo.sink.data.eq(0)
yield
while (yield fifo.sink.ready) == 0:
yield
yield
checker = self.fifo_ctrl_flag_checker(fifo.ctrl, write_threshold,
read_threshold)
run_simulation(fifo, [generator(), checker])
def __init__(self):
self.write_port = LiteDRAMNativeWritePort(address_width=32,
data_width=32)
self.read_port = LiteDRAMNativeReadPort(address_width=32,
data_width=32)
self.submodules.fifo = LiteDRAMFIFO(data_width=32,
depth=32,
base=16,
write_port=self.write_port,
read_port=self.read_port,
read_threshold=8,
write_threshold=32 - 8)
self.memory = DRAMMemory(32, 128)
def __init__(self, host_ip="192.168.1.100", host_udp_port=2000):
SimSoC.__init__(
self,
cpu_type="vexriscv",
integrated_rom_size=0x10000,
uart_name="sim",
with_sdram=True,
with_etherbone=True,
etherbone_mac_address=0x10e2d5000001,
etherbone_ip_address="192.168.1.50",
sdram_module="MT48LC16M16",
sdram_data_width=8,
with_sdcard=True,
)
# Sampler --------------------------------------------------------------------------------
data = Signal(8)
self.sync += data.eq(data + 1)
self.submodules.sampler = Sampler(data)
self.add_csr("sampler")
# DRAMFIFO ---------------------------------------------------------------------------------
from litedram.frontend.fifo import LiteDRAMFIFO
self.submodules.fifo = LiteDRAMFIFO(
data_width=8,
base=0x00000000,
depth=0x01000000, # 16MB
write_port=self.sdram.crossbar.get_port(mode="write",
data_width=8),
read_port=self.sdram.crossbar.get_port(mode="read", data_width=8),
)
# UDPStreamer ------------------------------------------------------------------------------
from liteeth.common import convert_ip
from liteeth.frontend.stream import LiteEthStream2UDPTX
udp_port = self.ethcore.udp.crossbar.get_port(host_udp_port, dw=8)
udp_streamer = LiteEthStream2UDPTX(ip_address=convert_ip(host_ip),
udp_port=host_udp_port,
fifo_depth=1024)
udp_streamer = ClockDomainsRenamer("eth_tx")(udp_streamer)
self.submodules += udp_streamer
udp_cdc = stream.ClockDomainCrossing([("data", 8)], "sys", "eth_tx")
self.submodules += udp_cdc
# Sampler/FIFO/UDPStreamer flow ------------------------------------------------------------
self.comb += self.sampler.source.connect(self.fifo.sink)
self.comb += self.fifo.source.connect(udp_cdc.sink)
self.comb += udp_cdc.source.connect(udp_streamer.sink)
self.comb += udp_streamer.source.connect(udp_port.sink)
def __init__(self, base, depth, data_width=8, address_width=32):
self.write_port = LiteDRAMNativeWritePort(address_width=32,
data_width=data_width)
self.read_port = LiteDRAMNativeReadPort(address_width=32,
data_width=data_width)
self.submodules.fifo = LiteDRAMFIFO(
data_width=data_width,
base=base,
depth=depth,
write_port=self.write_port,
read_port=self.read_port,
)
margin = 8
self.memory = DRAMMemory(data_width, base + depth + margin)
def __init__(self):
# ports
self.write_port = LiteDRAMNativeWritePort(address_width=32,
data_width=32)
self.read_port = LiteDRAMNativeReadPort(address_width=32,
data_width=32)
# fifo
self.submodules.fifo = LiteDRAMFIFO(data_width=32,
depth=64,
base=0,
write_port=self.write_port,
read_port=self.read_port,
read_threshold=8,
write_threshold=64 - 8)
# memory
self.memory = DRAMMemory(32, 256)
def __init__(self, platform, core_config, **kwargs):
platform.add_extension(get_common_ios())
# Parameters -------------------------------------------------------------------------------
sys_clk_freq = core_config["sys_clk_freq"]
cpu_type = core_config["cpu"]
cpu_variant = core_config.get("cpu_variant", "standard")
csr_alignment = core_config.get("csr_alignment", 32)
csr_data_width = core_config.get("csr_data_width", 8)
if cpu_type is None:
kwargs["integrated_rom_size"] = 0
kwargs["integrated_sram_size"] = 0
kwargs["with_uart"] = False
kwargs["with_timer"] = False
kwargs["with_ctrl"] = False
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
cpu_type=cpu_type,
cpu_variant=cpu_variant,
csr_data_width=csr_data_width,
csr_alignment=csr_alignment,
**kwargs)
# CRG --------------------------------------------------------------------------------------
if isinstance(platform, SimPlatform):
self.submodules.crg = CRG(platform.request("clk"))
elif core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
self.submodules.crg = crg = LiteDRAMECP5DDRPHYCRG(
platform, core_config)
elif core_config["sdram_phy"] in [
litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY,
litedram_phys.V7DDRPHY
]:
self.submodules.crg = LiteDRAMS7DDRPHYCRG(platform, core_config)
# DRAM -------------------------------------------------------------------------------------
platform.add_extension(get_dram_ios(core_config))
sdram_module = core_config["sdram_module"](
sys_clk_freq, "1:4" if core_config["memtype"] == "DDR3" else "1:2")
# Sim
if isinstance(platform, SimPlatform):
from litex.tools.litex_sim import get_sdram_phy_settings
sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings
phy_settings = get_sdram_phy_settings(
memtype=sdram_module.memtype,
data_width=core_config["sdram_module_nb"] * 8,
clk_freq=sdram_clk_freq)
self.submodules.ddrphy = SDRAMPHYModel(module=sdram_module,
settings=phy_settings,
clk_freq=sdram_clk_freq)
# ECP5DDRPHY
elif core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
assert core_config["memtype"] in ["DDR3"]
self.submodules.ddrphy = core_config["sdram_phy"](
pads=platform.request("ddram"), sys_clk_freq=sys_clk_freq)
self.comb += crg.stop.eq(self.ddrphy.init.stop)
self.add_constant("ECP5DDRPHY")
sdram_module = core_config["sdram_module"](sys_clk_freq, "1:2")
# S7DDRPHY
elif core_config["sdram_phy"] in [
litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY,
litedram_phys.V7DDRPHY
]:
assert core_config["memtype"] in ["DDR2", "DDR3"]
self.submodules.ddrphy = core_config["sdram_phy"](
pads=platform.request("ddram"),
memtype=core_config["memtype"],
nphases=4 if core_config["memtype"] == "DDR3" else 2,
sys_clk_freq=sys_clk_freq,
iodelay_clk_freq=core_config["iodelay_clk_freq"],
cmd_latency=core_config["cmd_latency"])
self.add_constant("CMD_DELAY", core_config["cmd_delay"])
if core_config["memtype"] == "DDR3":
self.ddrphy.settings.add_electrical_settings(
rtt_nom=core_config["rtt_nom"],
rtt_wr=core_config["rtt_wr"],
ron=core_config["ron"])
self.add_csr("ddrphy")
controller_settings = controller_settings = ControllerSettings(
cmd_buffer_depth=core_config["cmd_buffer_depth"])
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=sdram_module,
origin=self.mem_map["main_ram"],
size=
0x01000000, # Only expose 16MB to the CPU, enough for Init/Calib.
with_soc_interconnect=cpu_type is not None,
l2_cache_size=8,
l2_cache_min_data_width=0,
controller_settings=controller_settings,
)
# DRAM Control/Status ----------------------------------------------------------------------
# Expose calibration status to user.
self.submodules.ddrctrl = LiteDRAMCoreControl()
self.add_csr("ddrctrl")
self.comb += platform.request("init_done").eq(
self.ddrctrl.init_done.storage)
self.comb += platform.request("init_error").eq(
self.ddrctrl.init_error.storage)
# If no CPU, expose a bus control interface to user.
if cpu_type is None:
wb_bus = wishbone.Interface()
self.bus.add_master(master=wb_bus)
platform.add_extension(wb_bus.get_ios("wb_ctrl"))
wb_pads = platform.request("wb_ctrl")
self.comb += wb_bus.connect_to_pads(wb_pads, mode="slave")
# User ports -------------------------------------------------------------------------------
self.comb += [
platform.request("user_clk").eq(ClockSignal()),
platform.request("user_rst").eq(ResetSignal())
]
for name, port in core_config["user_ports"].items():
# Native -------------------------------------------------------------------------------
if port["type"] == "native":
user_port = self.sdram.crossbar.get_port()
platform.add_extension(
get_native_user_port_ios(name, user_port.address_width,
user_port.data_width))
_user_port_io = platform.request("user_port_{}".format(name))
self.comb += [
# cmd
user_port.cmd.valid.eq(_user_port_io.cmd_valid),
_user_port_io.cmd_ready.eq(user_port.cmd.ready),
user_port.cmd.we.eq(_user_port_io.cmd_we),
user_port.cmd.addr.eq(_user_port_io.cmd_addr),
# wdata
user_port.wdata.valid.eq(_user_port_io.wdata_valid),
_user_port_io.wdata_ready.eq(user_port.wdata.ready),
user_port.wdata.we.eq(_user_port_io.wdata_we),
user_port.wdata.data.eq(_user_port_io.wdata_data),
# rdata
_user_port_io.rdata_valid.eq(user_port.rdata.valid),
user_port.rdata.ready.eq(_user_port_io.rdata_ready),
_user_port_io.rdata_data.eq(user_port.rdata.data),
]
# Wishbone -----------------------------------------------------------------------------
elif port["type"] == "wishbone":
user_port = self.sdram.crossbar.get_port()
wb_port = wishbone.Interface(user_port.data_width,
user_port.address_width)
wishbone2native = LiteDRAMWishbone2Native(wb_port, user_port)
self.submodules += wishbone2native
platform.add_extension(
get_wishbone_user_port_ios(name, len(wb_port.adr),
len(wb_port.dat_w)))
_wb_port_io = platform.request("user_port_{}".format(name))
self.comb += [
wb_port.adr.eq(_wb_port_io.adr),
wb_port.dat_w.eq(_wb_port_io.dat_w),
_wb_port_io.dat_r.eq(wb_port.dat_r),
wb_port.sel.eq(_wb_port_io.sel),
wb_port.cyc.eq(_wb_port_io.cyc),
wb_port.stb.eq(_wb_port_io.stb),
_wb_port_io.ack.eq(wb_port.ack),
wb_port.we.eq(_wb_port_io.we),
_wb_port_io.err.eq(wb_port.err),
]
# AXI ----------------------------------------------------------------------------------
elif port["type"] == "axi":
user_port = self.sdram.crossbar.get_port()
axi_port = LiteDRAMAXIPort(
user_port.data_width, user_port.address_width +
log2_int(user_port.data_width // 8), port["id_width"])
axi2native = LiteDRAMAXI2Native(axi_port, user_port)
self.submodules += axi2native
platform.add_extension(
get_axi_user_port_ios(name, axi_port.address_width,
axi_port.data_width,
port["id_width"]))
_axi_port_io = platform.request("user_port_{}".format(name))
self.comb += [
# aw
axi_port.aw.valid.eq(_axi_port_io.awvalid),
_axi_port_io.awready.eq(axi_port.aw.ready),
axi_port.aw.addr.eq(_axi_port_io.awaddr),
axi_port.aw.burst.eq(_axi_port_io.awburst),
axi_port.aw.len.eq(_axi_port_io.awlen),
axi_port.aw.size.eq(_axi_port_io.awsize),
axi_port.aw.id.eq(_axi_port_io.awid),
# w
axi_port.w.valid.eq(_axi_port_io.wvalid),
_axi_port_io.wready.eq(axi_port.w.ready),
axi_port.w.last.eq(_axi_port_io.wlast),
axi_port.w.strb.eq(_axi_port_io.wstrb),
axi_port.w.data.eq(_axi_port_io.wdata),
# b
_axi_port_io.bvalid.eq(axi_port.b.valid),
axi_port.b.ready.eq(_axi_port_io.bready),
_axi_port_io.bresp.eq(axi_port.b.resp),
_axi_port_io.bid.eq(axi_port.b.id),
# ar
axi_port.ar.valid.eq(_axi_port_io.arvalid),
_axi_port_io.arready.eq(axi_port.ar.ready),
axi_port.ar.addr.eq(_axi_port_io.araddr),
axi_port.ar.burst.eq(_axi_port_io.arburst),
axi_port.ar.len.eq(_axi_port_io.arlen),
axi_port.ar.size.eq(_axi_port_io.arsize),
axi_port.ar.id.eq(_axi_port_io.arid),
# r
_axi_port_io.rvalid.eq(axi_port.r.valid),
axi_port.r.ready.eq(_axi_port_io.rready),
_axi_port_io.rlast.eq(axi_port.r.last),
_axi_port_io.rresp.eq(axi_port.r.resp),
_axi_port_io.rdata.eq(axi_port.r.data),
_axi_port_io.rid.eq(axi_port.r.id),
]
# FIFO ---------------------------------------------------------------------------------
elif port["type"] == "fifo":
platform.add_extension(
get_fifo_user_port_ios(name, user_port.data_width))
_user_fifo_io = platform.request("user_fifo_{}".format(name))
fifo = LiteDRAMFIFO(
data_width=user_port.data_width,
base=port["base"],
depth=port["depth"],
write_port=self.sdram.crossbar.get_port("write"),
write_threshold=port["depth"] - 32, # FIXME
read_port=self.sdram.crossbar.get_port("read"),
read_threshold=32 # FIXME
)
self.submodules += fifo
self.comb += [
# in
fifo.sink.valid.eq(_user_fifo_io.in_valid),
_user_fifo_io.in_ready.eq(fifo.sink.ready),
fifo.sink.data.eq(_user_fifo_io.in_data),
# out
_user_fifo_io.out_valid.eq(fifo.source.valid),
fifo.source.ready.eq(_user_fifo_io.out_ready),
_user_fifo_io.out_data.eq(fifo.source.data),
]
else:
raise ValueError("Unsupported port type: {}".format(
port["type"]))
def __init__(self, platform, core_config, **kwargs):
platform.add_extension(get_common_ios())
# Parameters -------------------------------------------------------------------------------
sys_clk_freq = core_config["sys_clk_freq"]
cpu_type = core_config["cpu"]
csr_expose = core_config.get("csr_expose", False)
csr_align = core_config.get("csr_align", 32)
if cpu_type is None:
kwargs["integrated_rom_size"] = 0
kwargs["integrated_sram_size"] = 0
kwargs["l2_size"] = 0
kwargs["min_l2_data_width"] = 0
kwargs["with_uart"] = False
kwargs["with_timer"] = False
kwargs["with_ctrl"] = False
kwargs["with_wishbone"] = False
else:
kwargs["l2_size"] = 0
kwargs["min_l2_data_width"] = 0
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(
self,
platform,
sys_clk_freq,
cpu_type=cpu_type,
csr_alignment=csr_align,
max_sdram_size=
0x01000000, # Only expose 16MB to the CPU, enough for Init/Calib.
**kwargs)
# CRG --------------------------------------------------------------------------------------
if core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
self.submodules.crg = crg = LiteDRAMECP5DDRPHYCRG(
platform, core_config)
if core_config["sdram_phy"] in [
litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY,
litedram_phys.V7DDRPHY
]:
self.submodules.crg = LiteDRAMS7DDRPHYCRG(platform, core_config)
# DRAM -------------------------------------------------------------------------------------
platform.add_extension(get_dram_ios(core_config))
if core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
assert core_config["memtype"] in ["DDR3"]
self.submodules.ddrphy = core_config["sdram_phy"](
pads=platform.request("ddram"), sys_clk_freq=sys_clk_freq)
self.comb += crg.stop.eq(self.ddrphy.init.stop)
sdram_module = core_config["sdram_module"](sys_clk_freq, "1:2")
if core_config["sdram_phy"] in [
litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY,
litedram_phys.V7DDRPHY
]:
assert core_config["memtype"] in ["DDR2", "DDR3"]
self.submodules.ddrphy = core_config["sdram_phy"](
pads=platform.request("ddram"),
memtype=core_config["memtype"],
nphases=4 if core_config["memtype"] == "DDR3" else 2,
sys_clk_freq=sys_clk_freq,
iodelay_clk_freq=core_config["iodelay_clk_freq"],
cmd_latency=core_config["cmd_latency"])
self.add_constant("CMD_DELAY", core_config["cmd_delay"])
if core_config["memtype"] == "DDR3":
self.ddrphy.settings.add_electrical_settings(
rtt_nom=core_config["rtt_nom"],
rtt_wr=core_config["rtt_wr"],
ron=core_config["ron"])
self.add_csr("ddrphy")
sdram_module = core_config["sdram_module"](
sys_clk_freq, "1:4" if core_config["memtype"] == "DDR3" else "1:2")
controller_settings = controller_settings = ControllerSettings(
cmd_buffer_depth=core_config["cmd_buffer_depth"])
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings,
controller_settings=controller_settings)
# DRAM Initialization ----------------------------------------------------------------------
self.submodules.ddrctrl = LiteDRAMCoreControl()
self.add_csr("ddrctrl")
self.comb += [
platform.request("init_done").eq(self.ddrctrl.init_done.storage),
platform.request("init_error").eq(self.ddrctrl.init_error.storage)
]
# CSR port ---------------------------------------------------------------------------------
if csr_expose:
csr_port = csr_bus.Interface(address_width=self.csr_address_width,
data_width=self.csr_data_width)
self.add_csr_master(csr_port)
platform.add_extension(
get_csr_ios(self.csr_address_width, self.csr_data_width))
_csr_port_io = platform.request("csr_port", 0)
self.comb += [
csr_port.adr.eq(_csr_port_io.adr),
csr_port.we.eq(_csr_port_io.we),
csr_port.dat_w.eq(_csr_port_io.dat_w),
_csr_port_io.dat_r.eq(csr_port.dat_r),
]
if self.cpu_type == None:
csr_base = core_config.get("csr_base", 0)
self.shadow_base = csr_base
# User ports -------------------------------------------------------------------------------
self.comb += [
platform.request("user_clk").eq(ClockSignal()),
platform.request("user_rst").eq(ResetSignal())
]
for name, port in core_config["user_ports"].items():
# Native -------------------------------------------------------------------------------
if port["type"] == "native":
user_port = self.sdram.crossbar.get_port()
platform.add_extension(
get_native_user_port_ios(name, user_port.address_width,
user_port.data_width))
_user_port_io = platform.request("user_port_{}".format(name))
self.comb += [
# cmd
user_port.cmd.valid.eq(_user_port_io.cmd_valid),
_user_port_io.cmd_ready.eq(user_port.cmd.ready),
user_port.cmd.we.eq(_user_port_io.cmd_we),
user_port.cmd.addr.eq(_user_port_io.cmd_addr),
# wdata
user_port.wdata.valid.eq(_user_port_io.wdata_valid),
_user_port_io.wdata_ready.eq(user_port.wdata.ready),
user_port.wdata.we.eq(_user_port_io.wdata_we),
user_port.wdata.data.eq(_user_port_io.wdata_data),
# rdata
_user_port_io.rdata_valid.eq(user_port.rdata.valid),
user_port.rdata.ready.eq(_user_port_io.rdata_ready),
_user_port_io.rdata_data.eq(user_port.rdata.data),
]
# Wishbone -----------------------------------------------------------------------------
elif port["type"] == "wishbone":
user_port = self.sdram.crossbar.get_port()
wb_port = wishbone.Interface(user_port.data_width,
user_port.address_width)
wishbone2native = LiteDRAMWishbone2Native(wb_port, user_port)
self.submodules += wishbone2native
platform.add_extension(
get_wishbone_user_port_ios(name, len(wb_port.adr),
len(wb_port.dat_w)))
_wb_port_io = platform.request("user_port_{}".format(name))
self.comb += [
wb_port.adr.eq(_wb_port_io.adr),
wb_port.dat_w.eq(_wb_port_io.dat_w),
_wb_port_io.dat_r.eq(wb_port.dat_r),
wb_port.sel.eq(_wb_port_io.sel),
wb_port.cyc.eq(_wb_port_io.cyc),
wb_port.stb.eq(_wb_port_io.stb),
_wb_port_io.ack.eq(wb_port.ack),
wb_port.we.eq(_wb_port_io.we),
_wb_port_io.err.eq(wb_port.err),
]
# AXI ----------------------------------------------------------------------------------
elif port["type"] == "axi":
user_port = self.sdram.crossbar.get_port()
axi_port = LiteDRAMAXIPort(
user_port.data_width, user_port.address_width +
log2_int(user_port.data_width // 8), port["id_width"])
axi2native = LiteDRAMAXI2Native(axi_port, user_port)
self.submodules += axi2native
platform.add_extension(
get_axi_user_port_ios(name, axi_port.address_width,
axi_port.data_width,
port["id_width"]))
_axi_port_io = platform.request("user_port_{}".format(name))
self.comb += [
# aw
axi_port.aw.valid.eq(_axi_port_io.awvalid),
_axi_port_io.awready.eq(axi_port.aw.ready),
axi_port.aw.addr.eq(_axi_port_io.awaddr),
axi_port.aw.burst.eq(_axi_port_io.awburst),
axi_port.aw.len.eq(_axi_port_io.awlen),
axi_port.aw.size.eq(_axi_port_io.awsize),
axi_port.aw.id.eq(_axi_port_io.awid),
# w
axi_port.w.valid.eq(_axi_port_io.wvalid),
_axi_port_io.wready.eq(axi_port.w.ready),
axi_port.w.last.eq(_axi_port_io.wlast),
axi_port.w.strb.eq(_axi_port_io.wstrb),
axi_port.w.data.eq(_axi_port_io.wdata),
# b
_axi_port_io.bvalid.eq(axi_port.b.valid),
axi_port.b.ready.eq(_axi_port_io.bready),
_axi_port_io.bresp.eq(axi_port.b.resp),
_axi_port_io.bid.eq(axi_port.b.id),
# ar
axi_port.ar.valid.eq(_axi_port_io.arvalid),
_axi_port_io.arready.eq(axi_port.ar.ready),
axi_port.ar.addr.eq(_axi_port_io.araddr),
axi_port.ar.burst.eq(_axi_port_io.arburst),
axi_port.ar.len.eq(_axi_port_io.arlen),
axi_port.ar.size.eq(_axi_port_io.arsize),
axi_port.ar.id.eq(_axi_port_io.arid),
# r
_axi_port_io.rvalid.eq(axi_port.r.valid),
axi_port.r.ready.eq(_axi_port_io.rready),
_axi_port_io.rlast.eq(axi_port.r.last),
_axi_port_io.rresp.eq(axi_port.r.resp),
_axi_port_io.rdata.eq(axi_port.r.data),
_axi_port_io.rid.eq(axi_port.r.id),
]
# FIFO ---------------------------------------------------------------------------------
elif port["type"] == "fifo":
platform.add_extension(
get_fifo_user_port_ios(name, user_port.data_width))
_user_fifo_io = platform.request("user_fifo_{}".format(name))
fifo = LiteDRAMFIFO(
data_width=user_port.data_width,
base=port["base"],
depth=port["depth"],
write_port=self.sdram.crossbar.get_port("write"),
write_threshold=port["depth"] - 32, # FIXME
read_port=self.sdram.crossbar.get_port("read"),
read_threshold=32 # FIXME
)
self.submodules += fifo
self.comb += [
# in
fifo.sink.valid.eq(_user_fifo_io.in_valid),
_user_fifo_io.in_ready.eq(fifo.sink.ready),
fifo.sink.data.eq(_user_fifo_io.in_data),
# out
_user_fifo_io.out_valid.eq(fifo.source.valid),
fifo.source.ready.eq(_user_fifo_io.out_ready),
_user_fifo_io.out_data.eq(fifo.source.data),
]
else:
raise ValueError("Unsupported port type: {}".format(
port["type"]))
def __init__(self,
variant="minimal",
with_sampler=False,
with_analyzer=False,
host_ip="192.168.1.100",
host_udp_port=2000):
platform = arty.Platform()
# BenchSoC ---------------------------------------------------------------------------------
bench_kwargs = {
"minimal": dict(cpu_variant="minimal",
integrated_main_ram_size=0x1000),
"standard": dict(),
}[variant]
BaseSoC.__init__(self,
sys_clk_freq=int(100e6),
integrated_rom_size=0x10000,
integrated_rom_mode="rw",
**bench_kwargs)
# SDCard on PMODD with Digilent's Pmod MicroSD ---------------------------------------------
self.platform.add_extension(arty._sdcard_pmod_io)
self.add_sdcard("sdcard")
if with_sampler or with_analyzer:
# Etherbone ----------------------------------------------------------------------------
from liteeth.phy.mii import LiteEthPHYMII
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy)
if with_sampler:
# PMODB Sampler (connected to PmodTPH2 with Pmode Cable Kit) ---------------------------
_la_pmod_ios = [("la_pmod", 0,
Pins("pmoda:0 pmoda:1 pmoda:2 pmoda:3",
"pmoda:4 pmoda:5 pmoda:6 pmoda:7"),
IOStandard("LVCMOS33"))]
self.platform.add_extension(_la_pmod_ios)
self.submodules.sampler = Sampler(self.platform.request("la_pmod"))
self.add_csr("sampler")
# DRAMFIFO -----------------------------------------------------------------------------
from litedram.frontend.fifo import LiteDRAMFIFO
self.submodules.fifo = LiteDRAMFIFO(
data_width=8,
base=0x00000000,
depth=0x01000000, # 16MB
write_port=self.sdram.crossbar.get_port(mode="write",
data_width=8),
read_port=self.sdram.crossbar.get_port(mode="read",
data_width=8),
)
# UDPStreamer --------------------------------------------------------------------------
from liteeth.common import convert_ip
from liteeth.frontend.stream import LiteEthStream2UDPTX
udp_port = self.ethcore.udp.crossbar.get_port(host_udp_port, dw=8)
udp_streamer = LiteEthStream2UDPTX(ip_address=convert_ip(host_ip),
udp_port=host_udp_port,
fifo_depth=1024)
udp_streamer = ClockDomainsRenamer("eth_tx")(udp_streamer)
self.submodules += udp_streamer
udp_cdc = stream.ClockDomainCrossing([("data", 8)], "sys",
"eth_tx")
self.submodules += udp_cdc
# Sampler/FIFO/UDPStreamer flow -------------------------------------------------------------
self.comb += self.sampler.source.connect(self.fifo.sink)
self.comb += self.fifo.source.connect(udp_cdc.sink)
self.comb += udp_cdc.source.connect(udp_streamer.sink)
self.comb += udp_streamer.source.connect(udp_port.sink)
if with_analyzer:
from litescope import LiteScopeAnalyzer
analyzer_signals = [
self.sdphy.sdpads,
self.sdphy.cmdw.sink,
self.sdphy.cmdr.sink,
self.sdphy.cmdr.source,
self.sdphy.dataw.sink,
self.sdphy.dataw.stop,
self.sdphy.dataw.crc.source,
self.sdphy.dataw.status.status,
self.sdphy.datar.sink,
self.sdphy.datar.source,
self.sdphy.clocker.ce,
self.sdphy.clocker.stop,
]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals,
depth=2048,
clock_domain="sys",
csr_csv="analyzer.csv")
self.add_csr("analyzer")
def __init__(self, platform, with_hdmi_in=False):
sys_clk_freq = int(81e6)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=0x8000)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_constant("ECP5DDRPHY", None)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
sdram_module = MT41K64M16(sys_clk_freq, "1:2")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
# HDMI In ----------------------------------------------------------------------------------
if with_hdmi_in:
from litedram.frontend.fifo import LiteDRAMFIFO
hdmi_layout = [("de", 1), ("hsync", 1), ("vsync", 1), ("r", 8),
("g", 8), ("b", 8)]
hdmi_pads = platform.request("hdmi_in")
self.clock_domains.cd_hdmi = ClockDomain()
self.comb += self.cd_hdmi.clk.eq(hdmi_pads.pclk)
# FIXME: Check hdmi_clk freq vs sys_clk freq
cdc = stream.AsyncFIFO(hdmi_layout, 4)
cdc = ClockDomainsRenamer({"write": "hdmi", "read": "sys"})(cdc)
converter = stream.Converter(32, 128)
self.submodules += cdc, converter
fifo_base = 0x00100000 # FIXME: Add control
fifo_depth = 0x00100000 # FIXME: Add control
fifo = LiteDRAMFIFO(
data_width=128,
base=fifo_base,
depth=fifo_depth,
write_port=self.sdram.crossbar.get_port(mode="write"),
write_threshold=fifo_depth - 32,
read_port=self.sdram.crossbar.get_port(mode="read"),
read_threshold=32)
self.submodules += fifo
self.sync.hdmi += [
cdc.sink.valid.eq(1), # FIXME: Add control
cdc.sink.de.eq(hdmi_pads.de),
cdc.sink.hsync.eq(hdmi_pads.hsync),
cdc.sink.vsync.eq(hdmi_pads.vsync),
cdc.sink.r.eq(hdmi_pads.r),
cdc.sink.g.eq(hdmi_pads.g),
cdc.sink.b.eq(hdmi_pads.b),
]
self.comb += cdc.source.connect(converter.sink,
keep={"valid", "ready"})
self.comb += converter.sink.data.eq(cdc.source.payload.raw_bits())
self.comb += converter.source.connect(fifo.sink)
self.comb += fifo.source.ready.eq(
1) # FIXME: to FX3, always ready for now
def __init__(self, ddr_wr_port, ddr_rd_port, udp_port):
SIZE = 1024 * 1024
SIZE = 1024
self.fifo_full = CSRStatus(reset=0)
self.fifo_error = CSRStatus(reset=0)
self.fifo_load = CSRStorage(
reset=0) # Load the coefficients in memory to the ROI Summer
self.fifo_read = CSRStorage(reset=0)
self.fifo_size = CSRStorage(32, reset=SIZE)
self.dst_ip = CSRStorage(32, reset=convert_ip("192.168.1.114"))
self.dst_port = CSRStorage(16, reset=7778)
dw = 64
print(
f"Write port: A ({ddr_wr_port.address_width})/ D ({ddr_wr_port.data_width})"
)
print(
f"Read port: A ({ddr_rd_port.address_width})/ D ({ddr_rd_port.data_width})"
)
self.submodules.dram_fifo = dram_fifo = LiteDRAMFIFO(
data_width=dw,
base=0,
depth=SIZE,
write_port=ddr_wr_port,
read_port=ddr_rd_port,
with_bypass=True,
)
# self.mf = mf = Signal(reset=0) # mf == More Fragments
# self.fragment_offset = fragment_offset = Signal(13, reset=0)
# self.identification = identification = Signal(16, reset=0)
self.submodules.adcs = adcs = ADCStream(1, dw)
self.fifo_counter = fifo_counter = Signal(24)
self.load_fifo = load_fifo = Signal()
# adc --> buffer_fifo
self.submodules.buffer_fifo = buffer_fifo = stream.SyncFIFO(
stream.EndpointDescription([("data", dw)]), 256, buffered=True)
# buffer_fifo --> dram_fifo
fifo_size = Signal(32)
self.sync += [
fifo_size.eq(self.fifo_size.storage),
If(self.fifo_load.re & self.fifo_load.storage, fifo_counter.eq(0),
load_fifo.eq(1)),
If(load_fifo & adcs.source.valid, self.fifo_full.status.eq(0),
self.fifo_error.status.eq(~dram_fifo.dram_fifo.ctrl.writable),
fifo_counter.eq(fifo_counter + 1)),
If((fifo_counter == fifo_size - 1) & adcs.source.valid,
load_fifo.eq(0), self.fifo_full.status.eq(1)),
]
self.comb += [
buffer_fifo.sink.data.eq(adcs.source.data),
buffer_fifo.sink.valid.eq(adcs.source.valid & load_fifo),
buffer_fifo.source.connect(dram_fifo.sink),
]
# fifo --> stride converter
self.submodules.stride_converter = sc = stream.Converter(
dw, udp_port.dw)
self.read_from_dram_fifo = read_from_dram_fifo = Signal()
self.comb += [dram_fifo.source.connect(sc.sink)]
self.receive_count = receive_count = Signal(24)
self.sync += [
If(dram_fifo.source.valid & dram_fifo.source.ready,
receive_count.eq(receive_count + 1)).Elif(
read_from_dram_fifo == 0, receive_count.eq(0))
]
# --> udp fragmenter -->
self.submodules.udp_fragmenter = udp_fragmenter = UDPFragmenter(
udp_port.dw)
self.sync += read_from_dram_fifo.eq(self.fifo_read.storage)
self.comb += If(
read_from_dram_fifo,
# TODO: There is a bug somewhere in the converter,
# its source.last somehow gets set, no idea why. That signal is of no real use
# for the fragmenter anyways, so we live without it
sc.source.connect(udp_fragmenter.sink, omit={'total_size',
'last'}))
# TODO: 8 should be adcstream data width // 8
self.comb += udp_fragmenter.sink.length.eq(fifo_size << log2_int(dw //
8))
self.comb += udp_fragmenter.source.connect(udp_port.sink)
self.comb += [
# param
udp_port.sink.src_port.eq(4321),
udp_port.sink.dst_port.eq(self.dst_port.storage),
udp_port.sink.ip_address.eq(self.dst_ip.storage),
# udp_port.sink.ip_address.eq(convert_ip("192.168.88.101")),
# payload
udp_port.sink.error.eq(0)
]
# debug
self.first_sample, self.last_sample = Signal(16), Signal(16)
self.sync += [
If(fifo_counter == 1, self.first_sample.eq(adcs.source.data[:16])),
If(fifo_counter == SIZE - 2,
self.last_sample.eq(adcs.source.data[:16])),
]
def __init__(self, ddr_wr_port, ddr_rd_port, udp_port, adc_source, adc_dw):
SIZE = 1024 * 1024
self.fifo_full = CSRStatus(reset=0)
self.fifo_error = CSRStatus(reset=0)
self.fifo_load = CSRStorage(reset=0)
self.fifo_read = CSRStorage(reset=0)
self.fifo_size = CSRStorage(32, reset=SIZE)
self.dst_ip = CSRStorage(32, reset=convert_ip("192.168.1.114"))
self.dst_port = CSRStorage(16, reset=7778)
self.fifo_counter = fifo_counter = Signal(24)
self.load_fifo = load_fifo = Signal()
dw = ddr_wr_port.data_width
print(
f"Write port: A ({ddr_wr_port.address_width})/ D ({ddr_wr_port.data_width})"
)
print(
f"Read port: A ({ddr_rd_port.address_width})/ D ({ddr_rd_port.data_width})"
)
print(f"dw: {dw}; adc_dw: {adc_dw}")
self.submodules.dram_fifo = dram_fifo = LiteDRAMFIFO(
data_width=dw,
base=0,
depth=SIZE * (dw // 8), # liteDRAM expects this in bytes
write_port=ddr_wr_port,
read_port=ddr_rd_port,
)
self.adc_data = adc_data = Signal(dw)
DW_RATIO = dw // adc_dw
log_dw_ratio = log2_int(DW_RATIO)
word_count = Signal(log_dw_ratio)
word_count_d = Signal(log_dw_ratio)
self.sync += [
If(adc_source.valid,
adc_data.eq(Cat(adc_data[adc_dw:], adc_source.data)),
word_count.eq(word_count + 1)),
word_count_d.eq(word_count),
]
self.comb += [
dram_fifo.sink.valid.eq((word_count == 0) & (word_count_d != 0)
& load_fifo),
dram_fifo.sink.data.eq(adc_data)
]
fifo_size = Signal(32)
self.sync += [
fifo_size.eq(self.fifo_size.storage),
If(self.fifo_load.re & self.fifo_load.storage, fifo_counter.eq(0),
load_fifo.eq(1)),
If(load_fifo & adc_source.valid, self.fifo_full.status.eq(0),
self.fifo_error.status.eq(~dram_fifo.dram_fifo.ctrl.writable),
fifo_counter.eq(fifo_counter + 1)),
If((fifo_counter == fifo_size - 1) & adc_source.valid,
load_fifo.eq(0), self.fifo_full.status.eq(1)),
]
# fifo --> stride converter
self.submodules.stride_converter = sc = stream.Converter(
dw, udp_port.dw)
self.read_from_dram_fifo = read_from_dram_fifo = Signal()
self.comb += [dram_fifo.source.connect(sc.sink)]
self.receive_count = receive_count = Signal(24)
self.sync += [
If(dram_fifo.source.valid & dram_fifo.source.ready,
receive_count.eq(receive_count + 1)).Elif(
read_from_dram_fifo == 0, receive_count.eq(0))
]
# --> udp fragmenter -->
self.submodules.udp_fragmenter = udp_fragmenter = UDPFragmenter(
udp_port.dw)
self.sync += read_from_dram_fifo.eq(self.fifo_read.storage)
self.comb += If(
read_from_dram_fifo,
# TODO: There is a bug somewhere in the converter,
# its source.last somehow gets set, no idea why. That signal is of no real use
# for the fragmenter anyways, so we live without it
sc.source.connect(udp_fragmenter.sink, omit={'total_size',
'last'}))
# TODO: 8 should be adcstream data width // 8
self.comb += udp_fragmenter.sink.length.eq(
fifo_size << log2_int(adc_dw // 8))
self.comb += udp_fragmenter.source.connect(udp_port.sink)
self.comb += [
# param
udp_port.sink.src_port.eq(4321),
udp_port.sink.dst_port.eq(self.dst_port.storage),
udp_port.sink.ip_address.eq(self.dst_ip.storage),
# udp_port.sink.ip_address.eq(convert_ip("192.168.88.101")),
# payload
udp_port.sink.error.eq(0)
]