def __init__(self, platform, *args, **kwargs): # Need a larger integrated ROM on or1k to fit the BIOS with TFTP support. if 'integrated_rom_size' not in kwargs and kwargs.get( 'cpu_type', 'lm32') != 'lm32': kwargs['integrated_rom_size'] = 0x10000 BaseSoC.__init__(self, platform, *args, **kwargs) # Ethernet --------------------------------------------------------------------------------- # Ethernet Phy self.submodules.ethphy = LiteEthPHY( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") # Ethernet Core etherbone_mac_address = 0x10e2d5000000 etherbone_ip_address = "192.168.100.50" self.submodules.ethcore = LiteEthUDPIPCore( phy=self.ethphy, mac_address=etherbone_mac_address, ip_address=etherbone_ip_address, clk_freq=self.clk_freq) # Etherbone Core self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234) self.add_wb_master(self.etherbone.wishbone.bus) # timing constraints self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9 / 25e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9 / 25e6) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, platform, eth_phy=0, mac_address=0x10e2d5000000, ip_address="192.168.1.50"): sys_clk_freq = int(133e6) SoCCore.__init__(self, platform, sys_clk_freq, cpu_type=None, with_uart=False) # crg self.submodules.crg = crg = _CRG(platform, sys_clk_freq) # 1gbps ethernet ethphy = LiteEthPHYRGMII(platform.request("eth_clocks", eth_phy), platform.request("eth", eth_phy)) ethcore = LiteEthUDPIPCore(ethphy, mac_address, convert_ip(ip_address), sys_clk_freq) self.submodules += ethphy, ethcore ethphy.crg.cd_eth_rx.clk.attr.add("keep") platform.add_period_constraint(ethphy.crg.cd_eth_rx.clk, period_ns(125e6)) platform.add_false_path_constraints(crg.cd_sys.clk, ethphy.crg.cd_eth_rx.clk) # led blink led_counter = Signal(32) self.sync += led_counter.eq(led_counter + 1) self.comb += platform.request("user_led").eq(led_counter[26])
def __init__(self, dw=8): self.dw = dw self.submodules.phy_model = phy.PHY(8, debug=False) self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=False) self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False) self.submodules.ip_model = ip.IP(self.mac_model, mac_address, ip_address, debug=False, loopback=False) self.submodules.udp_model = udp.UDP(self.ip_model, ip_address, debug=False, loopback=True) self.submodules.core = LiteEthUDPIPCore(self.phy_model, mac_address, ip_address, 100000) udp_port = self.core.udp.crossbar.get_port(0x5678, dw) self.submodules.streamer = PacketStreamer(eth_udp_user_description(dw)) self.submodules.logger = PacketLogger(eth_udp_user_description(dw)) self.comb += [ Record.connect(self.streamer.source, udp_port.sink), udp_port.sink.ip_address.eq(0x12345678), udp_port.sink.src_port.eq(0x1234), udp_port.sink.dst_port.eq(0x5678), udp_port.sink.length.eq(64 // (dw // 8)), Record.connect(udp_port.source, self.logger.sink) ]
def __init__(self, platform, mac_address=0x10e2d5000000, ip_address="192.168.1.50"): BaseSoC.__init__(self, platform, cpu_type=None, csr_data_width=32, l2_size=32) # ethernet mac/udp/ip stack self.submodules.ethphy = LiteEthPHYMII(self.platform.request("eth_clocks"), self.platform.request("eth")) self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy, mac_address, convert_ip(ip_address), self.clk_freq, with_icmp=True) # etherbone bridge self.add_cpu_or_bridge(LiteEthEtherbone(self.ethcore.udp, 1234)) self.add_wb_master(self.cpu_or_bridge.wishbone.bus) self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, period_ns(25e6)) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, period_ns(25e6)) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self): self.submodules.phy_model = phy.PHY(8, debug=False) self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=False) self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False) self.submodules.ip_model = ip.IP(self.mac_model, mac_address, ip_address, debug=False, loopback=False) self.submodules.udp_model = udp.UDP(self.ip_model, ip_address, debug=False, loopback=False) self.submodules.etherbone_model = etherbone.Etherbone(self.udp_model, debug=False) self.submodules.core = LiteEthUDPIPCore(self.phy_model, mac_address, ip_address, 100000) self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 0x1234) self.submodules.sram = wishbone.SRAM(1024) self.submodules.interconnect = wishbone.InterconnectPointToPoint( self.etherbone.wishbone.bus, self.sram.bus)
def __init__(self, eth_phy=0, **kwargs): BaseSoC.__init__(self, **kwargs) # Ethernet --------------------------------------------------------------------------------- # phy self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks", eth_phy), pads=self.platform.request("eth", eth_phy), tx_delay=0e-9, # 0ns FPGA delay (Clk delay added by PHY) rx_delay=2e-9 ) # 2ns FPGA delay to compensate Clk routing to IDDRX1F self.add_csr("ethphy") # core self.submodules.ethcore = LiteEthUDPIPCore(phy=self.ethphy, mac_address=0x10e2d5000000, ip_address="192.168.1.50", clk_freq=self.clk_freq) # etherbone self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234) self.add_wb_master(self.etherbone.wishbone.bus) # timing constraints self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9 / 125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9 / 125e6) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, **kwargs): BaseSoc.__init__(self, **kwargs) # ethernet PHY and UDP/IP stack mac_address = 0x10e2d5001000 ip_address = "192.168.1.50" self.submodules.ethphy = LiteEthPHY( self.platform.request("eth_clocks"), self.platform.request("eth"), self.clk_freq, # avoid huge reset delay in simulation with_hw_init_reset="synth" in argv) self.submodules.core = LiteEthUDPIPCore(self.ethphy, mac_address, convert_ip(ip_address), self.clk_freq) # MAC = wishbone slave = to let the CPU talk over ethernet # self.submodules.ethmac = LiteEthMAC( # phy=self.ethphy, dw=32, interface="wishbone", # endianness="little", with_preamble_crc=False # ) # self.add_wb_slave( # mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus # ) # self.add_memory_region( # "ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000 # ) # Etherbone = wishbone master = read and write registers remotely self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 1234, mode="master") self.add_wb_master(self.etherbone.wishbone.bus)
def __init__(self, **kwargs): BaseSoC.__init__(self, **kwargs) # Ethernet --------------------------------------------------------------------------------- # phy self.submodules.ethphy = LiteEthPHYMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") # core self.submodules.ethcore = LiteEthUDPIPCore(phy=self.ethphy, mac_address=0x10e2d5000000, ip_address="192.168.1.50", clk_freq=self.clk_freq) # etherbone self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234) self.add_wb_master(self.etherbone.wishbone.bus) # timing constraints self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9 / 25e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9 / 25e6) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, platform, mac_address=0x10e2d5000000, ip_address="192.168.1.50"): BaseSoC.__init__(self, platform, cpu_type=None, csr_data_width=32) # Ethernet PHY and UDP/IP stack self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"), self.platform.request("eth")) self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy, mac_address, convert_ip(ip_address), self.clk_freq, with_icmp=True) # Etherbone bridge self.add_cpu_or_bridge(LiteEthEtherbone(self.ethcore.udp, 20000)) self.add_wb_master(self.cpu_or_bridge.master.bus) self.specials += [ Keep(self.ethphy.crg.cd_eth_rx.clk), Keep(self.ethphy.crg.cd_eth_tx.clk) ] self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, eth_port=0, toolchain="diamond"): platform = versa_ecp5.Platform(toolchain=toolchain) sys_clk_freq = int(133e6) SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, cpu_type=None, with_uart=False, csr_data_width=32, ident="Versa ECP5 test SoC", ident_version=True) # crg self.submodules.crg = RGMIITestCRG(platform, sys_clk_freq) # ethernet mac/udp/ip stack ethphy = LiteEthPHYRGMII(platform.request("eth_clocks", eth_port), platform.request("eth", eth_port)) ethcore = LiteEthUDPIPCore(ethphy, mac_address=0x10e2d5000000, ip_address=convert_ip("192.168.1.50"), clk_freq=sys_clk_freq, with_icmp=True) self.submodules += ethphy, ethcore ethphy.crg.cd_eth_rx.clk.attr.add("keep") ethphy.crg.cd_eth_tx.clk.attr.add("keep") platform.add_period_constraint(ethphy.crg.cd_eth_rx.clk, 1e9 / 125e6) platform.add_period_constraint(ethphy.crg.cd_eth_tx.clk, 1e9 / 125e6) # led blinking led_counter = Signal(32) self.sync += led_counter.eq(led_counter + 1) self.comb += platform.request("user_led", 0).eq(led_counter[26])
def __init__(self, platform, eth_phy=0, mac_address=0x10e2d5000000, ip_address="192.168.1.50"): sys_clk_freq = int(133e6) # SoCMini ---------------------------------------------------------------------------------- SoCMini.__init__(self, platform, sys_clk_freq) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = crg = _CRG(platform, sys_clk_freq) # 1 Gbps Ethernet -------------------------------------------------------------------------- # phy ethphy = LiteEthPHYRGMII( clock_pads = platform.request("eth_clocks", eth_phy), pads = platform.request("eth", eth_phy)) # core ethcore = LiteEthUDPIPCore( phy = ethphy, mac_address = mac_address, ip_address = ip_address, clk_freq = sys_clk_freq) self.submodules += ethphy, ethcore # timing constraints platform.add_period_constraint(ethphy.crg.cd_eth_rx.clk, 1e9/125e6) platform.add_false_path_constraints(crg.cd_sys.clk, ethphy.crg.cd_eth_rx.clk) # Led -------------------------------------------------------------------------------------- counter = Signal(32) self.sync += counter.eq(counter + 1) self.comb += platform.request("user_led_n").eq(counter[26])
def __init__(self): ''' for testing on the berkeleylab_marble target. Ping-able. ''' BaseSoC.__init__( self, cpu_type=None, # f_sys must be >= 156.25 MHz sys_clk_freq=int(166.67e6), integrated_main_ram_size=8, integrated_sram_size=0, with_timer=False, with_etherbone=False, uart_name='uartbone', uart_baudrate=1152000 # not a typo ) self.submodules.ethphy = Phy10G( self.platform, self.platform.request("qsfp", 1), self.platform.request("clkmgt", 1), # SI570_CLK self.sys_clk_freq) self.ethphy.add_csr() # TODO this overrides the constraint from the IP file and causes a # critical warning. But without it Vivado fails to apply the false_path # constraint below. # https://support.xilinx.com/s/article/55248?language=en_US self.platform.add_period_constraint(self.ethphy.coreclk_out, 1e9 / 156.25e6) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.coreclk_out) my_ip = "192.168.10.50" my_mac = 0x10e2d5000000 # ---------------------- # UDP stack # ---------------------- ethcore = LiteEthUDPIPCore(phy=self.ethphy, mac_address=my_mac, ip_address=my_ip, clk_freq=self.clk_freq, dw=self.ethphy.dw) self.submodules.ethcore = ethcore # ---------------------- # UDP packet sender # ---------------------- D = 8 # Datapath width [bytes] self.udpp = self.ethcore.udp.crossbar.get_port(1337, D * 8) self.submodules.udp_sender = UdpSender(D=D, dst_ip="192.168.10.1") self.comb += [ self.udp_sender.source.connect(self.udpp.sink), self.udpp.source.ready.eq(1) ]
def __init__(self): self.platform = platform = FireSensePlatform() sys_clk_freq = int(125e6) SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, cpu_type="picorv32", with_uart=True, csr_data_width=32, ident="Versa ECP5 test SoC", ident_version=True) # crg self.submodules.crg = _CRG(platform, sys_clk_freq) # ethernet mac/udp/ip stack ethphy = LiteEthPHYRGMII(platform.request("eth_clocks"), platform.request("eth")) ethcore = LiteEthUDPIPCore(ethphy, mac_address=0x10e2d5000000, ip_address=convert_ip("192.168.1.50"), clk_freq=sys_clk_freq, with_icmp=True) self.submodules += ethphy, ethcore ethphy.crg.cd_eth_rx.clk.attr.add("keep") ethphy.crg.cd_eth_tx.clk.attr.add("keep") platform.add_period_constraint(ethphy.crg.cd_eth_rx.clk, period_ns(125e6)) platform.add_period_constraint(ethphy.crg.cd_eth_tx.clk, period_ns(125e6)) # led blinking #led_counter = Signal(32) #self.sync += led_counter.eq(led_counter + 1) #self.comb += platform.request("user_led", 0).eq(led_counter[0]) cam = DummyCamera() #cam = FlirTau2(platform) self.submodules += cam ethTTY = LiteEthTTY(ethcore.udp, convert_ip("192.168.1.100"), 9000, tx_fifo_depth=2 * 1024) self.submodules += ethTTY self.comb += cam.source.connect(ethTTY.sink) # led blinking led_counter = Signal(32) self.sync += led_counter.eq(led_counter + 1) self.comb += platform.request("user_led", 0).eq(led_counter[26])
def __init__(self, platform, clk_freq=int(166e6), mac_address=0x10e2d5000000, ip_address="192.168.1.50"): sys_clk_freq = int((1 / (platform.default_clk_period)) * 1e9) SoCCore.__init__(self, platform, clk_freq, cpu_type=None, csr_data_width=32, with_uart=False, ident="LiteEth Base Design", with_timer=False) # Serial Wishbone Bridge serial_bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq, baudrate=115200) self.submodules += serial_bridge self.add_wb_master(serial_bridge.wishbone) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) # Wishbone SRAM (to test Wishbone over UART and Etherbone) self.submodules.sram = wishbone.SRAM(1024) self.add_wb_slave(lambda a: a[23:25] == 1, self.sram.bus) # Ethernet PHY and UDP/IP stack self.submodules.ethphy = ethphy = LiteEthPHY( clock_pads=platform.request("eth_clocks"), pads=platform.request("eth"), clk_freq=clk_freq) self.add_csr("ethphy") self.submodules.ethcore = ethcore = LiteEthUDPIPCore( phy=ethphy, mac_address=mac_address, ip_address=ip_address, clk_freq=clk_freq) self.add_csr("ethcore") if isinstance(platform.toolchain, XilinxVivadoToolchain): self.crg.cd_sys.clk.attr.add("keep") ethphy.crg.cd_eth_rx.clk.attr.add("keep") ethphy.crg.cd_eth_tx.clk.attr.add("keep") platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9 / 125e6) platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9 / 125e6) platform.add_false_path_constraints(self.crg.cd_sys.clk, ethphy.crg.cd_eth_rx.clk, ethphy.crg.cd_eth_tx.clk)
def __init__(self, platform, cpu_type=None, mac_address=0x10e2d5000000, ip_address="192.168.100.50", **kwargs): clk_freq = int(142e6) SoCCore.__init__(self, platform, clk_freq, cpu_type=None, integrated_main_ram_size=0x8000, integrated_rom_size=0x10000, integrated_sram_size=0x8000, csr_data_width=32, with_uart=False, **kwargs) self.submodules.crg = CRG(platform) self.crg.cd_sys.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(clk_freq)) # ethernet mac/udp/ip stack self.submodules.ethphy = LiteEthPHYRGMII( self.platform.request("eth_clocks"), self.platform.request("eth")) self.add_csr("ethphy") self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy, mac_address, convert_ip(ip_address), self.clk_freq, with_icmp=True) self.add_csr("ethcore") # etherbone bridge self.add_cpu_or_bridge(LiteEthEtherbone(self.ethcore.udp, 1234)) self.add_wb_master(self.cpu_or_bridge.wishbone.bus) self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, period_ns(125e6)) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, period_ns(125e6)) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, platform, with_ethernet=True, mac_address=0x10e2d5000000, ip_address="192.168.1.50"): clk_freq = int(133e6) SoCCore.__init__(self, platform, clk_freq, cpu_type=None, csr_data_width=32, with_uart=False, ident="Daisho USB3.0 Test Design", with_timer=False) self.submodules.crg = _CRG(platform) # uart <--> wishbone self.add_cpu_or_bridge( UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)) self.add_wb_master(self.cpu_or_bridge.wishbone) self.crg.cd_sys.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, 7.5) # ethernet PHY and UDP/IP stack if with_ethernet: self.submodules.eth_phy = LiteEthPHYRGMII( self.platform.request("eth_clocks"), self.platform.request("eth")) self.submodules.eth_core = LiteEthUDPIPCore( self.eth_phy, mac_address, convert_ip(ip_address), clk_freq) # ethernet <--> wishbone self.submodules.etherbone = LiteEthEtherbone( self.eth_core.udp, 1234) self.add_wb_master(self.etherbone.wishbone.bus) # timing constraints self.eth_phy.crg.cd_eth_rx.clk.attr.add("keep") self.eth_phy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_rx.clk, 8.0) self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_tx.clk, 8.0) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.eth_phy.crg.cd_eth_rx.clk, self.eth_phy.crg.cd_eth_tx.clk)
def __init__(self, platform, clk_freq=166 * 1000000, mac_address=0x10e2d5000000, ip_address="192.168.1.50"): clk_freq = int((1 / (platform.default_clk_period)) * 1000000000) SoCCore.__init__(self, platform, clk_freq, cpu_type=None, csr_data_width=32, with_uart=False, ident="LiteEth Base Design", with_timer=False) self.add_cpu_or_bridge( UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)) self.add_wb_master(self.cpu_or_bridge.wishbone) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) # wishbone SRAM (to test Wishbone over UART and Etherbone) self.submodules.sram = wishbone.SRAM(1024) self.add_wb_slave(lambda a: a[23:25] == 1, self.sram.bus) # ethernet PHY and UDP/IP stack self.submodules.phy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"), clk_freq=clk_freq) self.submodules.core = LiteEthUDPIPCore(self.phy, mac_address, convert_ip(ip_address), clk_freq) if isinstance(platform.toolchain, XilinxVivadoToolchain): self.specials += [ Keep(self.crg.cd_sys.clk), Keep(self.phy.crg.cd_eth_rx.clk), Keep(self.phy.crg.cd_eth_tx.clk) ] platform.add_platform_command(""" create_clock -name sys_clk -period 6.0 [get_nets sys_clk] create_clock -name eth_rx_clk -period 8.0 [get_nets eth_rx_clk] create_clock -name eth_tx_clk -period 8.0 [get_nets eth_tx_clk] set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_rx_clk] set_false_path -from [get_clocks eth_rx_clk] -to [get_clocks sys_clk] set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_tx_clk] set_false_path -from [get_clocks eth_tx_clk] -to [get_clocks sys_clk] """)
def __init__(self, platform, mac_address=0x10e2d5000004, ip_address="10.0.11.2"): BaseSoC.__init__(self, platform, cpu_type="vexriscv", cpu_variant="debug", csr_data_width=8, l2_size=32) # ethernet mac/udp/ip stack self.submodules.ethphy = LiteEthPHYMII( self.platform.request("eth_clocks"), self.platform.request("eth")) self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy, mac_address, convert_ip(ip_address), self.clk_freq, with_icmp=True) # vexriscv debugging, at offset 0xf00f0000 self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu_or_bridge.debug_bus, 0x10) # Hook Etherbone up to the Wishbone bus, providing Wishbone over Ethernet. etherbone_cd = ClockDomain("etherbone") self.clock_domains += etherbone_cd self.comb += [ etherbone_cd.clk.eq(ClockSignal("sys")), etherbone_cd.rst.eq(ResetSignal("sys")) ] self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234, mode="master", cd="etherbone") self.add_wb_master(self.etherbone.wishbone.bus) self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, period_ns(25e6)) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, period_ns(25e6)) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, platform, core_config): # PHY -------------------------------------------------------------------------------------- PHYCore.__init__(self, platform, core_config) # Core ------------------------------------------------------------------------------------- self.submodules.core = LiteEthUDPIPCore(self.ethphy, mac_address = core_config["mac_address"], ip_address = core_config["ip_address"], clk_freq = core_config["clk_freq"]) # UDP -------------------------------------------------------------------------------------- udp_port = self.core.udp.crossbar.get_port(core_config["port"], 8) # XXX avoid manual connect udp_sink = self.platform.request("udp_sink") self.comb += [ # Control udp_port.sink.valid.eq(udp_sink.valid), udp_port.sink.last.eq(udp_sink.last), udp_sink.ready.eq(udp_port.sink.ready), # Param udp_port.sink.src_port.eq(udp_sink.src_port), udp_port.sink.dst_port.eq(udp_sink.dst_port), udp_port.sink.ip_address.eq(udp_sink.ip_address), udp_port.sink.length.eq(udp_sink.length), # Payload udp_port.sink.data.eq(udp_sink.data), udp_port.sink.error.eq(udp_sink.error) ] udp_source = self.platform.request("udp_source") self.comb += [ # Control udp_source.valid.eq(udp_port.source.valid), udp_source.last.eq(udp_port.source.last), udp_port.source.ready.eq(udp_source.ready), # Param udp_source.src_port.eq(udp_port.source.src_port), udp_source.dst_port.eq(udp_port.source.dst_port), udp_source.ip_address.eq(udp_port.source.ip_address), udp_source.length.eq(udp_port.source.length), # Payload udp_source.data.eq(udp_port.source.data), udp_source.error.eq(udp_port.source.error) ]
def __init__(self, **kwargs): super().__init__(**kwargs) ip = "192.168.19.70" print(f"setting to {ip}") self.submodules.udp_core = LiteEthUDPIPCore(self.ethphy, 0x12345678abcd, convert_ip(ip), clk_freq=self.sys_clk_freq) self.add_csr("udp_core") self.udp_port = udp_port = self.udp_core.udp.crossbar.get_port(4321, 8) ddr_wr_port, ddr_rd_port = self.sdram.crossbar.get_port( "write"), self.sdram.crossbar.get_port("read") self.submodules.data_pipe = DataPipe(ddr_wr_port, ddr_rd_port, udp_port) self.add_csr("data_pipe")
def __init__(self, ip="192.168.19.70", **kwargs): super().__init__(with_ethernet=True, **kwargs) if kwargs.get('uart_name') == "crossover+bridge": self.uart.add_auto_tx_flush(self.sys_clk_freq) print("added_flush") self.platform.add_extension(marble.break_off_pmod) self.user_leds = self.platform.request("pmod0") self.submodules.udp_core = LiteEthUDPIPCore(self.ethphy, 0x12345678abcd, convert_ip(ip), clk_freq=self.sys_clk_freq) self.add_csr("udp_core") self.udp_port = udp_port = self.udp_core.udp.crossbar.get_port(4321, 8) ddr_wr_port, ddr_rd_port = self.sdram.crossbar.get_port("write"), self.sdram.crossbar.get_port("read") REAL_ADC = True if REAL_ADC: self.add_zest() adc_dw = self.zest.dw adc_source = self.zest.source self.submodules.async_fifo = async_fifo = ClockDomainsRenamer( {"write": "adc", "read": "sys"} )(AsyncFIFO([("data", adc_dw)], depth=8, buffered=True)) self.comb += [ async_fifo.sink.data.eq(self.zest.source.data), async_fifo.sink.valid.eq(self.zest.source.valid), async_fifo.source.ready.eq(1) ] self.adc_source = adc_source = async_fifo.source else: adc_dw = 64 self.submodules.adcs = adcs = ADCStream(1, adc_dw) self.adc_source = adc_source = adcs.source self.submodules.data_pipe = DataPipe(ddr_wr_port, ddr_rd_port, udp_port, adc_source, adc_dw) self.add_csr("data_pipe") self.add_rom("bootrom", origin=0x20000000, size=2**14, contents=get_mem_data("firmware/app.bin", endianness="little")) self.add_constant("ROM_BOOT_ADDRESS", 0x20000000)
def __init__(self): self.platform = platform = FireSensePlatform() sys_clk_freq = int(150e6) SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, cpu_type=None, with_uart=False, csr_data_width=32, ident="Versa ECP5 test SoC", ident_version=True) # crg self.submodules.crg = _CRG(platform, sys_clk_freq) # uart self.submodules.bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq, baudrate=1000000) self.add_wb_master(self.bridge.wishbone) # ethernet phy ethphy = LiteEthPHYRGMII(platform.request("eth_clocks"), platform.request("eth")) ethcore = LiteEthUDPIPCore(ethphy, mac_address=0x10e2d5000000, ip_address=convert_ip("192.168.1.50"), clk_freq=sys_clk_freq, with_icmp=False) self.submodules += ethphy, ethcore # led blinking led_counter = Signal(32) self.sync += led_counter.eq(led_counter + 1) self.comb += platform.request("user_led", 0).eq(led_counter[25]) # analyzer analyzer_signals = [ # ethphy.sink, ethcore.mac.core.crc32_checker.source ] self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 128, "eth_rx")
def __init__(self, phy, clk_freq, mac_address, ip_address, port): PHYCore.__init__(self, phy, clk_freq) self.submodules.core = LiteEthUDPIPCore(self.ethphy, mac_address, convert_ip(ip_address), clk_freq) udp_port = self.core.udp.crossbar.get_port(port, 8) # XXX avoid manual connect udp_sink = self.platform.request("udp_sink") self.comb += [ # control udp_port.sink.valid.eq(udp_sink.valid), udp_port.sink.last.eq(udp_sink.last), udp_sink.ready.eq(udp_port.sink.ready), # param udp_port.sink.src_port.eq(udp_sink.src_port), udp_port.sink.dst_port.eq(udp_sink.dst_port), udp_port.sink.ip_address.eq(udp_sink.ip_address), udp_port.sink.length.eq(udp_sink.length), # payload udp_port.sink.data.eq(udp_sink.data), udp_port.sink.error.eq(udp_sink.error) ] udp_source = self.platform.request("udp_source") self.comb += [ # control udp_source.valid.eq(udp_port.source.valid), udp_source.last.eq(udp_port.source.last), udp_port.source.ready.eq(udp_source.ready), # param udp_source.src_port.eq(udp_port.source.src_port), udp_source.dst_port.eq(udp_port.source.dst_port), udp_source.ip_address.eq(udp_port.source.ip_address), udp_source.length.eq(udp_port.source.length), # payload udp_source.data.eq(udp_port.source.data), udp_source.error.eq(udp_port.source.error) ]
def __init__(self): D = 8 # Datapath width [bytes] self.clock_domains.cd_sys = ClockDomain() self.clock_domains.eth_tx = ClockDomain() self.clock_domains.eth_rx = ClockDomain() self.clk_freq = 100000 self.submodules.ethphy = phy.PHY(D * 8, debug=True) self.submodules.mac_model = mac.MAC(self.ethphy, debug=True, loopback=False) self.submodules.arp_model = arp.ARP(self.mac_model, dst_mac, dst_ip, debug=True) self.submodules.ip_model = ip.IP(self.mac_model, dst_mac, dst_ip, debug=True, loopback=False) self.submodules.icmp_model = icmp.ICMP(self.ip_model, dst_ip, debug=True) ethcore = LiteEthUDPIPCore(phy=self.ethphy, mac_address=local_mac, ip_address=local_ip, clk_freq=self.clk_freq, dw=self.ethphy.dw) self.submodules.ethcore = ethcore # ---------------------- # UDP packet sender # ---------------------- self.udpp = self.ethcore.udp.crossbar.get_port(1337, D * 8) self.submodules.udp_sender = UdpSender(D=D, dst_ip="192.168.1.10") self.comb += [ self.udp_sender.source.connect(self.udpp.sink), self.udpp.source.ready.eq(1) ]
def __init__(self, **kwargs): HelloLtc.__init__(self, **kwargs) p = self.platform # ethernet PHY and UDP/IP stack mac_address = 0x01E625688D7C ip_address = "192.168.1.50" self.submodules.ethphy = LiteEthPHY( p.request("eth_clocks"), p.request("eth"), self.clk_freq, # avoid huge reset delay in simulation with_hw_init_reset="synth" in argv ) self.submodules.core = LiteEthUDPIPCore( self.ethphy, mac_address, convert_ip(ip_address), self.clk_freq ) # Etherbone = wishbone master = read and write registers remotely self.submodules.etherbone = LiteEthEtherbone( self.core.udp, 1234, mode="master" ) self.add_wb_master(self.etherbone.wishbone.bus)
def __init__(self, platform, mac_address=0x10e2d5000000, ip_address="192.168.1.42", **kwargs): BaseSoC.__init__(self, platform, **kwargs) # Ethernet PHY and UDP/IP stack self.submodules.ethphy = LiteEthPHYMII(platform.request("eth_clocks"), platform.request("eth")) self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy, mac_address, convert_ip(ip_address), self.clk_freq, with_icmp=False) # Etherbone bridge self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 20000) self.add_wb_master(self.etherbone.master.bus) self.specials += [ Keep(self.ethphy.crg.cd_eth_rx.clk), Keep(self.ethphy.crg.cd_eth_tx.clk) ] platform.add_platform_command( """ NET "{eth_clocks_rx}" CLOCK_DEDICATED_ROUTE = FALSE; NET "{eth_clocks_rx}" TNM_NET = "GRPeth_clocks_rx"; NET "{eth_rx_clk}" TNM_NET = "GRPeth_rx_clk"; NET "{eth_tx_clk}" TNM_NET = "GRPeth_tx_clk"; TIMESPEC "TSise_sucks1" = FROM "GRPeth_clocks_rx" TO "GRPsys_clk" TIG; TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPeth_clocks_rx" TIG; TIMESPEC "TSise_sucks3" = FROM "GRPeth_tx_clk" TO "GRPsys_clk" TIG; TIMESPEC "TSise_sucks4" = FROM "GRPsys_clk" TO "GRPeth_tx_clk" TIG; TIMESPEC "TSise_sucks5" = FROM "GRPeth_rx_clk" TO "GRPsys_clk" TIG; TIMESPEC "TSise_sucks6" = FROM "GRPsys_clk" TO "GRPeth_rx_clk" TIG; """, eth_clocks_rx=platform.lookup_request("eth_clocks").rx, eth_rx_clk=self.ethphy.crg.cd_eth_rx.clk, eth_tx_clk=self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, sys_clk_freq=int(75e6), toolchain="trellis", **kwargs): BaseSoC.__init__(self, toolchain=toolchain, **kwargs) # Ethernet --------------------------------------------------------------------------------- # phy self.submodules.ethphy = ClockDomainsRenamer("sys2x_i")(LiteEthPHYRGMII( self.platform.request("eth_clocks"), self.platform.request("eth"))) self.add_csr("ethphy") self.submodules.eth_core = ClockDomainsRenamer("sys2x_i")(LiteEthUDPIPCore( phy = self.ethphy, mac_address = 0x10e2d5000001, ip_address = "192.168.1.50", clk_freq = int(2*sys_clk_freq), with_icmp = True)) self.add_udp_loopback(8000, 32, 128, "loopback_32") # etherbone - TODO, doesn't work yet # self.submodules.etherbone = LiteEthEtherbone(self.eth_core.udp, 1234) # self.add_wb_master(self.etherbone.wishbone.bus) # litescope - TODO, needs etherbone to work first # analyzer_signals = [ # self.loopback_32.sink # ] # self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 4096, csr_csv="tools/analyzer.csv") # self.add_csr("analyzer") # timing constraints self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, platform): sys_clk_freq = int(150e6) SoCMini.__init__(self, platform, sys_clk_freq, ident="UDPLoopback", ident_version=True) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # Ethernet --------------------------------------------------------------------------------- # phy self.submodules.eth_phy = LiteEthPHYRGMII( clock_pads=platform.request("eth_clocks"), pads=platform.request("eth")) self.add_csr("eth_phy") # core self.submodules.eth_core = LiteEthUDPIPCore(phy=self.eth_phy, mac_address=0x10e2d5000000, ip_address="192.168.1.50", clk_freq=sys_clk_freq) # add udp loopback on port 6000 with dw=8 self.add_udp_loopback(6000, 8, 128, "loopback_8") # add udp loopback on port 8000 with dw=32 self.add_udp_loopback(8000, 32, 128, "loopback_32") # timing constraints self.eth_phy.crg.cd_eth_rx.clk.attr.add("keep") self.eth_phy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_rx.clk, 1e9 / 125e6) self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_tx.clk, 1e9 / 125e6)
def __init__(self, platform, mac_address=0x10e2d5000000, ip_address="192.168.1.50"): clk_freq = int(1e9/platform.default_clk_period) SoCMini.__init__(self, platform, clk_freq, ident="Daisho USB3.0 Test Design", ident_version=True) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) # uart <--> wishbone self.submodules.uart_bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200) self.add_wb_master(self.uart_bridge.wishbone) # ethernet PHY and UDP/IP stack self.submodules.eth_phy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"), clk_freq=clk_freq) self.submodules.eth_core = LiteEthUDPIPCore(self.eth_phy, mac_address, convert_ip(ip_address), clk_freq) # ethernet <--> wishbone self.submodules.etherbone = LiteEthEtherbone(self.eth_core.udp, 1234) self.add_wb_master(self.etherbone.wishbone.bus) # timing constraints self.crg.cd_sys.clk.attr.add("keep") self.eth_phy.crg.cd_eth_rx.clk.attr.add("keep") self.eth_phy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, 6.0) self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_rx.clk, 8.0) self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_tx.clk, 8.0) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.eth_phy.crg.cd_eth_rx.clk, self.eth_phy.crg.cd_eth_tx.clk)
def __init__(self, platform, connector="pcie", with_etherbone=False, with_analyzer=False): sys_clk_freq = int(125e6) # SoCMini ---------------------------------------------------------------------------------- SoCMini.__init__(self, platform, sys_clk_freq, ident="USB3SoC", ident_version=True) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # Serial Bridge ---------------------------------------------------------------------------- self.submodules.bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq) self.add_wb_master(self.bridge.wishbone) # Ethernet <--> Wishbone ------------------------------------------------------------------- if with_etherbone: # phy self.submodules.eth_phy = LiteEthPHYRGMII( clock_pads=platform.request("eth_clocks"), pads=platform.request("eth")) self.add_csr("eth_phy") # core self.submodules.eth_core = LiteEthUDPIPCore( phy=self.eth_phy, mac_address=0x10e2d5000000, ip_address="192.168.1.50", clk_freq=sys_clk_freq) # etherbone self.submodules.etherbone = LiteEthEtherbone( self.eth_core.udp, 1234) self.add_wb_master(self.etherbone.wishbone.bus) # timing constraints self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_rx.clk, 1e9 / 125e6) self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_tx.clk, 1e9 / 125e6) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.eth_phy.crg.cd_eth_rx.clk, self.eth_phy.crg.cd_eth_tx.clk) # USB3 SerDes ------------------------------------------------------------------------------ usb3_serdes = ECP5USB3SerDes( platform, sys_clk=self.crg.cd_sys.clk, sys_clk_freq=sys_clk_freq, refclk_pads=ClockSignal("clk200"), refclk_freq=200e6, tx_pads=platform.request(connector + "_tx"), rx_pads=platform.request(connector + "_rx"), channel=1 if connector == "sma" else 0) self.submodules += usb3_serdes # USB3 PIPE -------------------------------------------------------------------------------- usb3_pipe = USB3PIPE(serdes=usb3_serdes, sys_clk_freq=sys_clk_freq) self.submodules.usb3_pipe = usb3_pipe self.comb += usb3_pipe.reset.eq(~platform.request("rst_n")) # USB3 Core -------------------------------------------------------------------------------- usb3_core = USB3Core(platform) self.submodules.usb3_core = usb3_core self.comb += [ usb3_pipe.source.connect(usb3_core.sink), usb3_core.source.connect(usb3_pipe.sink), usb3_core.reset.eq(~usb3_pipe.ready), ] self.add_csr("usb3_core") # Leds ------------------------------------------------------------------------------------- self.comb += platform.request("user_led", 0).eq(~usb3_serdes.ready) self.comb += platform.request("user_led", 1).eq(~usb3_pipe.ready) # Analyzer --------------------------------------------------------------------------------- if with_analyzer: analyzer_signals = [ # LFPS usb3_serdes.tx_idle, usb3_serdes.rx_idle, usb3_serdes.tx_pattern, usb3_serdes.rx_polarity, usb3_pipe.lfps.rx_polling, usb3_pipe.lfps.tx_polling, # Training Sequence usb3_pipe.ts.tx_enable, usb3_pipe.ts.rx_ts1, usb3_pipe.ts.rx_ts2, usb3_pipe.ts.tx_enable, usb3_pipe.ts.tx_tseq, usb3_pipe.ts.tx_ts1, usb3_pipe.ts.tx_ts2, usb3_pipe.ts.tx_done, # LTSSM usb3_pipe.ltssm.polling.fsm, usb3_pipe.ready, # Endpoints usb3_serdes.rx_datapath.skip_remover.skip, usb3_serdes.source, usb3_serdes.sink, usb3_pipe.source, usb3_pipe.sink, ] self.submodules.analyzer = LiteScopeAnalyzer( analyzer_signals, 4096, csr_csv="tools/analyzer.csv") self.add_csr("analyzer")