def __init__(self, platform): sys_clk_freq = int(125e6) SoCMini.__init__(self, platform, sys_clk_freq, csr_data_width=32, ident="LitePCIe example design", ident_version=True) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform) # PCIe PHY --------------------------------------------------------------------------------- self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1")) self.add_csr("pcie_phy") # PCIe Endpoint ---------------------------------------------------------------------------- self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) # PCIe Wishbone bridge --------------------------------------------------------------------- self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1) self.add_wb_master(self.pcie_bridge.wishbone) # PCIe DMA --------------------------------------------------------------------------------- self.submodules.pcie_dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True) self.add_csr("pcie_dma") # PCIe MSI --------------------------------------------------------------------------------- self.submodules.pcie_msi = LitePCIeMSI() self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA_WRITER": self.pcie_dma.writer.irq, "PCIE_DMA_READER": self.pcie_dma.reader.irq } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i)
def __init__(self, platform, **kwargs): BaseSoC.__init__(self, platform, **kwargs) # pcie phy self.submodules.pcie_phy = S7PCIEPHY(platform, link_width=1, cd="sys") # pcie endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, with_reordering=True) # pcie wishbone bridge self.submodules.pcie_wishbone = LitePCIeWishboneBridge( self.pcie_endpoint, lambda a: 1) self.add_wb_master(self.pcie_wishbone.wishbone) # pcie dma self.submodules.dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True) self.dma.source.connect(self.dma.sink) # pcie msi self.submodules.msi = LitePCIeMSI() self.comb += self.msi.source.connect(self.pcie_phy.interrupt) self.interrupts = { "dma_writer": self.dma.writer.irq, "dma_reader": self.dma.reader.irq } for k, v in sorted(self.interrupts.items()): self.comb += self.msi.irqs[self.interrupt_map[k]].eq(v) # flash the led on pcie clock counter = Signal(32) self.sync.clk125 += counter.eq(counter + 1) self.comb += platform.request("user_led", 0).eq(counter[26])
def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, **kwargs): platform = fk33.Platform() # SoCCore ---------------------------------------------------------------------------------- if kwargs.get("uart_name", "serial") == "serial": kwargs["uart_name"] = "jtag_uart" # Defaults to JTAG-UART. SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on FK33", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # PCIe ------------------------------------------------------------------------------------- if with_pcie: assert self.csr_data_width == 32 # PHY self.submodules.pcie_phy = USPHBMPCIEPHY( platform, platform.request("pcie_x4"), data_width=128, bar0_size=0x20000) # Endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint( self.pcie_phy, max_pending_requests=8) # Wishbone bridge self.submodules.pcie_bridge = LitePCIeWishboneBridge( self.pcie_endpoint, base_address=self.mem_map["csr"]) self.add_wb_master(self.pcie_bridge.wishbone) # DMA0 self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering=True, buffering_depth=1024, with_loopback=True) self.add_constant("DMA_CHANNELS", 1) # MSI self.submodules.pcie_msi = LitePCIeMSI() self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, "PCIE_DMA0_READER": self.pcie_dma0.reader.irq, } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, platform, speed="gen2", nlanes=4): data_width, sys_clk_freq = self.configs[speed + ":x{}".format(nlanes)] # SoCMini ---------------------------------------------------------------------------------- SoCMini.__init__(self, platform, sys_clk_freq, csr_data_width = 32, ident = "LitePCIe example design on FK33 ({}:x{})".format(speed, nlanes), ident_version = True, with_uart = False) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # PCIe ------------------------------------------------------------------------------------- # PHY self.submodules.pcie_phy = USPHBMPCIEPHY(platform, platform.request("pcie_x" + str(nlanes)), speed = speed, data_width = data_width, bar0_size = 0x20000, ) # Endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, endianness = "little", max_pending_requests = 8 ) # Wishbone bridge self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, base_address = self.mem_map["csr"]) self.add_wb_master(self.pcie_bridge.wishbone) # DMA0 self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering = True, buffering_depth=1024, with_loopback = True) # DMA1 self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering = True, buffering_depth=1024, with_loopback = True) self.add_constant("DMA_CHANNELS", 2) # MSI self.submodules.pcie_msi = LitePCIeMSI() self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, "PCIE_DMA0_READER": self.pcie_dma0.reader.irq, "PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq, "PCIE_DMA1_READER": self.pcie_dma1.reader.irq, } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i)
def __init__(self, platform, with_uart_bridge=True, **kwargs): clk_freq = 125*1000000 kwargs['cpu_type'] = None SoCCore.__init__(self, platform, clk_freq, shadow_base=0x00000000, csr_data_width=32, with_uart=False, ident="NeTV2 LiteX PCIe SoC", with_timer=False, **kwargs) self.submodules.crg = _CRG(platform) self.submodules.dna = dna.DNA() self.submodules.xadc = xadc.XADC() # pcie phy self.submodules.pcie_phy = S7PCIEPHY(platform, link_width=1) # pci endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, with_reordering=True) # pcie wishbone bridge self.add_cpu_or_bridge(LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1)) self.add_wb_master(self.cpu_or_bridge.wishbone) # pcie dma self.submodules.dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True) self.dma.source.connect(self.dma.sink) if with_uart_bridge: self.submodules.uart_bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200) self.add_wb_master(self.uart_bridge.wishbone) # pcie msi self.submodules.msi = LitePCIeMSI() self.comb += self.msi.source.connect(self.pcie_phy.interrupt) self.interrupts = { "dma_writer": self.dma.writer.irq, "dma_reader": self.dma.reader.irq } for k, v in sorted(self.interrupts.items()): self.comb += self.msi.irqs[self.interrupt_map[k]].eq(v) # flash the led on pcie clock counter = Signal(32) self.sync += counter.eq(counter + 1) self.comb += platform.request("user_led", 0).eq(counter[26])
def __init__(self, platform, with_uart_bridge=True): sys_clk_freq = int(125e6) SoCCore.__init__(self, platform, sys_clk_freq, cpu_type=None, shadow_base=0x00000000, csr_data_width=32, with_uart=False, ident="LitePCIe example design", ident_version=True, with_timer=False) self.submodules.crg = _CRG(platform) # PCIe endpoint self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1")) self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, with_reordering=True) # PCIe Wishbone bridge self.add_cpu_or_bridge( LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1)) self.add_wb_master(self.cpu_or_bridge.wishbone) # PCIe DMA self.submodules.dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True) if with_uart_bridge: self.submodules.uart_bridge = UARTWishboneBridge( platform.request("serial"), sys_clk_freq, baudrate=115200) self.add_wb_master(self.uart_bridge.wishbone) # MSI self.submodules.msi = LitePCIeMSI() self.comb += self.msi.source.connect(self.pcie_phy.msi) self.interrupts = { "DMA_WRITER": self.dma.writer.irq, "DMA_READER": self.dma.reader.irq } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i)
def __init__(self, platform, with_uart_bridge=True): clk_freq = 125 * 1000000 SoCCore.__init__(self, platform, clk_freq, cpu_type=None, shadow_base=0x00000000, csr_data_width=32, with_uart=False, ident="LitePCIe example design", with_timer=False) self.submodules.crg = _CRG(platform) # PCIe endpoint self.submodules.pcie_phy = S7PCIEPHY(platform, link_width=2) self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, with_reordering=True) # PCIe Wishbone bridge self.add_cpu_or_bridge( LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1)) self.add_wb_master(self.cpu_or_bridge.wishbone) # PCIe DMA self.submodules.dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True) self.dma.source.connect(self.dma.sink) if with_uart_bridge: self.submodules.uart_bridge = UARTWishboneBridge( platform.request("serial"), clk_freq, baudrate=115200) self.add_wb_master(self.uart_bridge.wishbone) # MSI self.submodules.msi = LitePCIeMSI() self.comb += self.msi.source.connect(self.pcie_phy.interrupt) self.interrupts = { "dma_writer": self.dma.writer.irq, "dma_reader": self.dma.reader.irq } for k, v in sorted(self.interrupts.items()): self.comb += self.msi.irqs[self.interrupt_map[k]].eq(v)
def __init__(self, platform, **kwargs): BaseSoC.__init__(self, platform, csr_data_width=32, **kwargs) # pcie phy self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1")) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) # pcie endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, with_reordering=True) # pcie wishbone bridge self.submodules.pcie_wishbone = LitePCIeWishboneBridge( self.pcie_endpoint, lambda a: 1) self.add_wb_master(self.pcie_wishbone.wishbone) # pcie dma self.submodules.dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True) self.dma.source.connect(self.dma.sink) # pcie msi self.submodules.msi = LitePCIeMSI() self.comb += self.msi.source.connect(self.pcie_phy.msi) self.interrupts = { "DMA_WRITER": self.dma.writer.irq, "DMA_READER": self.dma.reader.irq } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) # pcie led pcie_counter = Signal(32) self.sync.pcie += pcie_counter.eq(pcie_counter + 1) self.comb += self.pcie_led.eq(pcie_counter[26])
def __init__(self, sys_clk_freq=int(125e6), ddram_channel=0, with_pcie=False, **kwargs): platform = xcu1525.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on XCU1525", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR4 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = usddrphy.USPDDRPHY( pads=platform.request("ddram", ddram_channel), memtype="DDR4", sys_clk_freq=sys_clk_freq, iodelay_clk_freq=500e6, cmd_latency=1) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT40A512M8(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Workadound for Vivado 2018.2 DRC, can be ignored and probably fixed on newer Vivado versions. platform.add_platform_command( "set_property SEVERITY {{Warning}} [get_drc_checks PDCN-2736]") # PCIe ------------------------------------------------------------------------------------- if with_pcie: # PHY self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"), data_width=128, bar0_size=0x20000) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") # Endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint( self.pcie_phy, max_pending_requests=8) # Wishbone bridge self.submodules.pcie_bridge = LitePCIeWishboneBridge( self.pcie_endpoint, base_address=self.mem_map["csr"]) self.add_wb_master(self.pcie_bridge.wishbone) # DMA0 self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering=True, buffering_depth=1024, with_loopback=True) self.add_csr("pcie_dma0") self.add_constant("DMA_CHANNELS", 1) # MSI self.submodules.pcie_msi = LitePCIeMSI() self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, "PCIE_DMA0_READER": self.pcie_dma0.reader.irq, } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, platform, nlanes=4): sys_clk_freq = int(125e6) # SoCMini ---------------------------------------------------------------------------------- SoCMini.__init__(self, platform, sys_clk_freq, csr_data_width=32, ident="LitePCIe example design", ident_version=True, with_uart=True, uart_name="bridge") # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) self.add_csr("crg") # PCIe ------------------------------------------------------------------------------------- # PHY self.submodules.pcie_phy = USPCIEPHY(platform, platform.request("pcie_x" + str(nlanes)), data_width=128, bar0_size=0x20000) #self.pcie_phy.add_timing_constraints(platform) # FIXME platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") # Endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint( self.pcie_phy, endianness="little", max_pending_requests=8) # Wishbone bridge self.submodules.pcie_bridge = LitePCIeWishboneBridge( self.pcie_endpoint, base_address=self.mem_map["csr"]) self.add_wb_master(self.pcie_bridge.wishbone) # DMA0 self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering=True, buffering_depth=1024, with_loopback=True) self.add_csr("pcie_dma0") # DMA1 self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering=True, buffering_depth=1024, with_loopback=True) self.add_csr("pcie_dma1") self.add_constant("DMA_CHANNELS", 2) # MSI self.submodules.pcie_msi = LitePCIeMSI() self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, "PCIE_DMA0_READER": self.pcie_dma0.reader.irq, "PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq, "PCIE_DMA1_READER": self.pcie_dma1.reader.irq, } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i)
def __init__(self, platform, with_pcie_uart=True): sys_clk_freq = int(100e6) # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__( self, platform, sys_clk_freq, csr_data_width=32, integrated_rom_size=0x10000, integrated_sram_size=0x10000, integrated_main_ram_size= 0x10000, # FIXME: keep this for initial PCIe tests ident="Tagus LiteX Test SoC", ident_version=True, with_uart=not with_pcie_uart) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) self.add_csr("crg") # DNA -------------------------------------------------------------------------------------- self.submodules.dna = dna.DNA() self.add_csr("dna") # XADC ------------------------------------------------------------------------------------- self.submodules.xadc = xadc.XADC() self.add_csr("xadc") # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq, iodelay_clk_freq=200e6) self.add_csr("ddrphy") sdram_module = MT41J128M16(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings) # PCIe ------------------------------------------------------------------------------------- # pcie phy self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000) self.pcie_phy.cd_pcie.clk.attr.add("keep") platform.add_platform_command( "create_clock -name pcie_clk -period 8 [get_nets pcie_clk]") platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") # pcie endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) # pcie wishbone bridge self.submodules.pcie_wishbone = LitePCIeWishboneBridge( self.pcie_endpoint, lambda a: 1, base_address=self.mem_map["csr"]) self.add_wb_master(self.pcie_wishbone.wishbone) # pcie dma self.submodules.pcie_dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering=True, buffering_depth=1024, with_loopback=True) self.add_csr("pcie_dma") # pcie msi self.submodules.pcie_msi = LitePCIeMSI() self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.msis = { "DMA_WRITER": self.pcie_dma.writer.irq, "DMA_READER": self.pcie_dma.reader.irq } for i, (k, v) in enumerate(sorted(self.msis.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) # pcie_uart if with_pcie_uart: class PCIeUART(Module, AutoCSR): def __init__(self, uart): self.rx_valid = CSRStatus() self.rx_ready = CSR() self.rx_data = CSRStatus(8) self.tx_valid = CSR() self.tx_ready = CSRStatus() self.tx_data = CSRStorage(8) # # # # cpu to pcie self.comb += [ self.rx_valid.status.eq(uart.sink.valid), uart.sink.ready.eq(self.rx_ready.re), self.rx_data.status.eq(uart.sink.data), ] # pcie to cpu self.sync += [ If(self.tx_valid.re, uart.source.valid.eq(1)).Elif( uart.source.ready, uart.source.valid.eq(0)) ] self.comb += [ self.tx_ready.status.eq(~uart.source.valid), uart.source.data.eq(self.tx_data.storage) ] uart_interface = RS232PHYInterface() self.submodules.uart = UART(uart_interface) self.add_csr("uart") self.add_interrupt("uart") self.submodules.pcie_uart = PCIeUART(uart_interface) self.add_csr("pcie_uart") # Leds ------------------------------------------------------------------------------------- # led blinking (sys) sys_counter = Signal(32) self.sync.sys += sys_counter.eq(sys_counter + 1) self.comb += [ platform.request("user_led", 0).eq(1), platform.request("user_led", 1).eq(sys_counter[26]), platform.request("user_led", 2).eq(1), ]
def __init__(self, with_pcie=False, **kwargs): platform = acorn_cle_215.Platform() sys_clk_freq = int(100e6) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Acorn CLE 215+", ident_version = True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) self.add_csr("crg") # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 200e6) self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT41K512M16(sys_clk_freq, "1:4"), origin = self.mem_map["main_ram"], size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), l2_cache_reverse = True ) # PCIe ------------------------------------------------------------------------------------- if with_pcie: # PHY self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, bar0_size = 0x20000) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") self.comb += platform.request("pcie_clkreq_n").eq(0) # Endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8) # Wishbone bridge self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, base_address = self.mem_map["csr"]) self.add_wb_master(self.pcie_bridge.wishbone) # DMA0 self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering = True, buffering_depth=1024, with_loopback = True) self.add_csr("pcie_dma0") # DMA1 self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering = True, buffering_depth=1024, with_loopback = True) self.add_csr("pcie_dma1") self.add_constant("DMA_CHANNELS", 2) # MSI self.submodules.pcie_msi = LitePCIeMSI() self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, "PCIE_DMA0_READER": self.pcie_dma0.reader.irq, "PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq, "PCIE_DMA1_READER": self.pcie_dma1.reader.irq, } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) self.add_csr("leds")
def __init__(self, platform, **kwargs): sys_clk_freq = int(100e6) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tagus", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) self.add_csr("crg") # DNA -------------------------------------------------------------------------------------- self.submodules.dna = DNA() self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk) self.add_csr("dna") # XADC ------------------------------------------------------------------------------------- self.submodules.xadc = XADC() self.add_csr("xadc") # ICAP ------------------------------------------------------------------------------------- self.submodules.icap = ICAP(platform) self.icap.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk) self.add_csr("icap") # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq, iodelay_clk_freq=200e6) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT41J128M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # PCIe ------------------------------------------------------------------------------------- # PHY self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), data_width=64, bar0_size=0x20000) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") # Endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) # Wishbone bridge self.submodules.pcie_bridge = LitePCIeWishboneBridge( self.pcie_endpoint, base_address=self.mem_map["csr"]) self.add_wb_master(self.pcie_bridge.wishbone) # DMA0 self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering=True, buffering_depth=1024, with_loopback=True) self.add_csr("pcie_dma0") # DMA1 self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering=True, buffering_depth=1024, with_loopback=True) self.add_csr("pcie_dma1") self.add_constant("DMA_CHANNELS", 2) # MSI self.submodules.pcie_msi = LitePCIeMSI() self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, "PCIE_DMA0_READER": self.pcie_dma0.reader.irq, "PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq, "PCIE_DMA1_READER": self.pcie_dma1.reader.irq, } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i)
def __init__(self, platform, *args, **kwargs): BaseSoC.__init__(self, platform, csr_data_width=32, *args, **kwargs) sys_clk_freq = int(100e6) # pcie phy self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=32 * 1024 * 1024) self.add_csr("pcie_phy") platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) # pcie endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) # pcie wishbone bridge self.submodules.pcie_bridge = LitePCIeWishboneBridge( self.pcie_endpoint, lambda a: 1, shadow_base=0x40000000) self.submodules.wb_swap = WishboneEndianSwap(self.pcie_bridge.wishbone) self.add_wb_master(self.wb_swap.wishbone) # pcie dma self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True) self.add_csr("pcie_dma0") # pcie msi self.submodules.pcie_msi = LitePCIeMSI() self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, "PCIE_DMA0_READER": self.pcie_dma0.reader.irq } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) # hdmi in 0 hdmi_in0_pads = platform.request("hdmi_in", 0) self.submodules.hdmi_in0_freq = FreqMeter(period=sys_clk_freq) self.add_csr("hdmi_in0_freq") self.submodules.hdmi_in0 = HDMIIn( hdmi_in0_pads, self.sdram.crossbar.get_port(mode="write"), fifo_depth=1024, device="xc7", split_mmcm=True) self.add_csr("hdmi_in0") self.add_csr("hdmi_in0_edid_mem") self.add_interrupt("hdmi_in0") self.comb += self.hdmi_in0_freq.clk.eq( self.hdmi_in0.clocking.cd_pix.clk), for clk in [ self.hdmi_in0.clocking.cd_pix.clk, self.hdmi_in0.clocking.cd_pix1p25x.clk, self.hdmi_in0.clocking.cd_pix5x.clk ]: self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk) self.platform.add_period_constraint( platform.lookup_request("hdmi_in", 0).clk_p, period_ns(148.5e6)) # hdmi out 0 hdmi_out0_dram_port = self.sdram.crossbar.get_port(mode="read", dw=16, cd="hdmi_out0_pix", reverse=True) self.submodules.hdmi_out0 = VideoOut(platform.device, platform.request("hdmi_out", 0), hdmi_out0_dram_port, "ycbcr422", fifo_depth=4096) self.add_csr("hdmi_out0") for clk in [ self.hdmi_out0.driver.clocking.cd_pix.clk, self.hdmi_out0.driver.clocking.cd_pix5x.clk ]: self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk) for name, value in sorted(self.platform.hdmi_infos.items()): self.add_constant(name, value)
def __init__(self, platform, **kwargs): sys_clk_freq = int(100e6) # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tagus", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) self.add_csr("crg") # DNA -------------------------------------------------------------------------------------- self.submodules.dna = dna.DNA() self.add_csr("dna") # XADC ------------------------------------------------------------------------------------- self.submodules.xadc = xadc.XADC() self.add_csr("xadc") # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq, iodelay_clk_freq=200e6) self.add_csr("ddrphy") sdram_module = MT41J128M16(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, geom_settings=sdram_module.geom_settings, timing_settings=sdram_module.timing_settings) # PCIe ------------------------------------------------------------------------------------- # pcie phy self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") # pcie endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) # pcie wishbone bridge self.submodules.pcie_wishbone = LitePCIeWishboneBridge( self.pcie_endpoint, lambda a: 1, base_address=self.mem_map["csr"]) self.add_wb_master(self.pcie_wishbone.wishbone) # pcie dma self.submodules.pcie_dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering=True, buffering_depth=1024, with_loopback=True) self.add_csr("pcie_dma") # pcie msi self.submodules.pcie_msi = LitePCIeMSI() self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.msis = { "DMA_WRITER": self.pcie_dma.writer.irq, "DMA_READER": self.pcie_dma.reader.irq } for i, (k, v) in enumerate(sorted(self.msis.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i)
def __init__(self, platform, core_config): platform.add_extension(get_common_ios()) platform.add_extension(get_pcie_ios(core_config["phy_lanes"])) for i in range(core_config["dma_channels"]): platform.add_extension( get_axi_dma_ios(i, core_config["phy_data_width"])) assert core_config["msi_irqs"] <= 16 platform.add_extension(get_msi_irqs_ios(width=core_config["msi_irqs"])) sys_clk_freq = int(float(core_config.get("sys_clk_freq"))) # SoCMini ---------------------------------------------------------------------------------- SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, csr_data_width=32, ident="LitePCIe standalone core", ident_version=True) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = LitePCIeCRG(platform, sys_clk_freq) self.add_csr("crg") # PCIe PHY --------------------------------------------------------------------------------- self.submodules.pcie_phy = core_config["phy"]( platform, platform.request("pcie"), data_width=core_config["phy_data_width"], bar0_size=core_config["phy_bar0_size"]) self.pcie_phy.use_external_hard_ip("./") self.add_csr("pcie_phy") # PCIe Endpoint ---------------------------------------------------------------------------- self.submodules.pcie_endpoint = LitePCIeEndpoint( self.pcie_phy, endianness=core_config["endianness"]) # PCIe Wishbone bridge --------------------------------------------------------------------- pcie_wishbone = LitePCIeWishboneBridge( self.pcie_endpoint, lambda a: 1, qword_aligned=core_config["qword_aligned"]) self.submodules += pcie_wishbone self.add_wb_master(pcie_wishbone.wishbone) # PCIe MMAP -------------------------------------------------------------------------------- if core_config["mmap"]: platform.add_extension(get_axi_lite_mmap_ios(aw=32, dw=32)) wb = wishbone.Interface(data_width=32) self.add_wb_slave(core_config["mmap_base"], wb, core_config["mmap_size"]) self.add_memory_region("mmap", core_config["mmap_base"], core_config["mmap_size"], type="io") axi = AXILiteInterface(data_width=32, address_width=32) wb2axi = Wishbone2AXILite(wb, axi) self.submodules += wb2axi mmap_ios = platform.request("mmap_axi_lite") self.comb += [ # aw mmap_ios.awvalid.eq(axi.aw.valid), axi.aw.ready.eq(mmap_ios.awready), mmap_ios.awaddr.eq(axi.aw.addr), # w mmap_ios.wvalid.eq(axi.w.valid), axi.w.ready.eq(mmap_ios.wready), mmap_ios.wstrb.eq(axi.w.strb), mmap_ios.wdata.eq(axi.w.data), # b axi.b.valid.eq(mmap_ios.bvalid), mmap_ios.bready.eq(axi.b.ready), axi.b.resp.eq(mmap_ios.bresp), # ar mmap_ios.arvalid.eq(axi.ar.valid), axi.ar.ready.eq(mmap_ios.arready), mmap_ios.araddr.eq(axi.ar.addr), # r axi.r.valid.eq(mmap_ios.rvalid), mmap_ios.rready.eq(axi.r.ready), axi.r.data.eq(mmap_ios.rdata), axi.r.resp.eq(mmap_ios.rresp), ] # PCIe DMA --------------------------------------------------------------------------------- pcie_dmas = [] self.add_constant("DMA_CHANNELS", core_config["dma_channels"]) for i in range(core_config["dma_channels"]): pcie_dma = LitePCIeDMA( self.pcie_phy, self.pcie_endpoint, with_buffering=core_config["dma_buffering"] != 0, buffering_depth=core_config["dma_buffering"], with_loopback=core_config["dma_loopback"], with_synchronizer=core_config["dma_synchronizer"], with_monitor=core_config["dma_monitor"]) setattr(self.submodules, "pcie_dma" + str(i), pcie_dma) self.add_csr("pcie_dma{}".format(i)) dma_writer_ios = platform.request("dma{}_writer_axi".format(i)) dma_reader_ios = platform.request("dma{}_reader_axi".format(i)) self.add_interrupt("pcie_dma{}_writer".format(i)) self.add_interrupt("pcie_dma{}_reader".format(i)) self.comb += [ # Writer IOs pcie_dma.sink.valid.eq(dma_writer_ios.tvalid), dma_writer_ios.tready.eq(pcie_dma.sink.ready), pcie_dma.sink.last.eq(dma_writer_ios.tlast), pcie_dma.sink.data.eq(dma_writer_ios.tdata), # Reader IOs dma_reader_ios.tvalid.eq(pcie_dma.source.valid), pcie_dma.source.ready.eq(dma_reader_ios.tready), dma_reader_ios.tlast.eq(pcie_dma.source.last), dma_reader_ios.tdata.eq(pcie_dma.source.data), ] # PCIe MSI --------------------------------------------------------------------------------- self.submodules.pcie_msi = LitePCIeMSI(width=32) self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = {} for i in range(core_config["dma_channels"]): self.interrupts["pcie_dma" + str(i) + "_writer"] = getattr( self, "pcie_dma" + str(i)).writer.irq self.interrupts["pcie_dma" + str(i) + "_reader"] = getattr( self, "pcie_dma" + str(i)).reader.irq for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k.upper() + "_INTERRUPT", i) assert len(self.interrupts.keys()) <= 16 self.comb += self.pcie_msi.irqs[16:16 + core_config["msi_irqs"]].eq( platform.request("msi_irqs")) # 7-Series specific monitoring/flashing features ------------------------------------------- if platform.device[:3] == "xc7": from litex.soc.cores.dna import DNA from litex.soc.cores.xadc import XADC from litex.soc.cores.icap import ICAP from litex.soc.cores.spi_flash import S7SPIFlash self.submodules.dna = DNA() self.add_csr("dna") self.submodules.xadc = XADC() self.add_csr("xadc") self.submodules.icap = ICAP() self.add_csr("icap") platform.add_extension(get_flash_ios()) self.submodules.flash = S7SPIFlash(platform.request("flash"), sys_clk_freq, 25e6) self.add_csr("flash")
def __init__(self, sys_clk_freq=int(125e6), with_led_chaser=True, with_pcie=False, with_hbm=False, **kwargs): platform = fk33.Platform() if with_hbm: assert 225e6 <= sys_clk_freq <= 450e6 # SoCCore ---------------------------------------------------------------------------------- if kwargs.get("uart_name", "serial") == "serial": kwargs["uart_name"] = "crossover" # Defaults to Crossover-UART. SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on FK33", **kwargs) # JTAGBone -------------------------------------------------------------------------------- self.add_jtagbone( chain=2) # Chain 1 already used by HBM2 debug probes. # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, with_hbm) # HBM -------------------------------------------------------------------------------------- if with_hbm: # Add HBM Core. self.submodules.hbm = hbm = ClockDomainsRenamer({"axi": "sys"})( USPHBM2(platform)) # Get HBM .xci. os.system( "wget https://github.com/litex-hub/litex-boards/files/8178874/hbm_0.xci.txt" ) os.makedirs("ip/hbm", exist_ok=True) os.system("mv hbm_0.xci.txt ip/hbm/hbm_0.xci") # Connect four of the HBM's AXI interfaces to the main bus of the SoC. for i in range(4): axi_hbm = hbm.axi[i] axi_lite_hbm = AXILiteInterface(data_width=256, address_width=33) self.submodules += AXILite2AXI(axi_lite_hbm, axi_hbm) self.bus.add_slave(f"hbm{i}", axi_lite_hbm, SoCRegion(origin=0x4000_0000 + 0x1000_0000 * i, size=0x1000_0000)) # 256MB. # Link HBM2 channel 0 as main RAM self.bus.add_region("main_ram", SoCRegion(origin=0x4000_0000, size=0x1000_0000, linker=True)) # 256MB. # PCIe ------------------------------------------------------------------------------------- if with_pcie: assert self.csr_data_width == 32 # PHY self.submodules.pcie_phy = USPHBMPCIEPHY( platform, platform.request("pcie_x4"), data_width=128, bar0_size=0x20000) # Endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint( self.pcie_phy, max_pending_requests=8) # Wishbone bridge self.submodules.pcie_bridge = LitePCIeWishboneBridge( self.pcie_endpoint, base_address=self.mem_map["csr"]) self.add_wb_master(self.pcie_bridge.wishbone) # DMA0 self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering=True, buffering_depth=1024, with_loopback=True) self.add_constant("DMA_CHANNELS", 1) # MSI self.submodules.pcie_msi = LitePCIeMSI() self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, "PCIE_DMA0_READER": self.pcie_dma0.reader.irq, } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, platform, with_sdram=True, with_ethernet=False, with_etherbone=True, with_sdcard=True, with_pcie=False, with_hdmi_in0=False, with_hdmi_out0=False, with_hdmi_in1=False, with_hdmi_out1=False, with_interboard_communication=False): assert not (with_pcie and with_interboard_communication) sys_clk_freq = int(100e6) sd_freq = int(100e6) SoCSDRAM.__init__(self, platform, sys_clk_freq, #cpu_type="vexriscv", l2_size=32, cpu_type=None, l2_size=32, #csr_data_width=8, csr_address_width=14, csr_data_width=32, csr_address_width=14, integrated_rom_size=0x8000, integrated_sram_size=0x4000, integrated_main_ram_size=0x8000 if not with_sdram else 0, ident="NeTV2 LiteX Test SoC", ident_version=True, reserve_nmi_interrupt=False) # crg self.submodules.crg = CRG(platform, sys_clk_freq) # dnax self.submodules.dna = dna.DNA() # xadc self.submodules.xadc = xadc.XADC() # icap self.submodules.icap = ICAP(platform) # flash self.submodules.flash = Flash(platform.request("flash"), div=math.ceil(sys_clk_freq/25e6)) # sdram if with_sdram: self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq, iodelay_clk_freq=200e6) sdram_module = MT41J128M16(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings(with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True)) # ethernet if with_ethernet: self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"), self.platform.request("eth")) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.crg.cd_eth.clk.attr.add("keep") self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.crg.cd_eth.clk) # etherbone if with_etherbone: self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"), self.platform.request("eth")) self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy, 0x10e2d5000000, convert_ip("192.168.1.50"), sys_clk_freq) self.add_cpu(LiteEthEtherbone(self.ethcore.udp, 1234, mode="master")) self.add_wb_master(self.cpu.wishbone.bus) #self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234, mode="master") #self.add_wb_master(self.etherbone.wishbone.bus) self.crg.cd_eth.clk.attr.add("keep") self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.crg.cd_eth.clk) # sdcard self.submodules.sdclk = SDClockerS7() self.submodules.sdphy = SDPHY(platform.request("sdcard"), platform.device) self.submodules.sdcore = SDCore(self.sdphy) self.submodules.sdtimer = Timer() self.submodules.bist_generator = BISTBlockGenerator(random=True) self.submodules.bist_checker = BISTBlockChecker(random=True) self.comb += [ self.sdcore.source.connect(self.bist_checker.sink), self.bist_generator.source.connect(self.sdcore.sink) ] self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq) self.platform.add_period_constraint(self.sdclk.cd_sd.clk, 1e9/sd_freq) self.platform.add_period_constraint(self.sdclk.cd_sd_fb.clk, 1e9/sd_freq) self.crg.cd_sys.clk.attr.add("keep") self.sdclk.cd_sd.clk.attr.add("keep") self.sdclk.cd_sd_fb.clk.attr.add("keep") self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.sdclk.cd_sd.clk, self.sdclk.cd_sd_fb.clk) # pcie if with_pcie: # pcie phy self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x2")) platform.add_false_path_constraints( self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) # pcie endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, with_reordering=True) # pcie wishbone bridge self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1, shadow_base=0x80000000) self.add_wb_master(self.pcie_bridge.wishbone) # pcie dma self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True) # pcie msi self.submodules.pcie_msi = LitePCIeMSI() self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, "PCIE_DMA0_READER": self.pcie_dma0.reader.irq } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) # interboard communication if with_interboard_communication: self.clock_domains.cd_refclk = ClockDomain() self.submodules.refclk_pll = refclk_pll = S7PLL() refclk_pll.register_clkin(platform.lookup_request("clk50"), 50e6) refclk_pll.create_clkout(self.cd_refclk, 125e6) platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]") # qpll qpll = GTPQuadPLL(ClockSignal("refclk"), 125e6, 1.25e9) print(qpll) self.submodules += qpll # gtp gtp = GTP(qpll, platform.request("interboard_comm_tx"), platform.request("interboard_comm_rx"), sys_clk_freq, clock_aligner=True, internal_loopback=False) self.submodules += gtp counter = Signal(32) self.sync.tx += counter.eq(counter + 1) # send counter to other-board self.comb += [ gtp.encoder.k[0].eq(1), gtp.encoder.d[0].eq((5 << 5) | 28), gtp.encoder.k[1].eq(0), gtp.encoder.d[1].eq(counter[26:]) ] # receive counter and display it on leds self.comb += [ platform.request("user_led", 3).eq(gtp.rx_ready), platform.request("user_led", 4).eq(gtp.decoders[1].d[0]), platform.request("user_led", 5).eq(gtp.decoders[1].d[1]) ] gtp.cd_tx.clk.attr.add("keep") gtp.cd_rx.clk.attr.add("keep") platform.add_period_constraint(gtp.cd_tx.clk, 1e9/gtp.tx_clk_freq) platform.add_period_constraint(gtp.cd_rx.clk, 1e9/gtp.tx_clk_freq) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, gtp.cd_tx.clk, gtp.cd_rx.clk) # hdmi in 0 if with_hdmi_in0: hdmi_in0_pads = platform.request("hdmi_in", 0) self.submodules.hdmi_in0_freq = FreqMeter(period=sys_clk_freq) self.submodules.hdmi_in0 = HDMIIn( hdmi_in0_pads, self.sdram.crossbar.get_port(mode="write"), fifo_depth=512, device="xc7", split_mmcm=True) self.comb += self.hdmi_in0_freq.clk.eq(self.hdmi_in0.clocking.cd_pix.clk), for clk in [self.hdmi_in0.clocking.cd_pix.clk, self.hdmi_in0.clocking.cd_pix1p25x.clk, self.hdmi_in0.clocking.cd_pix5x.clk]: self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk) self.platform.add_period_constraint(platform.lookup_request("hdmi_in", 0).clk_p, period_ns(148.5e6)) # hdmi out 0 if with_hdmi_out0: hdmi_out0_dram_port = self.sdram.crossbar.get_port(mode="read", dw=16, cd="hdmi_out0_pix", reverse=True) self.submodules.hdmi_out0 = VideoOut( platform.device, platform.request("hdmi_out", 0), hdmi_out0_dram_port, "ycbcr422", fifo_depth=4096) for clk in [self.hdmi_out0.driver.clocking.cd_pix.clk, self.hdmi_out0.driver.clocking.cd_pix5x.clk]: self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk) # hdmi in 1 if with_hdmi_in1: hdmi_in1_pads = platform.request("hdmi_in", 1) self.submodules.hdmi_in1_freq = FreqMeter(period=sys_clk_freq) self.submodules.hdmi_in1 = HDMIIn( hdmi_in1_pads, self.sdram.crossbar.get_port(mode="write"), fifo_depth=512, device="xc7", split_mmcm=True) self.comb += self.hdmi_in1_freq.clk.eq(self.hdmi_in1.clocking.cd_pix.clk), for clk in [self.hdmi_in1.clocking.cd_pix.clk, self.hdmi_in1.clocking.cd_pix1p25x.clk, self.hdmi_in1.clocking.cd_pix5x.clk]: self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk) self.platform.add_period_constraint(platform.lookup_request("hdmi_in", 1).clk_p, period_ns(148.5e6)) # hdmi out 1 if with_hdmi_out1: hdmi_out1_dram_port = self.sdram.crossbar.get_port(mode="read", dw=16, cd="hdmi_out1_pix", reverse=True) self.submodules.hdmi_out1 = VideoOut( platform.device, platform.request("hdmi_out", 1), hdmi_out1_dram_port, "ycbcr422", fifo_depth=4096) for clk in [self.hdmi_out1.driver.clocking.cd_pix.clk, self.hdmi_out1.driver.clocking.cd_pix5x.clk]: self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk) # led blinking (sys) sys_counter = Signal(32) self.sync.sys += sys_counter.eq(sys_counter + 1) self.comb += platform.request("user_led", 0).eq(sys_counter[26]) # led blinking (pcie) if with_pcie: pcie_counter = Signal(32) self.sync.pcie += pcie_counter.eq(pcie_counter + 1) self.comb += platform.request("user_led", 1).eq(pcie_counter[26]) # led blinking (sdcard) if with_sdcard: sd_counter = Signal(32) self.sync.sd += sd_counter.eq(sd_counter + 1) self.comb += platform.request("user_led", 1).eq(sd_counter[26])
def __init__(self, platform, core_config): platform.add_extension(get_pcie_ios(core_config["phy_lanes"])) for i in range(core_config["dma_channels"]): platform.add_extension(get_axi_dma_ios(i, core_config["phy_data_width"])) platform.add_extension(get_msi_irqs_ios(width=core_config["msi_irqs"])) sys_clk_freq = float(core_config.get("clk_freq", 125e6)) # SoCMini ---------------------------------------------------------------------------------- SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, csr_data_width = 32, csr_ordering = core_config.get("csr_ordering", "big"), ident = "LitePCIe standalone core", ident_version = True ) # CRG -------------------------------------------------------------------------------------- clk_external = core_config.get("clk_external", False) self.submodules.crg = LitePCIeCRG(platform, sys_clk_freq, clk_external) # PCIe PHY --------------------------------------------------------------------------------- self.submodules.pcie_phy = core_config["phy"](platform, platform.request("pcie"), pcie_data_width = core_config.get("phy_pcie_data_width", 64), data_width = core_config["phy_data_width"], bar0_size = core_config["phy_bar0_size"]) # PCIe Endpoint ---------------------------------------------------------------------------- self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, endianness=core_config["endianness"]) # PCIe Wishbone Master --------------------------------------------------------------------- pcie_wishbone_master = LitePCIeWishboneMaster(self.pcie_endpoint, qword_aligned=core_config["qword_aligned"]) self.submodules += pcie_wishbone_master self.add_wb_master(pcie_wishbone_master.wishbone) # PCIe MMAP Master ------------------------------------------------------------------------- if core_config.get("mmap", False): mmap_base = core_config["mmap_base"] mmap_size = core_config["mmap_size"] mmap_translation = core_config.get("mmap_translation", 0x00000000) wb = wishbone.Interface(data_width=32) self.mem_map["mmap"] = mmap_base self.add_wb_slave(mmap_base, wb, mmap_size) self.add_memory_region("mmap", mmap_base, mmap_size, type="io") axi = AXILiteInterface(data_width=32, address_width=32) wb2axi = Wishbone2AXILite(wb, axi, base_address=-mmap_translation) self.submodules += wb2axi platform.add_extension(axi.get_ios("mmap_axi_lite")) axi_pads = platform.request("mmap_axi_lite") self.comb += axi.connect_to_pads(axi_pads, mode="master") # PCIe MMAP Slave -------------------------------------------------------------------------- if core_config.get("mmap_slave", False): # AXI-Full if core_config.get("mmap_slave_axi_full", False): pcie_axi_slave = LitePCIeAXISlave(self.pcie_endpoint, data_width=128) self.submodules += pcie_axi_slave platform.add_extension(pcie_axi_slave.axi.get_ios("mmap_slave_axi")) axi_pads = platform.request("mmap_slave_axi") self.comb += pcie_axi_slave.axi.connect_to_pads(axi_pads, mode="slave") # AXI-Lite else: platform.add_extension(axi.get_ios("mmap_slave_axi_lite")) axi_pads = platform.request("mmap_slave_axi_lite") wb = wishbone.Interface(data_width=32) axi = AXILiteInterface(data_width=32, address_width=32) self.comb += axi.connect_to_pads(axi_pads, mode="slave") axi2wb = AXILite2Wishbone(axi, wb) self.submodules += axi2wb pcie_wishbone_slave = LitePCIeWishboneSlave(self.pcie_endpoint, qword_aligned=core_config["qword_aligned"]) self.submodules += pcie_wishbone_slave self.comb += wb.connect(pcie_wishbone_slave.wishbone) # PCIe DMA --------------------------------------------------------------------------------- pcie_dmas = [] self.add_constant("DMA_CHANNELS", core_config["dma_channels"]) for i in range(core_config["dma_channels"]): pcie_dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering = core_config["dma_buffering"] != 0, buffering_depth = core_config["dma_buffering"], with_loopback = core_config["dma_loopback"], with_synchronizer = core_config["dma_synchronizer"], with_monitor = core_config["dma_monitor"]) pcie_dma = stream.BufferizeEndpoints({"sink" : stream.DIR_SINK})(pcie_dma) pcie_dma = stream.BufferizeEndpoints({"source" : stream.DIR_SOURCE})(pcie_dma) setattr(self.submodules, "pcie_dma" + str(i), pcie_dma) self.add_csr("pcie_dma{}".format(i)) dma_writer_ios = platform.request("dma{}_writer_axi".format(i)) dma_reader_ios = platform.request("dma{}_reader_axi".format(i)) self.comb += [ # Writer IOs pcie_dma.sink.valid.eq(dma_writer_ios.tvalid), dma_writer_ios.tready.eq(pcie_dma.sink.ready), pcie_dma.sink.last.eq(dma_writer_ios.tlast), pcie_dma.sink.data.eq(dma_writer_ios.tdata), pcie_dma.sink.first.eq(dma_writer_ios.tuser), # Reader IOs dma_reader_ios.tvalid.eq(pcie_dma.source.valid), pcie_dma.source.ready.eq(dma_reader_ios.tready), dma_reader_ios.tlast.eq(pcie_dma.source.last), dma_reader_ios.tdata.eq(pcie_dma.source.data), dma_reader_ios.tuser.eq(pcie_dma.source.first), ] # PCIe MSI --------------------------------------------------------------------------------- if core_config.get("msi_x", False): assert core_config["msi_irqs"] <= 32 self.submodules.pcie_msi = LitePCIeMSIX(self.pcie_endpoint, width=64) self.comb += self.pcie_msi.irqs[32:32+core_config["msi_irqs"]].eq(platform.request("msi_irqs")) else: assert core_config["msi_irqs"] <= 16 if core_config.get("msi_multivector", False): self.submodules.pcie_msi = LitePCIeMSIMultiVector(width=32) else: self.submodules.pcie_msi = LitePCIeMSI(width=32) self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.comb += self.pcie_msi.irqs[16:16+core_config["msi_irqs"]].eq(platform.request("msi_irqs")) self.interrupts = {} for i in range(core_config["dma_channels"]): self.interrupts["pcie_dma" + str(i) + "_writer"] = getattr(self, "pcie_dma" + str(i)).writer.irq self.interrupts["pcie_dma" + str(i) + "_reader"] = getattr(self, "pcie_dma" + str(i)).reader.irq for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k.upper() + "_INTERRUPT", i) assert len(self.interrupts.keys()) <= 16
def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, **kwargs): platform = alveo_u250.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Alveo U250", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR4 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = usddrphy.USPDDRPHY( platform.request("ddram"), memtype="DDR4", sys_clk_freq=sys_clk_freq, iodelay_clk_freq=500e6, cmd_latency=1, is_rdimm=True) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MTA18ASF2G72PZ(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Firmware RAM (To ease initial LiteDRAM calibration support) ------------------------------ self.add_ram("firmware_ram", 0x20000000, 0x8000) # PCIe ------------------------------------------------------------------------------------- if with_pcie: # PHY self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"), data_width=128, bar0_size=0x20000) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") # Endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint( self.pcie_phy, max_pending_requests=8) # Wishbone bridge self.submodules.pcie_bridge = LitePCIeWishboneBridge( self.pcie_endpoint, base_address=self.mem_map["csr"]) self.add_wb_master(self.pcie_bridge.wishbone) # DMA0 self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering=True, buffering_depth=1024, with_loopback=True) self.add_csr("pcie_dma0") self.add_constant("DMA_CHANNELS", 1) # MSI self.submodules.pcie_msi = LitePCIeMSI() self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, "PCIE_DMA0_READER": self.pcie_dma0.reader.irq, } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, platform, **kwargs): sys_clk_freq = int(100e6) # SoCCore --------------------_------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Nereid", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) self.add_csr("crg") # DNA -------------------------------------------------------------------------------------- self.submodules.dna = dna.DNA() self.add_csr("dna") # XADC ------------------------------------------------------------------------------------- self.submodules.xadc = xadc.XADC() self.add_csr("xadc") # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.K7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq, iodelay_clk_freq=200e6) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT8KTF51264(sys_clk_freq, "1:4", speedgrade="800"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # PCIe ------------------------------------------------------------------------------------- # pcie phy self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") # pcie endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) # pcie wishbone bridge self.submodules.pcie_wishbone = LitePCIeWishboneBridge( self.pcie_endpoint, lambda a: 1, base_address=self.mem_map["csr"]) self.add_wb_master(self.pcie_wishbone.wishbone) # pcie dma self.submodules.pcie_dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering=True, buffering_depth=1024, with_loopback=True) self.add_csr("pcie_dma") # pcie msi self.submodules.pcie_msi = LitePCIeMSI() self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.msis = { "DMA_WRITER": self.pcie_dma.writer.irq, "DMA_READER": self.pcie_dma.reader.irq } for i, (k, v) in enumerate(sorted(self.msis.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i)
def __init__(self, platform, with_cpu=True, with_sdram=True, with_etherbone=True, with_pcie=True, with_sdram_dmas=False, with_hdmi_in0=True, with_hdmi_out0=True): sys_clk_freq = int(100e6) # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__( self, platform, sys_clk_freq, cpu_type="vexriscv" if with_cpu else None, cpu_variant="lite", l2_size=128, csr_data_width=32, with_uart=with_cpu, uart_name="crossover", integrated_rom_size=0x8000 if with_cpu else 0x0000, integrated_main_ram_size=0x1000 if not with_sdram else 0x0000, ident="NeTV2 LiteX SoC", ident_version=True) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) self.add_csr("crg") # DNA -------------------------------------------------------------------------------------- self.submodules.dna = DNA() self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk) self.add_csr("dna") # XADC ------------------------------------------------------------------------------------- self.submodules.xadc = XADC() self.add_csr("xadc") # ICAP ------------------------------------------------------------------------------------- self.submodules.icap = ICAP(platform) self.icap.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk) self.add_csr("icap") # Flash ------------------------------------------------------------------------------------ self.submodules.flash = S7SPIFlash(platform.request("flash"), sys_clk_freq, 25e6) self.add_csr("flash") # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") sdram_module = K4B2G1646F(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, geom_settings=sdram_module.geom_settings, timing_settings=sdram_module.timing_settings) # Etherbone -------------------------------------------------------------------------------- if with_etherbone: # ethphy self.submodules.ethphy = LiteEthPHYRMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") # ethcore self.submodules.ethcore = LiteEthUDPIPCore( phy=self.ethphy, mac_address=0x10e2d5000000, ip_address="192.168.1.50", clk_freq=self.clk_freq) # etherbone self.submodules.etherbone = LiteEthEtherbone( self.ethcore.udp, 1234) self.add_wb_master(self.etherbone.wishbone.bus) # timing constraints self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9 / 50e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9 / 50e6) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk) # PCIe ------------------------------------------------------------------------------------- if with_pcie: # PHY ---------------------------------------------------------------------------------- self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), data_width=64, bar0_size=0x20000) platform.add_false_path_constraint(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") # Endpoint ----------------------------------------------------------------------------- self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) # Wishbone bridge ---------------------------------------------------------------------- self.submodules.pcie_bridge = LitePCIeWishboneBridge( self.pcie_endpoint, base_address=self.mem_map["csr"]) self.add_wb_master(self.pcie_bridge.wishbone) # DMA0 --------------------------------------------------------------------------------- self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering=True, buffering_depth=1024, with_loopback=True) self.add_csr("pcie_dma0") # DMA1 --------------------------------------------------------------------------------- self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering=True, buffering_depth=1024, with_loopback=True) self.add_csr("pcie_dma1") self.add_constant("DMA_CHANNELS", 2) # MSI ---------------------------------------------------------------------------------- self.submodules.pcie_msi = LitePCIeMSI() self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, "PCIE_DMA0_READER": self.pcie_dma0.reader.irq, "PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq, "PCIE_DMA1_READER": self.pcie_dma1.reader.irq, } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) # FIXME : Dummy counter capture, connect to HDMI In ------------------------------------ pcie_dma0_counter = Signal(32) self.sync += [ self.pcie_dma0.sink.valid.eq(1), If(self.pcie_dma0.sink.ready, pcie_dma0_counter.eq(pcie_dma0_counter + 1)), self.pcie_dma0.sink.data.eq(pcie_dma0_counter) ] pcie_dma1_counter = Signal(32) self.sync += [ self.pcie_dma1.sink.valid.eq(1), If(self.pcie_dma1.sink.ready, pcie_dma1_counter.eq(pcie_dma1_counter + 2)), self.pcie_dma1.sink.data.eq(pcie_dma1_counter) ] # SDRAM DMAs ------------------------------------------------------------------------------- if with_sdram_dmas: self.submodules.sdram_reader = LiteDRAMDMAReader( self.sdram.crossbar.get_port()) self.sdram_reader.add_csr() self.add_csr("sdram_reader") self.submodules.sdram_writer = LiteDRAMDMAReader( self.sdram.crossbar.get_port()) self.sdram_writer.add_csr() self.add_csr("sdram_writer") # HDMI In 0 -------------------------------------------------------------------------------- if with_hdmi_in0: hdmi_in0_pads = platform.request("hdmi_in", 0) self.submodules.hdmi_in0_freq = FreqMeter(period=sys_clk_freq) self.add_csr("hdmi_in0_freq") self.submodules.hdmi_in0 = HDMIIn( pads=hdmi_in0_pads, dram_port=self.sdram.crossbar.get_port(mode="write"), fifo_depth=512, device="xc7", split_mmcm=True) self.add_csr("hdmi_in0") self.add_csr("hdmi_in0_edid_mem") self.comb += self.hdmi_in0_freq.clk.eq( self.hdmi_in0.clocking.cd_pix.clk), platform.add_false_path_constraints( self.crg.cd_sys.clk, self.hdmi_in0.clocking.cd_pix.clk, self.hdmi_in0.clocking.cd_pix1p25x.clk, self.hdmi_in0.clocking.cd_pix5x.clk) self.platform.add_period_constraint( platform.lookup_request("hdmi_in", 0).clk_p, 1e9 / 74.25e6) # HDMI Out 0 ------------------------------------------------------------------------------- if with_hdmi_out0: self.submodules.hdmi_out0 = VideoOut( device=platform.device, pads=platform.request("hdmi_out", 0), dram_port=self.sdram.crossbar.get_port( mode="read", data_width=16, clock_domain="hdmi_out0_pix", reverse=True), mode="ycbcr422", fifo_depth=512) self.add_csr("hdmi_out0") platform.add_false_path_constraints( self.crg.cd_sys.clk, self.hdmi_out0.driver.clocking.cd_pix.clk, self.hdmi_out0.driver.clocking.cd_pix5x.clk)