def __init__(self, platform):
sys_clk_freq = int(100e6)
SoCCore.__init__(self, platform, sys_clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="Fast scope", ident_version=True,
with_timer=False
)
self.submodules.serdes = SerdesIO(platform)
# crg
self.submodules.crg = _CRG(platform,sys_clk_freq)
# bridge
bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq, baudrate=115200)
self.submodules.bridge = bridge
self.add_wb_master(bridge.wishbone)
# Litescope Analyzer
analyzer_groups = {}
# Analyzer group
analyzer_groups[0] = [
self.serdes.d0.signals,
self.serdes.d1.signals,
self.serdes.d2.signals,
self.serdes.d3.signals,
]
# analyzer
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_groups, 512)
def __init__(self, platform):
clk_freq = int((1/(platform.default_clk_period))*1000000000)
SoCCore.__init__(self, platform, clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="Litescope example design",
with_timer=False
)
self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
self.submodules.io = LiteScopeIO(8)
for i in range(8):
try:
self.comb += platform.request("user_led", i).eq(self.io.output[i])
except:
pass
counter = Signal(16)
self.sync += counter.eq(counter + 1)
toto = Signal()
self.submodules.analyzer = LiteScopeAnalyzer(counter, 512)
def __init__(self, platform):
from litescope import LiteScopeAnalyzer
BaseSoC.__init__(self, platform)
self.core_icmp_rx_fsm_state = Signal(4)
self.core_icmp_tx_fsm_state = Signal(4)
self.core_udp_rx_fsm_state = Signal(4)
self.core_udp_tx_fsm_state = Signal(4)
self.core_ip_rx_fsm_state = Signal(4)
self.core_ip_tx_fsm_state = Signal(4)
self.core_arp_rx_fsm_state = Signal(4)
self.core_arp_tx_fsm_state = Signal(4)
self.core_arp_table_fsm_state = Signal(4)
debug = [
# MAC interface
self.core.mac.core.sink.valid,
self.core.mac.core.sink.last,
self.core.mac.core.sink.ready,
self.core.mac.core.sink.data,
self.core.mac.core.source.valid,
self.core.mac.core.source.last,
self.core.mac.core.source.ready,
self.core.mac.core.source.data,
# ICMP interface
self.core.icmp.echo.sink.valid,
self.core.icmp.echo.sink.last,
self.core.icmp.echo.sink.ready,
self.core.icmp.echo.sink.data,
self.core.icmp.echo.source.valid,
self.core.icmp.echo.source.last,
self.core.icmp.echo.source.ready,
self.core.icmp.echo.source.data,
# IP interface
self.core.ip.crossbar.master.sink.valid,
self.core.ip.crossbar.master.sink.last,
self.core.ip.crossbar.master.sink.ready,
self.core.ip.crossbar.master.sink.data,
self.core.ip.crossbar.master.sink.ip_address,
self.core.ip.crossbar.master.sink.protocol,
# State machines
self.core_icmp_rx_fsm_state,
self.core_icmp_tx_fsm_state,
self.core_arp_rx_fsm_state,
self.core_arp_tx_fsm_state,
self.core_arp_table_fsm_state,
self.core_ip_rx_fsm_state,
self.core_ip_tx_fsm_state,
self.core_udp_rx_fsm_state,
self.core_udp_tx_fsm_state
]
self.submodules.analyzer = LiteScopeAnalyzer(debug, 4096)
def __init__(self, sys_clk_freq=int(100e6)):
platform = arty.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
cpu_type = "microwatt",
integrated_rom_size = 0x8000,
integrate_main_ram_size = 0x8000,
uart_name = "stub")
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# Bridge -----------------------------------------------------------------------------------
self.submodules.bridge = UARTWishboneBridge(
pads = self.platform.request("serial"),
clk_freq = sys_clk_freq,
baudrate = 115200)
self.bus.add_master("bridge", master=self.bridge.wishbone)
# LiteScope --------------------------------------------------------------------------------
analyzer_signals = [
self.cpu.reset,
self.cpu.wb_insn,
self.cpu.wb_data,
]
from litescope import LiteScopeAnalyzer
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth = 512,
clock_domain = "sys",
csr_csv = "analyzer.csv")
self.add_csr("analyzer")
def __init__(self, sys_clk_freq, output_dir, *args, **kwargs):
self._logger = logging.getLogger("ZephyrSoC")
super().__init__(
cpu_type="vexriscv",
cpu_variant="full",
csr_data_width=8,
integrated_rom_size=0x8000,
*args,
**kwargs,
) # TODO: Test if we actually need "full" for ecall
self.submodules.gpio_leds = GPIOOut(self.platform.request("gpio_leds"))
self.add_csr("gpio_leds")
self.submodules.switches = GPIOIn(self.platform.request_all("sw"))
self.add_csr("switches")
self.platform.add_extension(pmod1_uart_ios)
self.add_uartbone(name="pmod1_uart")
analyzer_signals = [self.cpu.ibus, self.cpu.dbus]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals,
depth=512,
clock_domain="sys",
csr_csv=os.path.join(output_dir, "analyzer.csv"),
)
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, with_uart=False, **kwargs)
# Memory test BIST
self.submodules.generator = LiteDRAMBISTGenerator(
self.sdram.crossbar.get_port(mode="write", data_width=32))
self.submodules.checker = LiteDRAMBISTChecker(
self.sdram.crossbar.get_port(mode="read", data_width=32))
self.submodules.checker_scope = LiteDRAMBISTCheckerScope(self.checker)
# Litescope for analyzing the BIST output
# --------------------
# Dummy UART
self.submodules.suart = shared_uart.SharedUART(self.clk_freq, 115200)
self.submodules.uart = self.suart.uart
self.submodules.uartbridge = UARTWishboneBridge(
platform.request("serial"), self.clk_freq, baudrate=19200)
self.add_wb_master(self.uartbridge.wishbone)
# self.submodules.io = LiteScopeIO(8)
# for i in range(8):
# try:
# self.comb += platform.request("user_led", i).eq(self.io.output[i])
# except:
# pass
analyzer_signals = self.checker_scope.signals()
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 64)
def __init__(self, platform):
EtherboneSoC.__init__(self, platform)
pmoda = platform.request("pmoda")
# use name override to keep naming in capture
pmoda_0 = Signal(name_override="pmoda_0")
pmoda_1 = Signal(name_override="pmoda_1")
pmoda_2 = Signal(name_override="pmoda_2")
pmoda_3 = Signal(name_override="pmoda_3")
pmoda_4 = Signal(name_override="pmoda_4")
pmoda_5 = Signal(name_override="pmoda_5")
pmoda_6 = Signal(name_override="pmoda_6")
pmoda_7 = Signal(name_override="pmoda_7")
# deglitch with multireg
self.specials += [
MultiReg(pmoda[0], pmoda_0),
MultiReg(pmoda[1], pmoda_1),
MultiReg(pmoda[2], pmoda_2),
MultiReg(pmoda[3], pmoda_3),
MultiReg(pmoda[4], pmoda_4),
MultiReg(pmoda[5], pmoda_5),
MultiReg(pmoda[6], pmoda_6),
MultiReg(pmoda[7], pmoda_7)
]
analyzer_signals = [
pmoda_0, pmoda_1, pmoda_2, pmoda_3, pmoda_4, pmoda_5, pmoda_6,
pmoda_7
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 8192)
def __init__(self,
uart="crossover",
sys_clk_freq=int(125e6),
with_bist=False,
with_analyzer=False):
platform = kc705.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
ident="LiteDRAM bench on KC705",
ident_version=True,
integrated_rom_size=0x10000,
integrated_rom_mode="rw",
uart_name=uart)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(pads=PHYPadsReducer(
platform.request("ddram"), [0, 1, 2, 3, 4, 5, 6, 7]),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT8JTF12864(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
with_bist=with_bist)
# UARTBone ---------------------------------------------------------------------------------
if uart != "serial":
self.add_uartbone(name="serial",
clk_freq=100e6,
baudrate=115200,
cd="uart")
# Etherbone --------------------------------------------------------------------------------
self.submodules.ethphy = LiteEthPHY(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
clk_freq=self.clk_freq)
self.add_etherbone(phy=self.ethphy)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
from litescope import LiteScopeAnalyzer
analyzer_signals = [self.ddrphy.dfi]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals,
depth=256,
clock_domain="sys",
csr_csv="analyzer.csv")
# Leds -------------------------------------------------------------------------------------
from litex.soc.cores.led import LedChaser
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self, platform, *args, **kwargs):
kwargs['cpu_type'] = None
BaseSoC.__init__(self, platform, *args, with_uart=False, **kwargs)
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
self.clk_freq,
baudrate=19200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
# Litescope for analyzing the BIST output
# --------------------
self.submodules.io = LiteScopeIO(8)
for i in range(8):
try:
self.comb += platform.request("user_led",
i).eq(self.io.output[i])
except:
pass
analyzer_signals = [
self.spiflash.bus,
# self.spiflash.cs_n,
# self.spiflash.clk,
# self.spiflash.dq_oe,
# self.spiflash.dqi,
# self.spiflash.sr,
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 1024)
def __init__(self,
sys_clk_freq=int(50e6),
x5_clk_freq=None,
toolchain="trellis",
**kwargs):
platform = ecp5_evn.Platform(toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_main_ram_size=0x8000,
**kwargs)
# CRG --------------------------------------------------------------------------------------
crg = _CRG(platform, sys_clk_freq, x5_clk_freq)
self.submodules.crg = crg
# HyperRam ---------------------------------------------------------------------------------
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.add_wb_slave(self.mem_map["hyperram"], self.hyperram.bus)
self.add_memory_region("hyperram", self.mem_map["hyperram"],
8 * 1024 * 1024)
# ADC --------------------------------------------------------------------------------------
trig_pad = platform.request("adc_trig", 0)
self.submodules.adc = ADC3321_DMA(trig_pad)
self.add_wb_master(self.adc.wishbone)
self.add_csr("adc")
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads=Cat(*[platform.request("user_led", i) for i in range(8)]),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
# Wishbone Debug
# added io to platform, serial_wb
self.submodules.bridge = UARTWishboneBridge(platform.request(
"serial_wb", 1),
sys_clk_freq,
baudrate=115200)
self.add_wb_master(self.bridge.wishbone)
self.add_csr("analyzer")
analyzer_signals = [
trig_pad,
# self.adc.wishbone.stb,
# self.adc.wishbone.dat_w,
# self.adc.wishbone.ack,
# self.adc.wishbone.adr,
]
analyzer_depth = 256 # samples
analyzer_clock_domain = "sys"
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals,
analyzer_depth,
clock_domain=analyzer_clock_domain)
def __init__(self, uart="crossover", sys_clk_freq=int(125e6), with_bist=False, with_analyzer=False):
platform = kcu105.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
ident = "LiteDRAM bench on KCU105",
ident_version = True,
integrated_rom_size = 0x10000,
integrated_rom_mode = "rw",
csr_data_width = 32,
uart_name = uart)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.add_csr("crg")
# DDR4 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
memtype = "DDR4",
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 200e6)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = EDY4016A(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"],
size = 0x40000000,
with_bist = with_bist,
)
# UARTBone ---------------------------------------------------------------------------------
if uart != "serial":
self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")
# Etherbone --------------------------------------------------------------------------------
self.submodules.ethphy = KU_1000BASEX(self.crg.cd_eth.clk,
data_pads = self.platform.request("sfp", 0),
sys_clk_freq = self.clk_freq)
self.add_csr("ethphy")
self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
self.platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]")
self.add_etherbone(phy=self.ethphy)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
from litescope import LiteScopeAnalyzer
analyzer_signals = [self.ddrphy.dfi]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth = 256,
clock_domain = "sys",
csr_csv = "analyzer.csv")
self.add_csr("analyzer")
# Leds -------------------------------------------------------------------------------------
from litex.soc.cores.led import LedChaser
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
def __init__(self,
uart="crossover",
sys_clk_freq=int(125e6),
channel=0,
with_bist=False,
with_analyzer=False):
platform = xcu1525.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
ident="LiteDRAM bench on XCU1525",
ident_version=True,
integrated_rom_size=0x10000,
integrated_rom_mode="rw",
uart_name=uart)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, channel)
# DDR4 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request(
"ddram", channel),
memtype="DDR4",
sys_clk_freq=sys_clk_freq,
iodelay_clk_freq=500e6)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT40A512M8(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=0x40000000,
with_bist=with_bist)
# Workaround for Vivado 2018.2 DRC, can be ignored and probably fixed on newer Vivado versions.
platform.add_platform_command(
"set_property SEVERITY {{Warning}} [get_drc_checks PDCN-2736]")
# UARTBone ---------------------------------------------------------------------------------
if uart != "serial":
self.add_uartbone(name="serial",
clk_freq=100e6,
baudrate=115200,
cd="uart")
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
from litescope import LiteScopeAnalyzer
analyzer_signals = [self.ddrphy.dfi]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals,
depth=256,
clock_domain="sys",
csr_csv="analyzer.csv")
# Leds -------------------------------------------------------------------------------------
from litex.soc.cores.led import LedChaser
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self, platform, **kwargs):
base_cls.__init__(self, platform, **kwargs)
# hdmi out 0
dram_port = self.sdram.crossbar.get_port(mode="read",
dw=16,
cd="pix",
reverse=True)
self.submodules.hdmi_out0 = VideoOut(platform.device,
platform.request("hdmi_out", 0),
dram_port,
mode="ycbcr422",
fifo_depth=4096)
# all PLL_ADV are used: router needs help...
platform.add_platform_command("""INST PLL_ADV LOC=PLL_ADV_X0Y0;""")
# FIXME: Fix the HDMI out so this can be removed.
platform.add_platform_command(
"""PIN "hdmi_out_pix_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;""")
platform.add_platform_command(
"""
NET "{pix0_clk}" TNM_NET = "GRPpix0_clk";
""",
pix0_clk=self.hdmi_out0.driver.clocking.cd_pix.clk)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_out0.driver.clocking.cd_pix.clk)
analyzer_signals = [
#self.hdmi_out0.core.timing.hactive,
#self.hdmi_out0.core.timing.vactive,
#self.hdmi_out0.core.timing.active,
#self.hdmi_out0.core.timing.hcounter,
#self.hdmi_out0.core.timing.vcounter,
self.hdmi_out0.core.timing.sink.valid,
self.hdmi_out0.core.timing.sink.ready,
self.hdmi_out0.core.timing.source.valid,
self.hdmi_out0.core.timing.source.ready,
#self.hdmi_out0.core.dma.offset,
self.hdmi_out0.core.dma.sink.valid,
self.hdmi_out0.core.dma.sink.ready,
self.hdmi_out0.core.dma.source.valid,
self.hdmi_out0.core.dma.source.ready,
dram_port.counter,
dram_port.rdata_chunk,
dram_port.cmd_buffer.sink.valid,
dram_port.cmd_buffer.sink.ready,
dram_port.cmd_buffer.source.valid,
dram_port.cmd_buffer.source.ready,
dram_port.rdata_buffer.sink.valid,
dram_port.rdata_buffer.sink.ready,
dram_port.rdata_buffer.source.valid,
dram_port.rdata_buffer.source.ready,
dram_port.rdata_converter.sink.valid,
dram_port.rdata_converter.sink.ready,
dram_port.rdata_converter.source.valid,
dram_port.rdata_converter.source.ready,
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 1024)
def __init__(self,
sys_clk_freq=int(250e6),
with_hbm=False,
with_analyzer=False,
**kwargs):
platform = Platform()
# SoCCore ----------------------------------------------------------------------------------
kwargs["uart_name"] = "crossover"
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX HBM2 Test SoC on Forest Kitten 33.",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# JTAGBone --------------------------------------------------------------------------------
self.add_jtagbone(
chain=2) # Chain 1 already used by HBM2 debug probes.
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads=Cat(*[platform.request("user_led", i) for i in range(7)]),
sys_clk_freq=sys_clk_freq)
# HBM --------------------------------------------------------------------------------------
if with_hbm:
# Add HBM Core.
self.submodules.hbm = hbm = ClockDomainsRenamer({"axi": "sys"})(
HBMIP(platform))
# Connect four of the HBM's AXI interfaces to the main bus of the SoC.
for i in range(4):
axi_hbm = hbm.axi[i]
axi_lite_hbm = AXILiteInterface(data_width=256,
address_width=33)
self.submodules += AXILite2AXI(axi_lite_hbm, axi_hbm)
self.bus.add_slave(f"hbm{i}", axi_lite_hbm,
SoCRegion(origin=0x4000_0000 +
0x1000_0000 * i,
size=0x1000_0000)) # 256MB.
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [
Signal(2), # Add useful signals.
Signal(2), # Add useful signals.
]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals,
depth=2048,
clock_domain="sys",
csr_csv="analyzer.csv")
def __init__(self, uart="crossover", sys_clk_freq=int(125e6)):
platform = genesys2.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
integrated_rom_mode="rw",
csr_data_width=32,
uart_name=uart)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.add_csr("crg")
# DDR3 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41J256M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"])
# UARTBone ---------------------------------------------------------------------------------
if uart != "serial":
self.add_uartbone(name="serial",
clk_freq=100e6,
baudrate=115200,
cd="uart")
# Etherbone --------------------------------------------------------------------------------
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
with_hw_init_reset=False)
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy)
# Analyzer ---------------------------------------------------------------------------------
from litescope import LiteScopeAnalyzer
analyzer_signals = [self.ddrphy.dfi]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth=512,
clock_domain="sys",
csr_csv="analyzer.csv")
self.add_csr("analyzer")
# Leds -------------------------------------------------------------------------------------
from litex.soc.cores.led import LedChaser
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self, platform):
sys_clk_freq = int((1e9 / platform.default_clk_period))
SoCCore.__init__(self,
platform,
sys_clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="Litescope example design",
ident_version=True,
with_timer=False)
# crg
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
# bridge
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
sys_clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
# Litescope IO
self.submodules.io = LiteScopeIO(8)
for i in range(8):
try:
self.comb += platform.request("user_led",
i).eq(self.io.output[i])
except:
pass
# Litescope Analyzer
analyzer_groups = {}
# counter group
counter = Signal(16, name_override="counter")
zero = Signal(name_override="zero")
self.sync += counter.eq(counter + 1)
self.comb += zero.eq(counter == 0)
analyzer_groups[0] = [zero, counter]
# communication group
analyzer_groups[1] = [
platform.lookup_request("serial").tx,
platform.lookup_request("serial").rx, self.cpu_or_bridge.wishbone
]
# fsm group
fsm = FSM(reset_state="STATE1")
self.submodules += fsm
fsm.act("STATE1", NextState("STATE2"))
fsm.act("STATE2", NextState("STATE1"))
analyzer_groups[2] = [fsm]
# analyzer
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_groups, 512)
def __init__(self, platform):
from litescope import LiteScopeAnalyzer
StreamSoC.__init__(self, platform)
analyzer_signals = [
self.streamer.sink.valid, self.streamer.sink.ready,
self.streamer.sink.data, self.streamer.source.valid,
self.streamer.source.ready, self.streamer.source.data
]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals, 4096, csr_csv="test/analyzer.csv")
self.add_csr("analyzer")
def __init__(self, platform):
from litescope import LiteScopeAnalyzer
TTYSoC.__init__(self, platform)
debug = [
self.tty.sink.valid,
self.tty.sink.ready,
self.tty.sink.data,
self.tty.source.valid,
self.tty.source.ready,
self.tty.source.data
]
self.submodules.analyzer = LiteScopeAnalyzer(debug, 4096)
def __init__(self, platform, with_analyzer=False):
clk_freq = int(125e6)
SoCCore.__init__(
self,
platform,
clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="Sayma RTM / AMC <--> RTM SERWB Link Test Design ",
ident_version=True,
with_timer=False)
self.submodules.crg = _CRG(platform)
# uart <--> wishbone
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
# amc rtm link
serwb_phy = SERWBPHY(platform.device,
platform.request("serwb"),
mode="slave")
platform.add_period_constraint(
platform.lookup_request("serwb").clk_p, 10.)
self.submodules.serwb_phy = serwb_phy
self.comb += self.crg.serwb_refclk.eq(serwb_phy.serdes.clocking.refclk)
# wishbone master
serwb_core = SERWBCore(serwb_phy, clk_freq, mode="master")
self.submodules += serwb_core
self.add_wb_master(serwb_core.etherbone.wishbone.bus)
# wishbone test memory
self.submodules.serwb_sram = wishbone.SRAM(
8192, init=[i for i in range(8192 // 4)])
self.register_mem("serwb_sram", self.mem_map["serwb"],
self.serwb_sram.bus, 8192)
if with_analyzer:
activity = Signal()
self.comb += activity.eq(serwb_phy.serdes.decoders[0].d != 0)
analyzer_signals = [
activity, serwb_core.etherbone.wishbone.bus,
serwb_phy.serdes.rx_ce, serwb_phy.serdes.rx_k,
serwb_phy.serdes.rx_d, serwb_phy.serdes.tx_ce,
serwb_phy.serdes.tx_k, serwb_phy.serdes.tx_d
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 256)
def __init__(self, platform):
from litescope import LiteScopeAnalyzer
UDPSoC.__init__(self, platform)
debug = [
self.loopback_8.sink.valid, self.loopback_8.sink.last,
self.loopback_8.sink.ready, self.loopback_8.sink.data,
self.loopback_8.source.valid, self.loopback_8.source.last,
self.loopback_8.source.ready, self.loopback_8.source.data,
self.loopback_32.sink.valid, self.loopback_32.sink.last,
self.loopback_32.sink.ready, self.loopback_32.sink.data,
self.loopback_32.source.valid, self.loopback_32.source.last,
self.loopback_32.source.ready, self.loopback_32.source.data
]
self.submodules.analyzer = LiteScopeAnalyzer(debug, 4096)
def __init__(self, **kwargs):
from litescope import LiteScopeAnalyzer
HelloETH.__init__(self, **kwargs)
p = self.platform
self.submodules.blink_rx = ClockDomainsRenamer("eth_rx")(
LedBlinker(125e6))
self.submodules.blink_tx = ClockDomainsRenamer("eth_tx")(
LedBlinker(125e6))
self.submodules.f_tx = FrequencyMeter(int(100e6))
self.comb += [
p.request("user_led").eq(self.blink_rx.out),
p.request("user_led").eq(self.blink_tx.out),
self.f_tx.clk.eq(ClockSignal("eth_tx"))
]
debug = [
p.lookup_request("eth").tx_en,
p.lookup_request("eth").tx_er,
p.lookup_request("eth").tx_data,
p.lookup_request("eth").mdc,
# MAC interface
self.core.mac.core.sink.valid,
self.core.mac.core.sink.last,
self.core.mac.core.sink.ready,
self.core.mac.core.sink.data,
self.core.mac.core.source.valid,
self.core.mac.core.source.last,
self.core.mac.core.source.ready,
self.core.mac.core.source.data,
# ICMP interface
self.core.icmp.echo.sink.valid,
self.core.icmp.echo.sink.last,
self.core.icmp.echo.sink.ready,
self.core.icmp.echo.sink.data,
self.core.icmp.echo.source.valid,
self.core.icmp.echo.source.last,
self.core.icmp.echo.source.ready,
self.core.icmp.echo.source.data,
# IP interface
self.core.ip.crossbar.master.sink.valid,
self.core.ip.crossbar.master.sink.last,
self.core.ip.crossbar.master.sink.ready,
self.core.ip.crossbar.master.sink.data,
self.core.ip.crossbar.master.sink.ip_address,
self.core.ip.crossbar.master.sink.protocol
]
self.submodules.analyzer = LiteScopeAnalyzer(debug, 4096)
def __init__(self, platform):
from litescope import LiteScopeAnalyzer
BaseSoC.__init__(self, platform)
analyzer_signals = [
# MAC interface
self.ethcore.mac.core.sink.valid,
self.ethcore.mac.core.sink.last,
self.ethcore.mac.core.sink.ready,
self.ethcore.mac.core.sink.data,
self.ethcore.mac.core.source.valid,
self.ethcore.mac.core.source.last,
self.ethcore.mac.core.source.ready,
self.ethcore.mac.core.source.data,
# ICMP interface
self.ethcore.icmp.echo.sink.valid,
self.ethcore.icmp.echo.sink.last,
self.ethcore.icmp.echo.sink.ready,
self.ethcore.icmp.echo.sink.data,
self.ethcore.icmp.echo.source.valid,
self.ethcore.icmp.echo.source.last,
self.ethcore.icmp.echo.source.ready,
self.ethcore.icmp.echo.source.data,
# IP interface
self.ethcore.ip.crossbar.master.sink.valid,
self.ethcore.ip.crossbar.master.sink.last,
self.ethcore.ip.crossbar.master.sink.ready,
self.ethcore.ip.crossbar.master.sink.data,
self.ethcore.ip.crossbar.master.sink.ip_address,
self.ethcore.ip.crossbar.master.sink.protocol,
# State machines
self.ethcore.icmp.rx.fsm,
self.ethcore.icmp.tx.fsm,
self.ethcore.arp.rx.fsm,
self.ethcore.arp.tx.fsm,
self.ethcore.arp.table.fsm,
self.ethcore.ip.rx.fsm,
self.ethcore.ip.tx.fsm,
self.ethcore.udp.rx.fsm,
self.ethcore.udp.tx.fsm
]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals, 4096, csr_csv="test/analyzer.csv")
self.add_csr("analyzer")
def __init__(self, platform):
from litescope import LiteScopeAnalyzer
BISTSoC.__init__(self, platform)
self.sata_core_link_rx_fsm_state = Signal(4)
self.sata_core_link_tx_fsm_state = Signal(4)
self.sata_core_transport_rx_fsm_state = Signal(4)
self.sata_core_transport_tx_fsm_state = Signal(4)
self.sata_core_command_rx_fsm_state = Signal(4)
self.sata_core_command_tx_fsm_state = Signal(4)
debug = [
self.sata_phy.ctrl.ready,
self.sata_phy.source.valid,
self.sata_phy.source.data,
self.sata_phy.source.charisk,
self.sata_phy.sink.valid,
self.sata_phy.sink.data,
self.sata_phy.sink.charisk,
self.sata_core.command.sink.valid,
self.sata_core.command.sink.last,
self.sata_core.command.sink.ready,
self.sata_core.command.sink.write,
self.sata_core.command.sink.read,
self.sata_core.command.sink.identify,
self.sata_core.command.source.valid,
self.sata_core.command.source.last,
self.sata_core.command.source.ready,
self.sata_core.command.source.write,
self.sata_core.command.source.read,
self.sata_core.command.source.identify,
self.sata_core.command.source.failed,
self.sata_core.command.source.data,
self.sata_core_link_rx_fsm_state,
self.sata_core_link_tx_fsm_state,
self.sata_core_transport_rx_fsm_state,
self.sata_core_transport_tx_fsm_state,
self.sata_core_command_rx_fsm_state,
self.sata_core_command_tx_fsm_state,
]
self.submodules.analyzer = LiteScopeAnalyzer(debug, 2048)
def __init__(self, toolchain="trellis"):
platform = logicbone.Platform(toolchain=toolchain, device="85F")
sys_clk_freq = int(75e6)
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
cpu_type=None,
l2_size=32,
with_uart=None,
csr_data_width=32,
ident="Logicbone test SoC",
ident_version=True)
#self.comb += platform.request("rst_n").eq(1)
# crg
crg = DDR3TestCRG(platform, sys_clk_freq)
self.submodules.crg = crg
# uart
self.submodules.bridge = UARTWishboneBridge(platform.request("serial"),
sys_clk_freq,
baudrate=115200)
self.add_wb_master(self.bridge.wishbone)
# sdram
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.comb += crg.stop.eq(self.ddrphy.init.stop)
sdram_module = MT41K512M8(sys_clk_freq, "1:2")
#sdram_module = AS4C1GM8(sys_clk_freq, "1:2")
self.register_sdram(self.ddrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
# led blinking
led_counter = Signal(32)
self.sync += led_counter.eq(led_counter + 1)
self.comb += platform.request("user_led", 0).eq(led_counter[26])
# analyzer
analyzer_signals = [
self.ddrphy.dfi.p0,
self.ddrphy.datavalid,
#self.ddrphy.burstdet
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 128)
def __init__(self, platform):
clk_freq = int((1 / (platform.default_clk_period)) * 1000000000)
SoCCore.__init__(self,
platform,
clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="Litescope example design",
with_timer=False)
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
self.submodules.io = LiteScopeIO(8)
for i in range(8):
try:
self.comb += platform.request("user_led",
i).eq(self.io.output[i])
except:
pass
# use name override to keep naming in capture
counter = Signal(4, name_override="counter")
counter0 = Signal(name_override="counter0")
counter1 = Signal(name_override="counter1")
counter2 = Signal(name_override="counter2")
counter3 = Signal(name_override="counter3")
self.sync += counter.eq(counter + 1)
self.comb += [
counter0.eq(counter[0]),
counter1.eq(counter[1]),
counter2.eq(counter[2]),
counter3.eq(counter[3]),
]
# group for vcd capture
vcd_group = [counter]
# group for sigrok capture (no bus support)
sigrok_group = [counter0, counter1, counter2, counter3]
analyzer_signals = {0: vcd_group, 1: sigrok_group}
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)
def __init__(self, platform, clk_freq=100*1000000):
self.clock_domains.cd_sys = ClockDomain("sys")
self.comb += [
self.cd_sys.clk.eq(platform.request("sys_clock")),
self.cd_sys.rst.eq(platform.request("sys_reset"))
]
SoCCore.__init__(self, platform, clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="Litescope example design",
with_timer=False
)
self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
self.add_wb_master(self.cpu.wishbone)
self.bus = platform.request("bus")
self.submodules.analyzer = LiteScopeAnalyzer((self.bus), 512)
def __init__(self):
self.platform = platform = FireSensePlatform()
sys_clk_freq = int(150e6)
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
cpu_type=None,
with_uart=False,
csr_data_width=32,
ident="Versa ECP5 test SoC",
ident_version=True)
# crg
self.submodules.crg = _CRG(platform, sys_clk_freq)
# uart
self.submodules.bridge = UARTWishboneBridge(platform.request("serial"),
sys_clk_freq,
baudrate=1000000)
self.add_wb_master(self.bridge.wishbone)
# ethernet phy
ethphy = LiteEthPHYRGMII(platform.request("eth_clocks"),
platform.request("eth"))
ethcore = LiteEthUDPIPCore(ethphy,
mac_address=0x10e2d5000000,
ip_address=convert_ip("192.168.1.50"),
clk_freq=sys_clk_freq,
with_icmp=False)
self.submodules += ethphy, ethcore
# led blinking
led_counter = Signal(32)
self.sync += led_counter.eq(led_counter + 1)
self.comb += platform.request("user_led", 0).eq(led_counter[25])
# analyzer
analyzer_signals = [
# ethphy.sink,
ethcore.mac.core.crc32_checker.source
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 128,
"eth_rx")
def __init__(self, platform):
from litescope import LiteScopeAnalyzer
BISTSoC.__init__(self, platform)
analyzer_signals = [
self.sata_phy.ctrl.ready,
self.sata_phy.source,
self.sata_phy.sink,
self.sata_core.command.sink,
self.sata_core.command.source,
self.sata_core.link.rx.fsm,
self.sata_core.link.tx.fsm,
self.sata_core.transport.rx.fsm,
self.sata_core.transport.tx.fsm,
self.sata_core.command.rx.fsm,
self.sata_core.command.tx.fsm,
]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals, 2048, csr_csv="test/analyzer.csv")
self.add_csr("analyzer")
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, **kwargs)
# # #
pix_freq = 148.50e6
# analyzer
from litex.soc.cores.uart import UARTWishboneBridge
from litescope import LiteScopeAnalyzer
self.submodules.bridge = UARTWishboneBridge(
platform.request("serial_litescope"), self.clk_freq, baudrate=115200)
self.add_wb_master(self.bridge.wishbone)
analyzer_signals = [
self.sys_led,
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 2048, cd="clk200", cd_ratio=2)
def __init__(self, platform):
from litescope import LiteScopeAnalyzer
StripingSoC.__init__(self, platform)
self.sata_core0_link_tx_fsm_state = Signal(4)
self.sata_core0_link_rx_fsm_state = Signal(4)
self.sata_core1_link_tx_fsm_state = Signal(4)
self.sata_core1_link_rx_fsm_state = Signal(4)
self.sata_core2_link_tx_fsm_state = Signal(4)
self.sata_core2_link_rx_fsm_state = Signal(4)
self.sata_core3_link_tx_fsm_state = Signal(4)
self.sata_core3_link_rx_fsm_state = Signal(4)
debug = [
self.sata_phy0.ctrl.ready, self.sata_phy1.ctrl.ready,
self.sata_phy2.ctrl.ready, self.sata_phy3.ctrl.ready,
self.sata_core0_link_tx_fsm_state,
self.sata_core0_link_rx_fsm_state, self.sata_core0.sink.valid,
self.sata_core0.source.valid, self.sata_phy0.source.valid,
self.sata_phy0.source.data, self.sata_phy0.source.charisk,
self.sata_phy0.sink.valid, self.sata_phy0.sink.data,
self.sata_phy0.sink.charisk, self.sata_core1_link_tx_fsm_state,
self.sata_core1_link_rx_fsm_state, self.sata_core1.sink.valid,
self.sata_core1.source.valid, self.sata_phy1.source.valid,
self.sata_phy1.source.data, self.sata_phy1.source.charisk,
self.sata_phy1.sink.valid, self.sata_phy1.sink.data,
self.sata_phy1.sink.charisk, self.sata_core2_link_tx_fsm_state,
self.sata_core2_link_rx_fsm_state, self.sata_core2.sink.valid,
self.sata_core2.source.valid, self.sata_phy2.source.valid,
self.sata_phy2.source.data, self.sata_phy2.source.charisk,
self.sata_phy2.sink.valid, self.sata_phy2.sink.data,
self.sata_phy2.sink.charisk, self.sata_core3_link_tx_fsm_state,
self.sata_core3_link_rx_fsm_state, self.sata_core3.sink.valid,
self.sata_core3.source.valid, self.sata_phy3.source.valid,
self.sata_phy3.source.data, self.sata_phy3.source.charisk,
self.sata_phy3.sink.valid, self.sata_phy3.sink.data,
self.sata_phy3.sink.charisk
]
self.submodules.analyzer = LiteScopeAnalyzer(debug, 2048)
