def main():
args = sys.argv[1:]
load = "load" in args
build = (not "load" in args)
if build:
print("[building]...")
plat = arty.Platform()
plat.add_extension(_extension_io)
module = Module()
counter = Signal(32)
module.sync += counter.eq(counter + 1)
serial_pads = plat.request("serial")
io_serial_pads = plat.request("io_serial")
module.comb += [
serial_pads.tx.eq(io_serial_pads.rx),
io_serial_pads.tx.eq(serial_pads.rx),
plat.request("user_led", 0).eq(plat.request("io_leds", 0)),
plat.request("user_led", 1).eq(plat.request("io_leds", 1)),
plat.request("user_led", 2).eq(plat.request("io_leds", 2)),
plat.request("io_rst", 0).eq(plat.request("user_btn", 0)),
]
plat.build(module, source=False)
elif load:
print("[loading]...")
prog = VivadoProgrammer()
prog.load_bitstream("build/top.bit")
def __init__(self,
sys_clk_freq=int(50e6),
integrated_rom_size=0x8000,
**kwargs):
platform = arty.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=integrated_rom_size,
integrated_sram_size=0x8000,
cpu_variant="lite",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = MT41K128M16(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
def __init__(self, sys_clk_freq=int(100e6)):
platform = arty.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
cpu_type = "microwatt",
integrated_rom_size = 0x8000,
integrate_main_ram_size = 0x8000,
uart_name = "stub")
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# Bridge -----------------------------------------------------------------------------------
self.submodules.bridge = UARTWishboneBridge(
pads = self.platform.request("serial"),
clk_freq = sys_clk_freq,
baudrate = 115200)
self.bus.add_master("bridge", master=self.bridge.wishbone)
# LiteScope --------------------------------------------------------------------------------
analyzer_signals = [
self.cpu.reset,
self.cpu.wb_insn,
self.cpu.wb_data,
]
from litescope import LiteScopeAnalyzer
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth = 512,
clock_domain = "sys",
csr_csv = "analyzer.csv")
self.add_csr("analyzer")
def __init__(self,
toolchain="vivado",
sys_clk_freq=int(100e6),
with_ethernet=False,
with_etherbone=False,
**kwargs):
platform = arty.Platform(toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
if toolchain == "symbiflow":
sys_clk_freq = int(60e6)
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Arty A7",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, toolchain)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size and toolchain != "symbiflow": # FIXME
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq,
interface_type="MEMORY")
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K128M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads=Cat(*[platform.request("user_led", i) for i in range(4)]),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def main():
parser = argparse.ArgumentParser(description="Arty LiteX SoC")
builder_args(parser)
soc_sdram_args(parser)
args = parser.parse_args()
platform = arty.Platform()
soc = BaseSoC(platform, **soc_sdram_argdict(args))
builder = Builder(soc, output_dir="build", csr_csv="test/csr.csv")
vns = builder.build()
soc.do_exit(vns)
def __init__(self, **kwargs):
platform = arty.Platform()
SoCCore.__init__(self,
platform,
clk_freq=100 * 1000000,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
integrated_main_ram_size=0x10000,
**kwargs)
self.submodules.crg = _CRG(platform)
def main():
parser = argparse.ArgumentParser(description="Arty LiteX SoC")
builder_args(parser)
parser.add_argument("--nocompile-gateware", action="store_true")
args = parser.parse_args()
platform = arty.Platform()
soc = EtherboneSoC(platform)
builder = Builder(soc,
output_dir="build",
compile_gateware=not args.nocompile_gateware,
csr_csv="test/csr.csv")
vns = builder.build()
def __init__(self,
sys_clk_freq=int(50e6),
integrated_rom_size=0x8000,
**kwargs):
platform = arty.Platform()
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=integrated_rom_size,
integrated_sram_size=0x8000,
ident="MiniLitex",
cpu_variant="lite",
**kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
def main():
parser = argparse.ArgumentParser(description="Arty LiteX SoC")
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--with-ethernet", action="store_true",
help="enable Ethernet support")
parser.add_argument("--nocompile-gateware", action="store_true")
args = parser.parse_args()
platform = arty.Platform()
cls = MiniSoC if args.with_ethernet else BaseSoC
soc = cls(platform, **soc_sdram_argdict(args))
builder = Builder(soc, output_dir="build",
compile_gateware=not args.nocompile_gateware,
csr_csv="test/csr.csv")
vns = builder.build()
def __init__(self, sys_clk_freq=int(100e6), **kwargs):
platform = arty.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
# sdram
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = MT41K128M16(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self,
sys_clk_freq=int(100e6),
with_ethernet=False,
with_etherbone=False,
**kwargs):
platform = arty.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq,
interface_type="MEMORY")
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K128M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy)
def __init__(self, **kwargs):
platform = arty.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=100*1000000,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform)
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("A7DDRPHY_BITSLIP", 2)
self.add_constant("A7DDRPHY_DELAY", 6)
sdram_module = MT41K128M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self,
toolchain="vivado",
sys_clk_freq=int(60e6),
with_ethernet=False,
with_ram=False,
board_variant="a7-35",
**kwargs):
platform = arty.Platform(variant=board_variant, toolchain=toolchain)
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Arty A7",
ident_version=False,
**kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq, toolchain)
# DDR3 SDRAM -------------------------------------------------------------------------------
if with_ram:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K128M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
if with_ethernet:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def main():
platform = arty.Platform()
soc = DMATestSoC(platform)
builder = Builder(soc, output_dir="build", csr_csv="test/csr.csv")
vns = builder.build()
soc.do_exit(vns)
# Analyzer group
analyzer_groups[0] = [
self.serdes.d0.signals,
self.serdes.d1.signals,
self.serdes.d2.signals,
self.serdes.d3.signals,
]
# analyzer
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_groups, 512)
def do_exit(self, vns):
self.analyzer.export_csv(vns, "test/analyzer.csv")
platform = arty.Platform()
soc = LiteScopeSoC(platform)
vns = platform.build(soc)
#
# Create csr and analyzer files
#
soc.finalize()
csr_regions = soc.get_csr_regions()
csr_constants = soc.get_constants()
from litex.build.tools import write_to_file
from litex.soc.integration import cpu_interface
csr_csv = cpu_interface.get_csr_csv(csr_regions, csr_constants)
write_to_file("test/csr.csv", csr_csv)
def get_platform(self):
return arty.Platform(toolchain=self.toolchain)
def __init__(self, with_cpu, with_emulator, with_analyzer):
platform = arty.Platform()
platform.add_extension(_sd_io)
clk_freq = int(100e6)
sd_freq = int(100e6)
SoCCore.__init__(self,
platform,
clk_freq=clk_freq,
cpu_type="lm32" if with_cpu else None,
csr_data_width=32,
with_uart=with_cpu,
with_timer=with_cpu,
ident="SDCard Test SoC",
ident_version=True,
integrated_rom_size=0x8000 if with_cpu else 0,
integrated_main_ram_size=0x8000 if with_cpu else 0)
self.submodules.crg = _CRG(platform)
# bridge
if not with_cpu:
self.add_cpu(
UARTWishboneBridge(platform.request("serial"),
clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu.wishbone)
# emulator
if with_emulator:
sdcard_pads = _sdemulator_pads()
self.submodules.sdemulator = SDEmulator(platform, sdcard_pads)
else:
sdcard_pads = platform.request('sdcard')
# sd
self.submodules.sdclk = SDClockerS7()
self.submodules.sdphy = SDPHY(sdcard_pads, platform.device)
self.submodules.sdcore = SDCore(self.sdphy)
self.submodules.sdtimer = Timer()
self.submodules.bist_generator = BISTBlockGenerator(random=True)
self.submodules.bist_checker = BISTBlockChecker(random=True)
self.comb += [
self.sdcore.source.connect(self.bist_checker.sink),
self.bist_generator.source.connect(self.sdcore.sink)
]
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / clk_freq)
self.platform.add_period_constraint(self.sdclk.cd_sd.clk,
1e9 / sd_freq)
self.platform.add_period_constraint(self.sdclk.cd_sd_fb.clk,
1e9 / sd_freq)
self.crg.cd_sys.clk.attr.add("keep")
self.sdclk.cd_sd.clk.attr.add("keep")
self.sdclk.cd_sd_fb.clk.attr.add("keep")
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.sdclk.cd_sd.clk,
self.sdclk.cd_sd_fb.clk)
# led
led_counter = Signal(32)
self.sync.sd += led_counter.eq(led_counter + 1)
self.comb += platform.request("user_led", 0).eq(led_counter[26])
# analyzer
if with_analyzer:
analyzer_signals = [
self.sdphy.sdpads, self.sdphy.cmdw.sink, self.sdphy.cmdr.sink,
self.sdphy.cmdr.source, self.sdphy.dataw.sink,
self.sdphy.datar.sink, self.sdphy.datar.source
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
2048,
cd="sd")
def __init__(self,
toolchain="vivado",
sys_clk_freq=int(100e6),
args=None,
ip_address="192.168.100.50",
mac_address=0x10e2d5000001,
udp_port=1234,
**kwargs):
if not args.sim:
platform = arty.Platform(toolchain=toolchain)
else:
platform = SimPlatform("SIM", _io)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Arty A7",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
if not args.sim:
self.submodules.crg = _CRG(platform, sys_clk_freq, args)
else:
self.submodules.crg = CRG(platform.request("sys_clk"))
# DDR3 SDRAM -------------------------------------------------------------------------------
if not args.sim:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
else:
from litedram.gen import get_dram_ios
core_config = dict()
core_config["sdram_module_nb"] = 2 # Number of byte groups
core_config["sdram_rank_nb"] = 1 # Number of ranks
core_config['sdram_module'] = getattr(litedram_modules,
'MT41K128M16')
core_config["memtype"] = "DDR3" # DRAM type
platform.add_extension(get_dram_ios(core_config))
sdram_module = core_config["sdram_module"](
sys_clk_freq,
rate={
"DDR2": "1:2",
"DDR3": "1:4",
"DDR4": "1:4"
}[core_config["memtype"]])
from litex.tools.litex_sim import get_sdram_phy_settings
sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings
phy_settings = get_sdram_phy_settings(
memtype=sdram_module.memtype,
data_width=core_config["sdram_module_nb"] * 8,
clk_freq=sdram_clk_freq)
self.submodules.ddrphy = SDRAMPHYModel(
module=sdram_module,
settings=phy_settings,
clk_freq=sdram_clk_freq,
verbosity=3,
)
class ControllerDynamicSettings(Module, AutoCSR, AutoDoc):
"""Allows to change LiteDRAMController behaviour at runtime"""
def __init__(self):
self.refresh = CSRStorage(
reset=1,
description="Enable/disable Refresh commands sending")
self.submodules.controller_settings = ControllerDynamicSettings()
self.add_csr("controller_settings")
controller_settings = ControllerSettings()
controller_settings.with_auto_precharge = True
controller_settings.with_refresh = self.controller_settings.refresh.storage
self.add_csr("ddrphy")
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=MT41K128M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=0,
l2_cache_min_data_width=0, #128
l2_cache_reverse=True,
controller_settings=controller_settings)
# Ethernet / Etherbone ---------------------------------------------------------------------
if not args.sim:
# Ethernet PHY (arty)
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy,
ip_address=ip_address,
mac_address=mac_address,
udp_port=udp_port)
else:
# Ethernet PHY (simulation)
self.submodules.ethphy = LiteEthPHYModel(
self.platform.request("eth", 0)) # FIXME
self.add_csr("ethphy")
# Ethernet Core
ethcore = LiteEthUDPIPCore(self.ethphy,
ip_address=ip_address,
mac_address=mac_address,
clk_freq=sys_clk_freq)
self.submodules.ethcore = ethcore
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp,
udp_port,
mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
if args.sim:
self.comb += platform.trace.eq(1)
# Rowhammer --------------------------------------------------------------------------------
self.submodules.rowhammer_dma = LiteDRAMDMAReader(
self.sdram.crossbar.get_port())
self.submodules.rowhammer = RowHammerDMA(self.rowhammer_dma)
self.add_csr("rowhammer")
def add_xram(self, name, origin, mem, mode='rw'):
from litex.soc.interconnect import wishbone
from litex.soc.integration.soc import SoCRegion
ram = wishbone.SRAM(mem,
bus=wishbone.Interface(data_width=mem.width),
read_only='w' not in mode)
ram_bus = wishbone.Interface(data_width=self.bus.data_width)
self.submodules += wishbone.Converter(ram_bus, ram.bus)
region = SoCRegion(origin=origin,
size=mem.width // 8 * mem.depth,
mode=mode)
self.bus.add_slave(name, ram_bus, region)
self.check_if_exists(name)
self.logger.info("RAM {} {} {}.".format(
colorer(name), colorer("added", color="green"),
self.bus.regions[name]))
setattr(self.submodules, name, ram)
# Bist -------------------------------------------------------------------------------------
if not args.no_memory_bist:
# ------------------------------ writer ------------------------------------
dram_wr_port = self.sdram.crossbar.get_port()
self.submodules.writer = Writer(dram_wr_port)
self.add_csr('writer')
# TODO: Rename as 'pattern_wr_w?'
add_xram(self,
name='pattern_w0',
mem=self.writer.memory_w0,
origin=0x20000000)
add_xram(self,
name='pattern_w1',
mem=self.writer.memory_w1,
origin=0x21000000)
add_xram(self,
name='pattern_w2',
mem=self.writer.memory_w2,
origin=0x22000000)
add_xram(self,
name='pattern_w3',
mem=self.writer.memory_w3,
origin=0x23000000)
add_xram(self,
name='pattern_adr',
mem=self.writer.memory_adr,
origin=0x24000000)
# ----------------------------- reader -------------------------------------
dram_rd_port = self.sdram.crossbar.get_port()
self.submodules.reader = Reader(dram_rd_port)
self.add_csr('reader')
add_xram(self,
name='pattern_rd_w0',
mem=self.reader.memory_w0,
origin=0x30000000)
add_xram(self,
name='pattern_rd_w1',
mem=self.reader.memory_w1,
origin=0x31000000)
add_xram(self,
name='pattern_rd_w2',
mem=self.reader.memory_w2,
origin=0x32000000)
add_xram(self,
name='pattern_rd_w3',
mem=self.reader.memory_w3,
origin=0x33000000)
add_xram(self,
name='pattern_rd_adr',
mem=self.reader.memory_adr,
origin=0x34000000)
# Payload executor -------------------------------------------------------------------------
if not args.no_payload_executor:
# TODO: disconnect bus during payload execution
phy_settings = self.sdram.controller.settings.phy
scratchpad_width = phy_settings.dfi_databits * phy_settings.nphases
scratchpad_size = 2**10
payload_mem = Memory(32, 2**10)
scratchpad_mem = Memory(scratchpad_width,
scratchpad_size // (scratchpad_width // 8))
self.specials += payload_mem, scratchpad_mem
add_xram(self, name='payload', mem=payload_mem, origin=0x35000000)
add_xram(self,
name='scratchpad',
mem=scratchpad_mem,
origin=0x36000000,
mode='r')
self.submodules.payload_executor = PayloadExecutor(
mem_payload=payload_mem,
mem_scratchpad=scratchpad_mem,
dfi=self.sdram.dfii.ext_dfi,
dfi_sel=self.sdram.dfii.ext_dfi_sel,
nranks=self.sdram.controller.settings.phy.nranks,
bankbits=self.sdram.controller.settings.geom.bankbits,
rowbits=self.sdram.controller.settings.geom.rowbits,
colbits=self.sdram.controller.settings.geom.colbits,
rdphase=self.sdram.controller.settings.phy.rdphase,
)
self.payload_executor.add_csrs()
self.add_csr('payload_executor')
def __init__(self,
sys_clk_freq=int(100e6),
with_ethernet=False,
with_etherbone=False,
**kwargs):
platform = arty.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq,
interface_type="MEMORY")
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K128M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy)
#------- GPIO module
ckio_pins = [
("ckio", 0, Pins("ck_io:ck_io0"), IOStandard("LVCMOS33")),
("ckio", 1, Pins("ck_io:ck_io1"), IOStandard("LVCMOS33")),
("ckio", 2, Pins("ck_io:ck_io2"), IOStandard("LVCMOS33")),
("ckio", 3, Pins("ck_io:ck_io3"), IOStandard("LVCMOS33")),
("ckio", 4, Pins("ck_io:ck_io4"), IOStandard("LVCMOS33")),
("ckio", 5, Pins("ck_io:ck_io5"), IOStandard("LVCMOS33")),
("ckio", 6, Pins("ck_io:ck_io6"), IOStandard("LVCMOS33")),
("ckio", 7, Pins("ck_io:ck_io7"), IOStandard("LVCMOS33")),
("ckio", 8, Pins("ck_io:ck_io8"), IOStandard("LVCMOS33")),
("ckio", 9, Pins("ck_io:ck_io9"), IOStandard("LVCMOS33")),
("ckio", 10, Pins("ck_io:ck_io10"), IOStandard("LVCMOS33")),
("ckio", 11, Pins("ck_io:ck_io11"), IOStandard("LVCMOS33")),
("ckio", 12, Pins("ck_io:ck_io12"), IOStandard("LVCMOS33")),
("ckio", 13, Pins("ck_io:ck_io13"), IOStandard("LVCMOS33")),
("ckio", 14, Pins("ck_io:ck_io14"), IOStandard("LVCMOS33")),
("ckio", 15, Pins("ck_io:ck_io15"), IOStandard("LVCMOS33")),
("ckio", 16, Pins("ck_io:ck_io16"), IOStandard("LVCMOS33")),
("ckio", 17, Pins("ck_io:ck_io17"), IOStandard("LVCMOS33")),
("ckio", 18, Pins("ck_io:ck_io18"), IOStandard("LVCMOS33")),
("ckio", 19, Pins("ck_io:ck_io19"), IOStandard("LVCMOS33")),
("ckio", 20, Pins("ck_io:ck_io20"), IOStandard("LVCMOS33")),
("ckio", 21, Pins("ck_io:ck_io21"), IOStandard("LVCMOS33")),
("ckio", 22, Pins("ck_io:ck_io22"), IOStandard("LVCMOS33")),
("ckio", 23, Pins("ck_io:ck_io23"), IOStandard("LVCMOS33")),
("ckio", 24, Pins("ck_io:ck_io24"), IOStandard("LVCMOS33")),
("ckio", 25, Pins("ck_io:ck_io25"), IOStandard("LVCMOS33")),
("ckio", 26, Pins("ck_io:ck_io26"), IOStandard("LVCMOS33")),
("ckio", 27, Pins("ck_io:ck_io27"), IOStandard("LVCMOS33")),
("ckio", 28, Pins("ck_io:ck_io28"), IOStandard("LVCMOS33")),
("ckio", 29, Pins("ck_io:ck_io29"), IOStandard("LVCMOS33")),
("ckio", 30, Pins("ck_io:ck_io30"), IOStandard("LVCMOS33")),
("ckio", 31, Pins("ck_io:ck_io31"), IOStandard("LVCMOS33")),
("ckio", 32, Pins("ck_io:ck_io32"), IOStandard("LVCMOS33")),
("ckio", 33, Pins("ck_io:ck_io33"), IOStandard("LVCMOS33")),
("ckio", 34, Pins("ck_io:ck_io34"), IOStandard("LVCMOS33")),
("ckio", 35, Pins("ck_io:ck_io35"), IOStandard("LVCMOS33")),
("ckio", 36, Pins("ck_io:ck_io36"), IOStandard("LVCMOS33")),
("ckio", 37, Pins("ck_io:ck_io37"), IOStandard("LVCMOS33")),
("ckio", 38, Pins("ck_io:ck_io38"), IOStandard("LVCMOS33")),
("ckio", 39, Pins("ck_io:ck_io39"), IOStandard("LVCMOS33")),
("ckio", 40, Pins("ck_io:ck_io40"), IOStandard("LVCMOS33")),
("ckio", 41, Pins("ck_io:ck_io41"), IOStandard("LVCMOS33"))
]
self.platform.add_extension(ckio_pins)
sig = self.platform.request("ckio")
self.submodules.gpjajo = GPIOOut(sig)
self.add_csr("gpjajo")
def __init__(self,
toolchain="vivado",
sys_clk_freq=int(100e6),
args=None,
ip_address="192.168.100.50",
mac_address=0x10e2d5000001,
udp_port=1234,
**kwargs):
if not args.sim:
platform = arty.Platform(toolchain=toolchain)
else:
platform = Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Arty A7",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
if not args.sim:
self.submodules.crg = _CRG(platform, sys_clk_freq, args)
else:
self.submodules.crg = CRG(platform.request("sys_clk"))
# DDR3 SDRAM -------------------------------------------------------------------------------
if not args.sim:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
else:
from litedram.gen import get_dram_ios
core_config = dict()
core_config["sdram_module_nb"] = 2 # Number of byte groups
core_config["sdram_rank_nb"] = 1 # Number of ranks
core_config['sdram_module'] = getattr(litedram_modules,
'MT41K128M16')
core_config["memtype"] = "DDR3" # DRAM type
platform.add_extension(get_dram_ios(core_config))
sdram_module = core_config["sdram_module"](
sys_clk_freq,
rate={
"DDR2": "1:2",
"DDR3": "1:4",
"DDR4": "1:4"
}[core_config["memtype"]])
from litex.tools.litex_sim import get_sdram_phy_settings
sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings
phy_settings = get_sdram_phy_settings(
memtype=sdram_module.memtype,
data_width=core_config["sdram_module_nb"] * 8,
clk_freq=sdram_clk_freq)
self.submodules.ddrphy = SDRAMPHYModel(
module=sdram_module,
settings=phy_settings,
clk_freq=sdram_clk_freq,
verbosity=3,
)
class ControllerDynamicSettings(Module, AutoCSR, AutoDoc):
"""Allows to change LiteDRAMController behaviour at runtime"""
def __init__(self):
self.refresh = CSRStorage(
reset=1,
description="Enable/disable Refresh commands sending")
self.submodules.controller_settings = ControllerDynamicSettings()
self.add_csr("controller_settings")
controller_settings = ControllerSettings()
controller_settings.with_auto_precharge = True
controller_settings.with_refresh = self.controller_settings.refresh.storage
self.add_csr("ddrphy")
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=MT41K128M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=0,
l2_cache_min_data_width=0, #128
l2_cache_reverse=True,
controller_settings=controller_settings)
# Ethernet / Etherbone ---------------------------------------------------------------------
if not args.sim:
# Ethernet PHY (arty)
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy,
ip_address=ip_address,
mac_address=mac_address,
udp_port=udp_port)
else:
# Ethernet PHY (simulation)
self.submodules.ethphy = LiteEthPHYModel(
self.platform.request("eth", 0)) # FIXME
self.add_csr("ethphy")
# Ethernet Core
ethcore = LiteEthUDPIPCore(self.ethphy,
ip_address=ip_address,
mac_address=mac_address,
clk_freq=sys_clk_freq)
self.submodules.ethcore = ethcore
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp,
udp_port,
mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
# Analyzer ---------------------------------------------------------------------------------
# analyzer_signals = [
# self.bus.masters['master0'].stb,
# self.bus.masters['master0'].cyc,
# self.bus.masters['master0'].adr,
# self.bus.masters['master0'].we,
# self.bus.masters['master0'].ack,
# self.bus.masters['master0'].sel,
# self.bus.masters['master0'].dat_w,
# self.bus.masters['master0'].dat_r,
# ]
# from litescope import LiteScopeAnalyzer
# self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
# depth = 512,
# clock_domain = "sys",
# csr_csv = "analyzer.csv")
# self.add_csr("analyzer")
if args.sim:
self.comb += platform.trace.eq(1)
# Rowhammer --------------------------------------------------------------------------------
from litedram.frontend.dma import LiteDRAMDMAReader, LiteDRAMDMAWriter
self.submodules.rowhammer_dma = LiteDRAMDMAReader(
self.sdram.crossbar.get_port())
self.submodules.rowhammer = RowHammerDMA(self.rowhammer_dma)
self.add_csr("rowhammer")
# Bist -------------------------------------------------------------------------------------
if not args.no_memory_bist:
from litedram.frontend.bist import LiteDRAMBISTGenerator, LiteDRAMBISTChecker
def add_xram(self, name, origin, mem):
from litex.soc.interconnect import wishbone
from litex.soc.integration.soc import SoCRegion
ram_bus = wishbone.Interface(data_width=self.bus.data_width)
ram = wishbone.SRAM(mem, bus=ram_bus)
self.bus.add_slave(
name, ram.bus,
SoCRegion(origin=origin,
size=mem.width * mem.depth,
mode='rw'))
self.check_if_exists(name)
self.logger.info("RAM {} {} {}.".format(
colorer(name), colorer("added", color="green"),
self.bus.regions[name]))
setattr(self.submodules, name, ram)
return
# ------------------------------ writer ------------------------------------
memory_w0 = Memory(32, 1024)
memory_w1 = Memory(32, 1024)
memory_w2 = Memory(32, 1024)
memory_w3 = Memory(32, 1024)
memory_adr = Memory(32, 1024)
add_xram(self, name='pattern_w0', mem=memory_w0, origin=0x20000000)
add_xram(self, name='pattern_w1', mem=memory_w1, origin=0x21000000)
add_xram(self, name='pattern_w2', mem=memory_w2, origin=0x22000000)
add_xram(self, name='pattern_w3', mem=memory_w3, origin=0x23000000)
add_xram(self,
name='pattern_adr',
mem=memory_adr,
origin=0x24000000)
class Writer(Module, AutoCSR):
def __init__(self, dram_port, w0_port, w1_port, w2_port,
w3_port, adr_port):
self.reset = CSRStorage()
self.start = CSRStorage()
self.done = CSRStatus()
self.count = CSRStorage(size=(32 * 1))
self.mem_base = CSRStorage(size=32)
self.mem_mask = CSRStorage(size=32)
self.data_mask = CSRStorage(size=32) # patterns
dma = LiteDRAMDMAWriter(dram_port, fifo_depth=1)
self.submodules += dma
cmd_counter = Signal(32)
self.comb += [
w0_port.adr.eq(cmd_counter & self.data_mask.storage),
w1_port.adr.eq(cmd_counter & self.data_mask.storage),
w2_port.adr.eq(cmd_counter & self.data_mask.storage),
w3_port.adr.eq(cmd_counter & self.data_mask.storage),
adr_port.adr.eq(cmd_counter & self.data_mask.storage),
]
self.comb += [
dma.sink.address.eq(self.mem_base.storage +
adr_port.dat_r +
(cmd_counter
& self.mem_mask.storage)),
dma.sink.data.eq(
Cat(w0_port.dat_r, w1_port.dat_r, w2_port.dat_r,
w3_port.dat_r)),
]
fsm = FSM(reset_state="IDLE")
self.submodules += fsm
fsm.act(
"IDLE",
If(
self.start.storage,
NextValue(cmd_counter, 0),
NextState("WAIT"),
))
fsm.act(
"WAIT",
If(cmd_counter >= self.count.storage,
NextState("DONE")).Else(NextState("RUN")))
fsm.act(
"RUN", dma.sink.valid.eq(1),
If(dma.sink.ready,
NextValue(cmd_counter, cmd_counter + 1),
NextState("WAIT")))
fsm.act("DONE", self.done.status.eq(1),
If(self.reset.storage, NextState("IDLE")))
dram_port = self.sdram.crossbar.get_port()
w0_port = memory_w0.get_port()
w1_port = memory_w1.get_port()
w2_port = memory_w2.get_port()
w3_port = memory_w3.get_port()
adr_port = memory_adr.get_port()
self.specials += w0_port, w1_port, w2_port, w3_port, adr_port
self.submodules.writer = Writer(dram_port, w0_port, w1_port,
w2_port, w3_port, adr_port)
self.add_csr('writer')
# ----------------------------- reader -------------------------------------
memory_rd_w0 = Memory(32, 1024)
memory_rd_w1 = Memory(32, 1024)
memory_rd_w2 = Memory(32, 1024)
memory_rd_w3 = Memory(32, 1024)
memory_rd_adr = Memory(32, 1024)
add_xram(self,
name='pattern_rd_w0',
mem=memory_rd_w0,
origin=0x30000000)
add_xram(self,
name='pattern_rd_w1',
mem=memory_rd_w1,
origin=0x31000000)
add_xram(self,
name='pattern_rd_w2',
mem=memory_rd_w2,
origin=0x32000000)
add_xram(self,
name='pattern_rd_w3',
mem=memory_rd_w3,
origin=0x33000000)
add_xram(self,
name='pattern_rd_adr',
mem=memory_rd_adr,
origin=0x34000000)
class Reader(Module, AutoCSR):
def __init__(self, dram_port, w0_port, w1_port, w2_port,
w3_port, adr_port):
self.reset = CSRStorage()
self.start = CSRStorage()
self.done = CSRStatus()
self.count = CSRStorage(size=32)
self.pointer = CSRStatus(size=32)
self.mem_base = CSRStorage(size=32)
self.mem_mask = CSRStorage(size=32)
self.data_mask = CSRStorage(size=32) # patterns
dma = LiteDRAMDMAReader(dram_port,
fifo_depth=1,
fifo_buffered=False)
self.submodules += dma
cmd_counter = Signal(32)
self.comb += [
w0_port.adr.eq(cmd_counter & self.data_mask.storage),
w1_port.adr.eq(cmd_counter & self.data_mask.storage),
w2_port.adr.eq(cmd_counter & self.data_mask.storage),
w3_port.adr.eq(cmd_counter & self.data_mask.storage),
adr_port.adr.eq(cmd_counter & self.data_mask.storage),
]
data_pattern = Signal(32 * 4)
self.comb += [
dma.sink.address.eq(self.mem_base.storage +
adr_port.dat_r +
(cmd_counter
& self.mem_mask.storage)),
data_pattern.eq(
Cat(w0_port.dat_r, w1_port.dat_r, w2_port.dat_r,
w3_port.dat_r)),
]
fsm = FSM(reset_state="IDLE")
self.submodules += fsm
fsm.act(
"IDLE",
If(
self.start.storage,
NextValue(cmd_counter, 0),
NextValue(self.pointer.status, 0xdeadbeef),
NextState("WAIT"),
))
fsm.act(
"WAIT",
If(cmd_counter >= self.count.storage,
NextState("DONE")).Else(NextState("WR_ADR")))
fsm.act("WR_ADR", dma.sink.valid.eq(1),
If(dma.sink.ready, NextState("RD_DATA")))
fsm.act(
"RD_DATA", dma.source.ready.eq(1),
If(
dma.source.valid,
NextValue(cmd_counter, cmd_counter + 1),
If(dma.source.data != data_pattern,
NextValue(self.pointer.status, cmd_counter)),
NextState("WAIT")))
fsm.act("DONE", self.done.status.eq(1),
If(self.reset.storage, NextState("IDLE")))
dram_rd_port = self.sdram.crossbar.get_port()
w0_port = memory_rd_w0.get_port()
w1_port = memory_rd_w1.get_port()
w2_port = memory_rd_w2.get_port()
w3_port = memory_rd_w3.get_port()
adr_port = memory_rd_adr.get_port()
self.specials += w0_port, w1_port, w2_port, w3_port, adr_port
self.submodules.reader = Reader(dram_rd_port, w0_port, w1_port,
w2_port, w3_port, adr_port)
self.add_csr('reader')
