def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, **kwargs): platform = nexys4ddr.Platform() # SoCCore ----------------------------------_----------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR2 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR2", nphases=2, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT47H64M16(sys_clk_freq, "1:2"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHYRMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy)
def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, **kwargs): platform = nexys4ddr.Platform() # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR2 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR2", nphases=2, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") sdram_module = MT47H64M16(sys_clk_freq, "1:2") self.register_sdram(self.ddrphy, geom_settings=sdram_module.geom_settings, timing_settings=sdram_module.timing_settings) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHYRMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_ethernet(phy=self.ethphy)
def __init__(self, **kwargs): platform = nexys4ddr.Platform() SoCSDRAM.__init__(self, platform, clk_freq=100*1000000, integrated_rom_size=0x8000, integrated_sram_size=0x8000, **kwargs) self.submodules.crg = _CRG(platform) # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) sdram_module = MT47H64M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings)
def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = nexys4ddr.Platform() # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR2 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR2", nphases=2, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") sdram_module = MT47H64M16(sys_clk_freq, "1:2") self.register_sdram(self.ddrphy, geom_settings=sdram_module.geom_settings, timing_settings=sdram_module.timing_settings)
def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = nexys4ddr.Platform() SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x8000, **kwargs) self.submodules.crg = _CRG(platform, sys_clk_freq) # sdram self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype="DDR2", nphases=2, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") sdram_module = MT47H64M16(sys_clk_freq, "1:2") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings) self.add_constant("MEMTEST_ADDR_SIZE", 0) # FIXME
from migen import * from litex.boards.platforms import nexys4ddr # Create a led blinker module class Blink(Module): def __init__(self, led): counter = Signal(26) # combinatorial assignment self.comb += led.eq(counter[25]) # synchronous assignement self.sync += counter.eq(counter + 1) # Create our platform platform = nexys4ddr.Platform() # Get led signal from our platform led = platform.request("user_led", 0) # Create our main module module = Blink(led) # Build the design platform.build(module)
def __init__(self, with_cpu, with_emulator, with_analyzer): platform = nexys4ddr.Platform() sys_clk_freq = int(100e6) sd_clk_freq = int(100e6) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, cpu_type="vexriscv" if with_cpu else None, csr_data_width=32, with_uart=with_cpu, with_timer=with_cpu, ident="SDCard Test SoC", ident_version=True, integrated_rom_size=0x8000 if with_cpu else 0, integrated_main_ram_size=0x8000 if with_cpu else 0) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # Serial bridge (optional) ----------------------------------------------------------------- if not with_cpu: self.submodules.bridge = UARTWishboneBridge( platform.request("serial"), sys_clk_freq) self.add_wb_master(self.bridge.wishbone) # SDCard Emulator (optional) --------------------------------------------------------------- if with_emulator: from litesdcard.emulator import SDEmulator, _sdemulator_pads sdcard_pads = _sdemulator_pads() self.submodules.sdemulator = SDEmulator(platform, sdcard_pads) self.add_csr("sdemulator") else: sdcard_pads = platform.request('sdcard') # SDCard ----------------------------------------------------------------------------------- self.comb += sdcard_pads.rst.eq(0) self.submodules.sdclk = SDClockerS7() self.submodules.sdphy = SDPHY(sdcard_pads, platform.device) self.submodules.sdcore = SDCore(self.sdphy) self.submodules.sdtimer = Timer() self.add_csr("sdclk") self.add_csr("sdphy") self.add_csr("sdcore") self.add_csr("sdtimer") self.submodules.bist_generator = BISTBlockGenerator(random=True) self.submodules.bist_checker = BISTBlockChecker(random=True) self.add_csr("bist_generator") self.add_csr("bist_checker") self.comb += [ self.sdcore.source.connect(self.bist_checker.sink), self.bist_generator.source.connect(self.sdcore.sink) ] self.platform.add_period_constraint(self.sdclk.cd_sd.clk, 1e9 / sd_clk_freq) self.platform.add_period_constraint(self.sdclk.cd_sd_fb.clk, 1e9 / sd_clk_freq) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.sdclk.cd_sd.clk, self.sdclk.cd_sd_fb.clk) # Led -------------------------------------------------------------------------------------- led_counter = Signal(32) self.sync.sd += led_counter.eq(led_counter + 1) self.comb += platform.request("user_led", 0).eq(led_counter[26]) # Analyzer (optional) ---------------------------------------------------------------------- if with_analyzer: from litescope import LiteScopeAnalyzer analyzer_signals = [ self.sdphy.sdpads, self.sdphy.cmdw.sink, self.sdphy.cmdr.sink, self.sdphy.cmdr.source, self.sdphy.dataw.sink, self.sdphy.datar.sink, self.sdphy.datar.source ] self.submodules.analyzer = LiteScopeAnalyzer( analyzer_signals, 2048, clock_domain="sd", csr_csv="../test/analyzer.csv") self.add_csr("analyzer")