def main():
with open("README.md") as f:
description = [str(f.readline()) for i in range(1, 9)]
parser = argparse.ArgumentParser(
description="".join(description[1:]),
formatter_class=argparse.RawTextHelpFormatter)
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--flash", action="store_true", help="Flash bitstream")
args = parser.parse_args()
if args.load:
from litex.build.openocd import OpenOCD
prog = OpenOCD("openocd/openocd.cfg")
prog.load_bitstream("build/gateware/top.bit")
exit()
if args.flash:
from litex.build.openocd import OpenOCD
prog = OpenOCD("openocd/openocd.cfg",
flash_proxy_basename="openocd/bscan_spi_xc7a35t.bit")
prog.set_flash_proxy_dir(".")
prog.flash(0, "build/gateware/top.bin")
exit()
platform = netv2.Platform()
platform.add_extension(_pcie_analyzer_io)
soc = PCIeAnalyzer(platform)
builder = Builder(soc, output_dir="build", csr_csv="tools/csr.csv")
builder.build(run=args.build)
def load():
import os
f = open("netv2.cfg", "w")
f.write(
"""
interface bcm2835gpio
transport select jtag
bcm2835gpio_peripheral_base 0x3F000000
bcm2835gpio_speed_coeffs 100000 5
bcm2835gpio_jtag_nums 4 17 27 22
bcm2835gpio_srst_num 24
reset_config none
source [find cpld/xilinx-xc7.cfg]
adapter_khz 10000
proc fpga_program {} {
global _CHIPNAME
xc7_program $_CHIPNAME.tap
}
""")
f.close()
from litex.build.openocd import OpenOCD
prog = OpenOCD("netv2.cfg")
prog.load_bitstream("build/gateware/top.bit")
def main():
parser = argparse.ArgumentParser(description="PCIe Screamer Test Gateware")
parser.add_argument("--m2", action="store_true", help="use M2 variant of PCIe Screamer")
parser.add_argument("--with-analyzer", action="store_true", help="enable Analyzer")
parser.add_argument("--with-loopback", action="store_true", help="enable USB Loopback")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--flash", action="store_true", help="Flash bitstream")
args = parser.parse_args()
if args.m2:
from platforms.pcie_screamer_m2 import Platform
else:
from platforms.pcie_screamer import Platform
platform = Platform()
soc = PCIeScreamer(platform, args.with_analyzer, args.with_loopback)
builder = Builder(soc, output_dir="build", csr_csv="test/csr.csv")
builder.build(run=args.build)
if args.load:
from litex.build.openocd import OpenOCD
prog = OpenOCD("openocd/openocd.cfg")
prog.load_bitstream("build/gateware/top.bit")
if args.flash:
from litex.build.openocd import OpenOCD
prog = OpenOCD("openocd/openocd.cfg",
flash_proxy_basename="openocd/bscan_spi_xc7a35t.bit")
prog.set_flash_proxy_dir(".")
prog.flash(0, "build/gateware/top.bin")
def __init__(self, soc):
openocddir = os.path.join(os.environ["ZTC_TOOLS_DIR"], "share",
"openocd")
cfg = os.path.join(openocddir, "openocd_xilinx.cfg")
device = soc.platform.device.split("-", 1)[0]
if device == "xc7a35ticsg324":
device = "xc7a35t"
flash_proxy = os.path.join("bscan_spi_bitstreams",
"bscan_spi_" + device + ".bit")
self.prog = OpenOCD(cfg, flash_proxy_basename=flash_proxy)
self.prog.set_flash_proxy_dir(openocddir)
def main():
description = "LiteX-VexRiscv SoC Builder\n\n"
parser = argparse.ArgumentParser(
description=description, formatter_class=argparse.RawTextHelpFormatter)
parser.add_argument("--build", action="store_true", help="build bitstream")
parser.add_argument("--load",
action="store_true",
help="load bitstream (to SRAM)")
parser.add_argument("--flash",
action="store_true",
help="flash bitstream/images (to SPI Flash)")
args = parser.parse_args()
if args.build:
platform = basys3.Platform()
dut = System(platform)
platform.build(dut,
build_dir="build/sys_accel_simulator_release/gateware")
if args.load:
from litex.build.xilinx import VivadoProgrammer
prog = VivadoProgrammer()
prog.load_bitstream(
"build/sys_accel_simulator_release/gateware/top.bit")
if args.flash:
from litex.build.openocd import OpenOCD
prog = OpenOCD("../prog/openocd_xilinx.cfg",
flash_proxy_basename="../prog/bscan_spi_xc7a35t.bit")
prog.set_flash_proxy_dir(".")
prog.flash(0, "build/sys_accel_simulator_release/gateware/top.bin")
def create_programmer(self, **kwargs):
# For xc3sprog
# See also http://xc3sprog.sourceforge.net
# get source with: svn checkout https://svn.code.sf.net/p/xc3sprog/code/trunk xc3sprog
if self.programmer == "xc3sprog":
# to program the configuration flash, the FPGA must first be
# programmed with a bitstream which provides a way to foward
# data to flash. This is called a "flash proxy". Flash proxies
# for some parts are already included in xc3sprog. Additional
# ones can be found e.g. https://github.com/quartiq/bscan_spi_bitstreams
# defines which flash proxy bitstream to use for which part
flash_proxy = {
"s7-50": "bscan_spi_xc7s50.bit",
"s7-25": "bscan_spi_xc7s25.bit"
}[self.device_variant]
programmer = XC3SProg("jtaghs1_fast",
flash_proxy_basename=flash_proxy)
# search part where to find proxy bitsreams. If not specified
# defaults to one of:
# "~/.migen", "/usr/local/share/migen", "/usr/share/migen",
# "~/.mlabs", "/usr/local/share/mlabs", "/usr/share/mlabs",
# "~/.litex", "/usr/local/share/litex", "/usr/share/litex"
programmer.set_flash_proxy_dir("prog")
return programmer
# For Xilinx Vivado programmer
# Vivado also uses flash proxy bitstreams but they are already shipped
# with Vivado and are used automatically. Flash_part specifies the
# exact part used in the Arty-S7 Rev. E
elif self.programmer == "vivado":
return VivadoProgrammer(flash_part="mt25ql128-spi-x1_x2_x4")
# For OpenOCD
elif self.programmer == "openocd":
bscan_spi = "bscan_spi_xc7s50.bit" \
if "xc7s50" in self.device \
else "bscan_spi_xc7a25.bit"
programmer = OpenOCD("openocd_xilinx.cfg", bscan_spi)
programmer.set_flash_proxy_dir("prog")
return programmer
else:
raise ValueError("{} programmer is not supported".format(
self.programmer))
def main():
args = sys.argv[1:]
load = "load" in args
build = not "load" in args
if build:
with_cpu = "cpu" in args
with_emulator = "emulator" in args
with_analyzer = "analyzer" in args
print("[building]... cpu: {}, emulator: {}, analyzer: {}".format(
with_cpu, with_emulator, with_analyzer))
soc = SDSoC(with_cpu, with_emulator, with_analyzer)
builder = Builder(soc, output_dir="build", csr_csv="../test/csr.csv")
vns = builder.build()
soc.do_exit(vns)
elif load:
print("[loading]...")
prog = OpenOCD("board/minispartan6.cfg")
prog.load_bitstream("build/gateware/top.bit")
def create_programmer(self):
if self.programmer == "openocd":
proxy="bscan_spi_{}.bit".format(self.device.split('-')[0])
return OpenOCD(config="board/digilent_cmod_a7.cfg", flash_proxy_basename=proxy)
elif self.programmer == "vivado":
# n25q32-3.3v-spi-x1_x2_x4
return VivadoProgrammer(flash_part="n25q32-3.3v-spi-x1_x2_x4")
else:
raise ValueError(
"{} programmer is not supported".format(self.programmer))
def main():
parser = argparse.ArgumentParser(description="Linux on LiteX-VexRiscv")
parser.add_argument("--build", action="store_true", help="build bitstream")
parser.add_argument("--load",
action="store_true",
help="load bitstream (SRAM)")
parser.add_argument("--flash",
action="store_true",
help="flash bitstream (SPI Flash)")
args = parser.parse_args()
if args.build:
soc = LinuxSoC()
builder = Builder(soc, output_dir="build")
builder.build()
if args.load:
from litex.build.openocd import OpenOCD
prog = OpenOCD("openocd/openocd_xilinx.cfg")
prog.load_bitstream("build/gateware/top.bit")
if args.flash:
flash_regions = {
"build/gateware/top.bin":
"0x00000000", # FPGA image: automatically loaded at startup
"binaries/Image":
"0x00400000", # Linux Image: copied to 0xc0000000 by bios
"binaries/rootfs.cpio":
"0x00800000", # File System: copied to 0xc2000000 by bios
"binaries/rv32.dtb":
"0x00f00000", # Device tree: copied to 0xc3000000 by bios
"emulator/emulator.bin":
"0x00f80000", # MM Emulator: copied to 0x20000000 by bios
}
from litex.build.openocd import OpenOCD
prog = OpenOCD("openocd/openocd_xilinx.cfg",
flash_proxy_basename="openocd/bscan_spi_xc7a35t.bit")
prog.set_flash_proxy_dir(".")
for filename, base in flash_regions.items():
base = int(base, 16)
print("Flashing {} at 0x{:08x}".format(filename, base))
prog.flash(base, filename)
def create_programmer(self):
proxy = "bscan_spi_{}.bit".format(self.device.split('-')[0])
if self.programmer == "openocd":
return OpenOCD(config="board/pipistrello.cfg",
flash_proxy_basename=proxy)
# Alternative programmers - not regularly tested.
elif self.programmer == "xc3sprog":
return XC3SProg("papilio", "bscan_spi_lx45_csg324.bit")
else:
raise ValueError("{} programmer is not supported".format(
self.programmer))
def create_programmer(self):
proxy="bscan_spi_{}.bit".format(self.device.split('-')[0])
if self.programmer == "openocd":
return OpenOCD(config="board/minispartan6.cfg", flash_proxy_basename=proxy)
# Alternative programmers - not regularly tested.
elif self.programmer == "xc3sprog":
return XC3SProg("minispartan6", proxy)
elif self.programmer == "fpgaprog":
return FpgaProg()
else:
raise ValueError("{} programmer is not supported".format(self.programmer))
def flash(self):
flash_regions = {
"buildroot/Image.fbi": "0x00000000", # Linux Image: copied to 0xc0000000 by bios
"buildroot/rootfs.cpio.fbi": "0x00500000", # File System: copied to 0xc0800000 by bios
"buildroot/rv32.dtb.fbi": "0x00d00000", # Device tree: copied to 0xc1000000 by bios
"emulator/emulator.bin.fbi": "0x00e00000", # MM Emulator: copied to 0xc1100000 by bios
}
from litex.build.openocd import OpenOCD
prog = OpenOCD("prog/openocd_xilinx.cfg", flash_proxy_basename="bscan_spi_xc7a35t.bit")
prog.set_flash_proxy_dir(".")
for filename, base in flash_regions.items():
base = int(base, 16)
print("Flashing {} at 0x{:08x}".format(filename, base))
prog.flash(base, filename)
def flash(self):
flash_regions = {
"build/arty/gateware/top.bin": "0x00000000", # FPGA image: loaded at startup
"buildroot/Image": "0x00400000", # Linux Image: copied to 0xc0000000 by bios
"buildroot/rootfs.cpio": "0x00800000", # File System: copied to 0xc0800000 by bios
"buildroot/rv32.dtb": "0x00f00000", # Device tree: copied to 0xc1000000 by bios
"emulator/emulator.bin": "0x00f80000", # MM Emulator: copied to 0x20000000 by bios
}
from litex.build.openocd import OpenOCD
prog = OpenOCD("prog/openocd_xilinx.cfg",
flash_proxy_basename="prog/bscan_spi_xc7a35t.bit")
prog.set_flash_proxy_dir(".")
for filename, base in flash_regions.items():
base = int(base, 16)
print("Flashing {} at 0x{:08x}".format(filename, base))
prog.flash(base, filename)
class XilinxOCDProgrammer():
def __init__(self, soc):
openocddir = os.path.join(os.environ["ZTC_TOOLS_DIR"], "share",
"openocd")
cfg = os.path.join(openocddir, "openocd_xilinx.cfg")
device = soc.platform.device.split("-", 1)[0]
if device == "xc7a35ticsg324":
device = "xc7a35t"
flash_proxy = os.path.join("bscan_spi_bitstreams",
"bscan_spi_" + device + ".bit")
self.prog = OpenOCD(cfg, flash_proxy_basename=flash_proxy)
self.prog.set_flash_proxy_dir(openocddir)
def load(self, bitstream_file):
self.prog.load_bitstream(bitstream_file)
def flash(self, regions):
for _, item in regions.items():
print("Flashing {} at 0x{:08x}".format(item[0], item[2]))
self.prog.flash(item[2], item[0])
def create_programmer(self):
return OpenOCD("openocd_xc7_ft4232.cfg", "bscan_spi_xc7k70t.bit")
def flash_gw(self):
from litex.build.openocd import OpenOCD
prog = OpenOCD("prog/openocd_xilinx.cfg",
flash_proxy_basename="prog/bscan_spi_xc7a35t.bit")
prog.set_flash_proxy_dir(".")
prog.flash(0, "build/basys3/gateware/top.bin")
def create_programmer(self):
return OpenOCD("openocd_marblemini.cfg")
def load(self):
from litex.build.openocd import OpenOCD
prog = OpenOCD("prog/openocd_xilinx.cfg")
prog.load_bitstream("build/arty/gateware/top.bit")
def create_programmer(self):
return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a325t.bit")
def flash_gw(self):
from litex.build.openocd import OpenOCD
prog = OpenOCD("prog/openocd_xilinx_platform_cable.cfg",
flash_proxy_basename="prog/bscan_spi_xc7a100t.bit")
prog.set_flash_proxy_dir(".")
prog.flash(0, "build/at7core/gateware/top.bin")
def create_programmer(self):
bscan_spi = "bscan_spi_xc7a35t.bit"
return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi) #FIXME
def create_programmer(self):
return OpenOCD("openocd_nexys_video.cfg", "bscan_spi_xc7a200t.bit")
def create_programmer(self):
return OpenOCD("openocd_xc6_ft232.cfg")
def create_programmer(self):
bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit"
return OpenOCD("openocd_netv2_rpi.cfg", bscan_spi)
def create_programmer(self):
bscan_spi = "bscan_spi_xc7a15t.bit" if "xc7a15t" in self.device else "bscan_spi_xc7a35t.bit"
return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi)
def jtag2telnet(self):
prog = OpenOCD(self.config)
prog.stream(self.port)
def create_programmer(self):
return OpenOCD("openocd_genesys2.cfg", "bscan_spi_xc7a325t.bit")
def create_programmer(self):
return OpenOCD(config="board/digilent_zedboard.cfg")
def load(self):
from litex.build.openocd import OpenOCD
prog = OpenOCD("prog/openocd_netv2_rpi.cfg")
prog.load_bitstream("build/netv2/gateware/top.bit")
def create_programmer(self):
# same file works for marble mini and for marble
return OpenOCD("openocd_marblemini.cfg")
