def build(self, platform, fragment, build_dir="build", build_name="top",
toolchain_path="/opt/Xilinx/Vivado", source=True, run=True,
synth_mode="vivado", enable_xpm=False, **kwargs):
if toolchain_path is None:
toolchain_path = "/opt/Xilinx/Vivado"
os.makedirs(build_dir, exist_ok=True)
cwd = os.getcwd()
os.chdir(build_dir)
if not isinstance(fragment, _Fragment):
fragment = fragment.get_fragment()
platform.finalize(fragment)
self._convert_clocks(platform)
self._constrain(platform)
v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
named_sc, named_pc = platform.resolve_signals(v_output.ns)
v_file = build_name + ".v"
v_output.write(v_file)
sources = platform.sources | {(v_file, "verilog", "work")}
edifs = platform.edifs
ips = platform.ips
self._build_batch(platform, sources, edifs, ips, build_name, synth_mode, enable_xpm)
tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc))
if run:
if synth_mode == "yosys":
common._run_yosys(platform.device, sources, platform.verilog_include_paths, build_name)
_run_vivado(build_name, toolchain_path, source)
os.chdir(cwd)
return v_output.ns
def build(self,
platform,
fragment,
build_dir="build",
build_name="top",
toolchain_path=None,
source=True,
run=True,
synth_mode="vivado",
enable_xpm=False,
**kwargs):
# Get default toolchain path (if not specified)
if toolchain_path is None:
toolchain_path = "/opt/Xilinx/Vivado"
# Create build directory
os.makedirs(build_dir, exist_ok=True)
cwd = os.getcwd()
os.chdir(build_dir)
# Finalize design
if not isinstance(fragment, _Fragment):
fragment = fragment.get_fragment()
platform.finalize(fragment)
# Generate timing constraints
self._build_clock_constraints(platform)
self._build_false_path_constraints(platform)
# Generate verilog
v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
named_sc, named_pc = platform.resolve_signals(v_output.ns)
v_file = build_name + ".v"
v_output.write(v_file)
platform.add_source(v_file)
# Generate design project (.tcl)
self._build_tcl(platform=platform,
build_name=build_name,
synth_mode=synth_mode,
enable_xpm=enable_xpm)
# Generate design constraints (.xdc)
tools.write_to_file(build_name + ".xdc",
_build_xdc(named_sc, named_pc))
# Run
if run:
if synth_mode == "yosys":
common._run_yosys(platform.device, platform.sources,
platform.verilog_include_paths, build_name)
script = _build_script(build_name, toolchain_path, source)
_run_script(script)
os.chdir(cwd)
return v_output.ns
def run_script(self, script):
if self._synth_mode == "yosys":
common._run_yosys(self.platform.device, self.platform.sources,
self.platform.verilog_include_paths, self._build_name)
if sys.platform in ["win32", "cygwin"]:
shell = ["cmd", "/c"]
else:
shell = ["bash"]
if which("vivado") is None and os.getenv("LITEX_ENV_VIVADO", False) == False:
msg = "Unable to find or source Vivado toolchain, please either:\n"
msg += "- Source Vivado's settings manually.\n"
msg += "- Or set LITEX_ENV_VIVADO environment variant to Vivado's settings path.\n"
msg += "- Or add Vivado toolchain to your $PATH."
raise OSError(msg)
if tools.subprocess_call_filtered(shell + [script], common.colors) != 0:
raise OSError("Error occured during Vivado's script execution.")
