示例#1
0
 def _build_clock_constraints(self, platform):
     platform.add_platform_command(_xdc_separator("Clock constraints"))
     #for clk, period in sorted(self.clocks.items(), key=lambda x: x[0].duid):
     #    platform.add_platform_command(
     #        "create_clock -period " + str(period) +
     #        " {clk}", clk=clk)
     pass  #clock constraints not supported
示例#2
0
文件: f4pga.py 项目: cklarhorst/litex
 def build_timing_constraints(self):
     self.platform.add_platform_command(_xdc_separator("Clock constraints"))
     for clk, period in sorted(self.clocks.items(), key=lambda x: x[0].duid):
         self.platform.add_platform_command(
             "create_clock -period " + str(period) +
             " {clk}", clk=clk)
     return ("", "")
示例#3
0
def _build_pcf(named_sc):
    r = _xdc_separator("Design constraints")
    current_resname = ""
    for sig, pins, _, resname in named_sc:
        if current_resname != resname[0]:
            if current_resname:
                r += "\n"
            current_resname = resname[0]
            r += f"# {current_resname}\n"
        if len(pins) > 1:
            for i, p in enumerate(pins):
                r += f"set_io {sig}[{i}] {Pins(p).identifiers[0]}\n"
        elif pins:
            r += f"set_io {sig} {Pins(pins[0]).identifiers[0]}\n"
    return r