def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Alchitry Au(+)")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--flash", action="store_true", help="Flash bitstream.")
target_group.add_argument("--variant", default="au", help="Board variant (au or au+).")
target_group.add_argument("--sys-clk-freq", default=83333333, help="System clock frequency.")
target_group.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(
variant = args.variant,
sys_clk_freq = int(float(args.sys_clk_freq)),
with_spi_flash = args.with_spi_flash,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder.build(**vivado_build_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if args.flash:
prog = soc.platform.create_programmer()
prog.flash(0, builder.get_bitstream_filename(mode="flash"))
def main():
parser = argparse.ArgumentParser(
description="LiteX SoC on MicroNova Mercury2")
parser.add_argument("--toolchain",
default="vivado",
help="Toolchain use to build (default: vivado)")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--variant",
default="a7-35",
help="Board variant: a7-35 (default) or a7-100")
parser.add_argument("--sys-clk-freq",
default=50e6,
help="System clock frequency (default: 50MHz)")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(variant=args.variant,
toolchain=args.toolchain,
sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_core_argdict(args))
builder_argd = builder_argdict(args)
builder = Builder(soc, **builder_argd)
builder_kwargs = vivado_build_argdict(
args) if args.toolchain == "vivado" else {}
builder.build(**builder_kwargs, run=args.build)
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on ZCU216")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
parser.set_defaults(cpu_type="zynqmp")
parser.set_defaults(no_uart=True)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
if args.cpu_type == "zynqmp":
soc.builder = builder
builder.add_software_package('libxil')
builder.add_software_library('libxil')
builder.build(**vivado_build_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC Blackmagic Decklink Mini 4K")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=148.5e6, help="System clock frequency.")
pcieopts = parser.add_mutually_exclusive_group()
pcieopts.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
viopts = parser.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
pcieopts.add_argument("--with-sata", action="store_true", help="Enable SATA support (over PCIe2SATA).")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_pcie = args.with_pcie,
with_sata = args.with_sata,
with_video_terminal = args.with_video_terminal,
with_video_framebuffer = args.with_video_framebuffer,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder_kwargs = vivado_build_argdict(args)
builder.build(**builder_kwargs, run=args.build)
if args.driver:
generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on EGO1")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--flash", action="store_true", help="Flash bitstream.")
parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal.")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_video_terminal = args.with_video_terminal,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder.build(**vivado_build_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if args.flash:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="flash"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC Blackmagic Decklink Intensity Pro 4K")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
target_group.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
target_group.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_pcie = args.with_pcie | True, # FIXME: Always enable PCIe for now.
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder_kwargs = vivado_build_argdict(args)
builder.build(**builder_kwargs, run=args.build)
if args.driver:
generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on EBAZ4205")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--sys-clk-freq",
default=100e6,
help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(**vivado_build_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"),
device=1)
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Nexys Video")
parser.add_argument("--toolchain",
default="vivado",
help="Toolchain use to build (default: vivado)")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq",
default=100e6,
help="System clock frequency (default: 100MHz)")
parser.add_argument("--with-ethernet",
action="store_true",
help="Enable Ethernet support")
sdopts = parser.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard",
action="store_true",
help="Enable SPI-mode SDCard support")
sdopts.add_argument("--with-sdcard",
action="store_true",
help="Enable SDCard support")
parser.add_argument("--with-sata",
action="store_true",
help="Enable SATA support (over FMCRAID)")
parser.add_argument("--vadj",
default="1.2V",
help="FMC VADJ value",
choices=["1.2V", "1.8V", "2.5V", "3.3V"])
viopts = parser.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal",
action="store_true",
help="Enable Video Terminal (HDMI)")
viopts.add_argument("--with-video-framebuffer",
action="store_true",
help="Enable Video Framebuffer (HDMI)")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(toolchain=args.toolchain,
sys_clk_freq=int(float(args.sys_clk_freq)),
with_ethernet=args.with_ethernet,
with_sata=args.with_sata,
vadj=args.vadj,
with_video_terminal=args.with_video_terminal,
with_video_framebuffer=args.with_video_framebuffer,
**soc_core_argdict(args))
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kwargs = vivado_build_argdict(
args) if args.toolchain == "vivado" else {}
builder.build(**builder_kwargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on PYNQ Z1")
parser.add_argument("--build",
action="store_true",
help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq",
default=125e6,
help="System clock frequency.")
parser.add_argument("--with-video-terminal",
action="store_true",
help="Enable Video Terminal (HDMI).")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
with_video_terminal=args.with_video_terminal,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(**vivado_build_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir,
soc.build_name + ".bit"),
device=1)
def main():
parser = argparse.ArgumentParser(
description="LiteX SoC Blackmagic Decklink Intensity Pro 4K.")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq",
default=125e6,
help="System clock frequency (default: 125MHz)")
parser.add_argument("--with-pcie",
action="store_true",
help="Enable PCIe support")
parser.add_argument("--driver",
action="store_true",
help="Generate PCIe driver")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq=int(float(args.sys_clk_freq)),
with_pcie=args.with_pcie | True, # FIXME: Always enable PCIe for now.
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder_kwargs = vivado_build_argdict(args)
builder.build(**builder_kwargs, run=args.build)
if args.driver:
generate_litepcie_software(soc,
os.path.join(builder.output_dir, "driver"))
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on CMOD A7")
parser.add_argument("--toolchain",
default="vivado",
help="FPGA toolchain (vivado or symbiflow).")
parser.add_argument("--build",
action="store_true",
help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--variant",
default="a7-35",
help="Board variant (a7-35 or a7-100).")
parser.add_argument("--sys-clk-freq",
default=48e6,
help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(variant=args.variant,
toolchain=args.toolchain,
sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_core_argdict(args))
builder_argd = builder_argdict(args)
builder = Builder(soc, **builder_argd)
builder_kwargs = vivado_build_argdict(
args) if args.toolchain == "vivado" else {}
builder.build(**builder_kwargs, run=args.build)
def main():
parser = argparse.ArgumentParser(
description="LiteX SoC on QMTECH Wukong Board")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq",
default=100e6,
help="System clock frequency (default: 100MHz)")
ethopts = parser.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet",
action="store_true",
help="Enable Ethernet support")
ethopts.add_argument("--with-etherbone",
action="store_true",
help="Enable Etherbone support")
parser.add_argument("--eth-ip",
default="192.168.1.50",
type=str,
help="Ethernet/Etherbone IP address")
sdopts = parser.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard",
action="store_true",
help="Enable SPI-mode SDCard support")
sdopts.add_argument("--with-sdcard",
action="store_true",
help="Enable SDCard support")
viopts = parser.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal",
action="store_true",
help="Enable Video Terminal (HDMI)")
viopts.add_argument("--with-video-framebuffer",
action="store_true",
help="Enable Video Framebuffer (HDMI)")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
eth_ip=args.eth_ip,
with_video_terminal=args.with_video_terminal,
with_video_framebuffer=args.with_video_framebuffer,
**soc_core_argdict(args))
if args.with_spi_sdcard:
soc.platform.add_extension(qmtech_wukong._sdcard_pmod_io)
soc.add_spi_sdcard()
if args.with_sdcard:
soc.platform.add_extension(qmtech_wukong._sdcard_pmod_io)
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder.build(**vivado_build_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on SDS1104X-E")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
viopts = parser.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_etherbone = args.with_etherbone,
eth_ip = args.eth_ip,
with_video_terminal = args.with_video_terminal,
with_video_framebuffer = args.with_video_framebuffer,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder.build(**vivado_build_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"), device=1)
def main():
parser = common.ArgumentParser(
description="LiteX SoC on Arty A7",
sys_clk_freq='100e6',
module='MT41K128M16',
)
g = parser.add_argument_group(title="Arty A7")
parser.add(g,
"--toolchain",
default="vivado",
choices=['vivado', 'symbiflow'],
help="Gateware toolchain to use")
parser.add(g,
"--variant",
default="a7-35",
choices=['a7-35', 'a7-100'],
help="FPGA variant")
vivado_build_args(g)
args = parser.parse_args()
soc_kwargs = common.get_soc_kwargs(args)
soc = SoC(variant=args.variant, toolchain=args.toolchain, **soc_kwargs)
target_name = 'arty'
builder_kwargs = common.get_builder_kwargs(args, target_name=target_name)
builder = Builder(soc, **builder_kwargs)
build_kwargs = vivado_build_argdict(args) if not args.sim else {}
common.run(args, builder, build_kwargs, target_name=target_name)
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arty Z7")
parser.add_argument("--toolchain", default="vivado", help="FPGA toolchain (vivado, symbiflow or yosys+nextpnr).")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--variant", default="z7-20", help="Board variant (z7-20 or z7-10).")
parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
parser.set_defaults(cpu_type="zynq7000")
args = parser.parse_args()
soc = BaseSoC(
variant = args.variant,
toolchain = args.toolchain,
sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {}
builder.build(**builder_kwargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Alinx AXU2CGA")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--cable",
default="ft232",
help="JTAG interface.")
target_group.add_argument("--sys-clk-freq",
default=25e6,
help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
parser.set_defaults(cpu_type="zynqmp")
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
if args.cpu_type == "zynqmp":
soc.builder = builder
builder.add_software_package('libxil')
builder.add_software_library('libxil')
builder.build(**vivado_build_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer(args.cable)
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Zedboard")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq",
default=100e6,
help="System clock frequency (default: 100MHz)")
parser.add_argument(
"--board",
default="redpitaya14",
help="Board type: redpitaya14 (default) or redpitaya16")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(board=args.board,
sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(**vivado_build_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir,
soc.build_name + ".bit"),
device=1)
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Ztex 2.13")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--expansion", default="debug", help="Expansion board, 'debug' (default) or 'sbus'")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default=100MHz)")
parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
builder_args(parser)
soc_sdram_args(parser)
#soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), expansion=args.expansion, **soc_sdram_argdict(args))
assert not (args.with_spi_sdcard and args.with_sdcard)
if args.with_spi_sdcard:
soc.add_spi_sdcard() #sbus only
if args.with_sdcard:
soc.add_sdcard() #sbus only
builder = Builder(soc, **builder_argdict(args))
builder.build(**vivado_build_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Mimas A7")
parser.add_argument("--build",
action="store_true",
help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq",
default=100e6,
help="System clock frequency.")
parser.add_argument("--with-ethernet",
action="store_true",
help="Enable Ethernet support.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
with_ethernet=args.with_ethernet,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(**vivado_build_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(
description="LiteX SoC on Spartan Edge Accelerator")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--sys-clk-freq",
default=100e6,
help="System clock frequency.")
target_group.add_argument("--with-jtagbone",
action="store_true",
help="Enable Jtagbone support.")
target_group.add_argument("--with-video-terminal",
action="store_true",
help="Enable Video Colorbars (HDMI).")
target_group.add_argument("--with-neopixel",
action="store_true",
help="Enable onboard 2 Neopixels Leds.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
with_jtagbone=args.with_jtagbone,
with_video_terminal=args.with_video_terminal,
with_neopixel=args.with_neopixel,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder_kwargs = vivado_build_argdict(args)
builder.build(**builder_kwargs, run=args.build)
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
builder_args(parser)
soc_sdram_args(parser)
vivado_build_args(parser)
parser.add_argument("--with-ethernet",
action="store_true",
help="Enable Ethernet support")
parser.add_argument("--with-etherbone",
action="store_true",
help="Enable Etherbone support")
parser.add_argument("--with-spiflash",
action="store_true",
help="Enable SPIFlash support")
args = parser.parse_args()
assert not (args.with_ethernet and args.with_etherbone)
soc = BaseSoC(with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
with_spiflash=args.with_spiflash,
**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(**vivado_build_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arty S7")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--variant",
default="s7-50",
help="Board variant: s7-50 (default) or s7-25")
parser.add_argument("--sys-clk-freq",
default=100e6,
help="System clock frequency (default: 100MHz)")
parser.add_argument("--with-spi-flash",
action="store_true",
help="Enable SPI Flash (MMAPed)")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(variant=args.variant,
sys_clk_freq=int(float(args.sys_clk_freq)),
with_spi_flash=args.with_spi_flash,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(**vivado_build_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main():
parser = common.ArgumentParser(
description="LiteX SoC on DDR4 Datacenter Test Board",
sys_clk_freq='50e6',
module='MTA18ASF2G72PZ')
g = parser.add_argument_group(title="DDR4 Datacenter Test Board")
parser.add(g,
"--eth-reset-time",
default="10e-3",
help="Duration of Ethernet PHY reset")
parser.add(g,
"--iodelay-clk-freq",
default="200e6",
help="IODELAY clock frequency")
vivado_build_args(g)
args = parser.parse_args()
soc_kwargs = common.get_soc_kwargs(args)
soc = SoC(**soc_kwargs)
target_name = 'ddr4_datacenter_test_board'
builder_kwargs = common.get_builder_kwargs(args, target_name=target_name)
builder = Builder(soc, **builder_kwargs)
build_kwargs = vivado_build_argdict(args) if not args.sim else {}
common.run(args, builder, build_kwargs, target_name=target_name)
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument(
"--toolchain",
default="vivado",
help="Gateware toolchain to use, vivado (default) or symbiflow")
builder_args(parser)
soc_sdram_args(parser)
vivado_build_args(parser)
parser.add_argument("--with-ethernet",
action="store_true",
help="Enable Ethernet support")
parser.add_argument("--with-etherbone",
action="store_true",
help="Enable Etherbone support")
args = parser.parse_args()
assert not (args.with_ethernet and args.with_etherbone)
soc = BaseSoC(args.toolchain,
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder_kwargs = vivado_build_argdict(
args) if args.toolchain == "vivado" else {}
builder.build(**builder_kwargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on SDS1104X-E")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq",
default=100e6,
help="System clock frequency (default: 100MHz)")
parser.add_argument("--with-etherbone",
action="store_true",
help="Enable Etherbone support")
parser.add_argument("--eth-ip",
default="192.168.1.50",
type=str,
help="Ethernet/Etherbone IP address")
builder_args(parser)
soc_sdram_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
with_etherbone=args.with_etherbone,
eth_ip=args.eth_ip,
**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(**vivado_build_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir,
soc.build_name + ".bit"),
device=1)
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Alinx AXU2CGA")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--cable", default="ft232", help="JTAG interface.")
parser.add_argument("--sys-clk-freq", default=25e6, help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
parser.set_defaults(cpu_type="zynqmp")
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
if args.cpu_type == "zynqmp":
soc.builder = builder
builder.add_software_package('libxil')
builder.add_software_library('libxil')
builder.build(**vivado_build_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer(args.cable)
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Trenz TE0725")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--flash", action="store_true", help="Flash bitstream")
parser.add_argument("--sys-clk-freq",
default=100e6,
help="System clock frequency (default: 100MHz)")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(**vivado_build_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
if args.flash:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".bin"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Arty Z7")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--toolchain", default="vivado", help="FPGA toolchain (vivado, symbiflow or yosys+nextpnr).")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--variant", default="z7-20", help="Board variant (z7-20 or z7-10).")
target_group.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
parser.set_defaults(cpu_type="zynq7000")
parser.set_defaults(no_uart=True)
args = parser.parse_args()
soc = BaseSoC(
variant = args.variant,
toolchain = args.toolchain,
sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {}
builder.build(**builder_kwargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"), device=1)
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
builder_args(parser)
soc_sdram_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
assert not (args.with_ethernet and args.with_etherbone)
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
**soc_sdram_argdict(args)
)
assert not (args.with_spi_sdcard and args.with_sdcard)
soc.platform.add_extension(arty._sdcard_pmod_io)
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder.build(**vivado_build_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
parser.add_argument("--toolchain", default="vivado", help="Toolchain use to build (default: vivado)")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--variant", default="a7-35", help="Board variant: a7-35 (default) or a7-100")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
ethopts = parser.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address")
parser.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting")
sdopts = parser.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
parser.add_argument("--sdcard-adapter", type=str, help="SDCard PMOD adapter: digilent (default) or numato")
parser.add_argument("--no-ident-version", action="store_false", help="Disable build time output")
parser.add_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed)")
parser.add_argument("--with-pmod-gpio", action="store_true", help="Enable GPIOs through PMOD") # FIXME: Temporary test.
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
assert not (args.with_etherbone and args.eth_dynamic_ip)
soc = BaseSoC(
variant = args.variant,
toolchain = args.toolchain,
sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
eth_ip = args.eth_ip,
eth_dynamic_ip = args.eth_dynamic_ip,
ident_version = args.no_ident_version,
with_jtagbone = args.with_jtagbone,
with_spi_flash = args.with_spi_flash,
with_pmod_gpio = args.with_pmod_gpio,
**soc_core_argdict(args)
)
if args.sdcard_adapter == "numato":
soc.platform.add_extension(arty._numato_sdcard_pmod_io)
else:
soc.platform.add_extension(arty._sdcard_pmod_io)
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {}
builder.build(**builder_kwargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
