def __init__(self,
platform,
clk_freq,
cpu_type="lm32",
cpu_reset_address=0x00000000,
integrated_rom_size=0,
integrated_sram_size=4096,
integrated_main_ram_size=0,
shadow_base=0x80000000,
csr_data_width=8,
csr_address_width=14,
with_uart=True,
uart_baudrate=115200,
ident="",
with_timer=True):
self.platform = platform
self.clk_freq = clk_freq
self.cpu_type = cpu_type
if integrated_rom_size:
cpu_reset_address = 0
self.cpu_reset_address = cpu_reset_address
self.integrated_rom_size = integrated_rom_size
self.integrated_sram_size = integrated_sram_size
self.integrated_main_ram_size = integrated_main_ram_size
self.with_uart = with_uart
self.uart_baudrate = uart_baudrate
self.shadow_base = shadow_base
self.csr_data_width = csr_data_width
self.csr_address_width = csr_address_width
self._memory_regions = [] # list of (name, origin, length)
self._csr_regions = [
] # list of (name, origin, busword, csr_list/Memory)
self._constants = [] # list of (name, value)
self._wb_masters = []
self._wb_slaves = []
if cpu_type is not None:
if cpu_type == "lm32":
self.add_cpu_or_bridge(
lm32.LM32(platform, self.cpu_reset_address))
elif cpu_type == "or1k":
self.add_cpu_or_bridge(
mor1kx.MOR1KX(platform, self.cpu_reset_address))
elif cpu_type == "riscv32":
self.add_cpu_or_bridge(
picorv32.PicoRV32(platform, self.cpu_reset_address))
else:
raise ValueError("Unsupported CPU type: {}".format(cpu_type))
self.add_wb_master(self.cpu_or_bridge.ibus)
self.add_wb_master(self.cpu_or_bridge.dbus)
if integrated_rom_size:
self.submodules.rom = wishbone.SRAM(integrated_rom_size,
read_only=True)
self.register_rom(self.rom.bus, integrated_rom_size)
if integrated_sram_size:
self.submodules.sram = wishbone.SRAM(integrated_sram_size)
self.register_mem("sram", self.mem_map["sram"], self.sram.bus,
integrated_sram_size)
# Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping.
if integrated_main_ram_size:
self.submodules.main_ram = wishbone.SRAM(integrated_main_ram_size)
self.register_mem("main_ram", self.mem_map["main_ram"],
self.main_ram.bus, integrated_main_ram_size)
self.submodules.wishbone2csr = wishbone2csr.WB2CSR(
bus_csr=csr_bus.Interface(csr_data_width, csr_address_width))
self.register_mem("csr", self.mem_map["csr"],
self.wishbone2csr.wishbone)
if with_uart:
self.submodules.uart_phy = uart.RS232PHY(
platform.request("serial"), clk_freq, uart_baudrate)
self.submodules.uart = uart.UART(self.uart_phy)
if ident:
self.submodules.identifier = identifier.Identifier(ident)
self.add_constant("SYSTEM_CLOCK_FREQUENCY", int(clk_freq))
if with_timer:
self.submodules.timer0 = timer.Timer()
def __init__(self,
platform,
clk_freq,
cpu_type="lm32",
cpu_reset_address=0x00000000,
cpu_variant=None,
integrated_rom_size=0,
integrated_rom_init=[],
integrated_sram_size=4096,
integrated_main_ram_size=0,
integrated_main_ram_init=[],
shadow_base=0x80000000,
csr_data_width=8,
csr_address_width=14,
with_uart=True,
uart_name="serial",
uart_baudrate=115200,
uart_stub=False,
ident="",
ident_version=False,
reserve_nmi_interrupt=True,
with_timer=True):
self.config = dict()
self.platform = platform
self.clk_freq = clk_freq
self.cpu_type = cpu_type
self.cpu_variant = cpu_variant
if integrated_rom_size:
cpu_reset_address = self.mem_map["rom"]
self.cpu_reset_address = cpu_reset_address
self.config["CPU_RESET_ADDR"] = self.cpu_reset_address
self.integrated_rom_size = integrated_rom_size
self.integrated_rom_initialized = integrated_rom_init != []
self.integrated_sram_size = integrated_sram_size
self.integrated_main_ram_size = integrated_main_ram_size
self.with_uart = with_uart
self.uart_baudrate = uart_baudrate
self.shadow_base = shadow_base
self.csr_data_width = csr_data_width
self.csr_address_width = csr_address_width
self._memory_regions = [] # list of (name, origin, length)
self._csr_regions = [
] # list of (name, origin, busword, csr_list/Memory)
self._constants = [] # list of (name, value)
self._wb_masters = []
self._wb_slaves = []
if cpu_type is not None:
if cpu_type == "lm32":
self.add_cpu_or_bridge(
lm32.LM32(platform, self.cpu_reset_address,
self.cpu_variant))
elif cpu_type == "or1k":
self.add_cpu_or_bridge(
mor1kx.MOR1KX(platform, self.cpu_reset_address,
self.cpu_variant))
elif cpu_type == "riscv32":
self.add_cpu_or_bridge(
picorv32.PicoRV32(platform, self.cpu_reset_address,
self.cpu_variant))
else:
raise ValueError("Unsupported CPU type: {}".format(cpu_type))
self.add_wb_master(self.cpu_or_bridge.ibus)
self.add_wb_master(self.cpu_or_bridge.dbus)
self.config["CPU_TYPE"] = str(cpu_type).upper()
if self.cpu_variant:
self.config["CPU_VARIANT"] = str(cpu_type).upper()
if integrated_rom_size:
self.submodules.rom = wishbone.SRAM(integrated_rom_size,
read_only=True,
init=integrated_rom_init)
self.register_rom(self.rom.bus, integrated_rom_size)
if integrated_sram_size:
self.submodules.sram = wishbone.SRAM(integrated_sram_size)
self.register_mem("sram", self.mem_map["sram"], self.sram.bus,
integrated_sram_size)
# Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping.
if integrated_main_ram_size:
self.submodules.main_ram = wishbone.SRAM(
integrated_main_ram_size, init=integrated_main_ram_init)
self.register_mem("main_ram", self.mem_map["main_ram"],
self.main_ram.bus, integrated_main_ram_size)
self.submodules.wishbone2csr = wishbone2csr.WB2CSR(
bus_csr=csr_bus.Interface(csr_data_width, csr_address_width))
self.config["CSR_DATA_WIDTH"] = csr_data_width
self.add_constant("CSR_DATA_WIDTH", csr_data_width)
self.register_mem("csr", self.mem_map["csr"],
self.wishbone2csr.wishbone)
if reserve_nmi_interrupt:
self.soc_interrupt_map[
"nmi"] = 0 # Reserve zero for "non-maskable interrupt"
if with_uart:
if uart_stub:
self.submodules.uart = uart.UARTStub()
else:
self.submodules.uart_phy = uart.RS232PHY(
platform.request(uart_name), clk_freq, uart_baudrate)
self.submodules.uart = uart.UART(self.uart_phy)
#else:
# del self.soc_interrupt_map["uart"]
if ident:
if ident_version:
ident = ident + " " + version()
self.submodules.identifier = identifier.Identifier(ident)
self.config["CLOCK_FREQUENCY"] = int(clk_freq)
self.add_constant("SYSTEM_CLOCK_FREQUENCY", int(clk_freq))
if with_timer:
self.submodules.timer0 = timer.Timer()
else:
del self.soc_interrupt_map["timer0"]
# Invert the interrupt map.
interrupt_rmap = {}
for mod_name, interrupt in self.interrupt_map.items():
assert interrupt not in interrupt_rmap, (
"Interrupt vector conflict for IRQ %s, user defined %s conflicts with user defined %s"
% (interrupt, mod_name, interrupt_rmap[interrupt]))
interrupt_rmap[interrupt] = mod_name
# Add the base SoC's interrupt map
for mod_name, interrupt in self.soc_interrupt_map.items():
assert interrupt not in interrupt_rmap, (
"Interrupt vector conflict for IRQ %s, user defined %s conflicts with SoC inbuilt %s"
% (interrupt, mod_name, interrupt_rmap[interrupt]))
self.interrupt_map[mod_name] = interrupt
interrupt_rmap[interrupt] = mod_name
# Make sure other functions are not using this value.
self.soc_interrupt_map = None
# Make the interrupt vector read only
self.interrupt_map = ReadOnlyDict(self.interrupt_map)
# Save the interrupt reverse map
self.interrupt_rmap = ReadOnlyDict(interrupt_rmap)
