def __init__(self, **kwargs): super().__init__(**kwargs) self.platform.add_extension(ltc.ltc_pads) self.submodules.lvds = LTCPhy(self.platform, self.sys_clk_freq, 120e6) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.lvds.pads_dco) # Frequency counter for received sample clock self.submodules.f_sample = FreqMeter(self.sys_clk_freq) self.comb += self.f_sample.clk.eq(ClockSignal("sample")) spi_pads = self.platform.request("LTC_SPI") self.submodules.spi = spi.SPIMaster(spi_pads, 16, self.sys_clk_freq, self.sys_clk_freq / 32) width, depth = 16 * 2, 8192 storage = Memory(width, depth, init=[0x1234, 0xCAFECAFE, 0x00C0FFEE]) self.specials += storage self.submodules.adc_data_buffer = wishbone.SRAM(storage, read_only=True) port = storage.get_port(write_capable=True, clock_domain="sample") self.register_mem("adc_data_buffer", 0x10000000, self.adc_data_buffer.bus, depth * 8) self.specials += port self.submodules.acq = DumpToRAM(width, depth, port) self.sync.sample += self.acq.adc_data.eq( Cat(Signal(2), self.lvds.sample_outs[0], Signal(2), self.lvds.sample_outs[1])) self.sync += self.lvds.init_running.eq(self.ctrl.reset) for p in LTCSocDev.csr_peripherals: self.add_csr(p)
def add_csr(self): # Add frequency-meter to 156.25 MHz reference clock self.submodules.f_coreclk = FreqMeter(period=int(self.sys_clk_freq), width=4, clk=ClockSignal('eth_tx')) # Config / Status CSRs self.status = CSRStatus(len(self.status_vector)) # 536 bit config reg is very challenging for the synthesizer # self.configuration = CSRStorage(len(self.configuration_vector)) self.comb += [ self.status.status.eq(self.status_vector), # self.configuration_vector.eq(self.configuration.storage) ]
def __init__(self, **kwargs): super().__init__(with_led_chaser=False, **kwargs) self.user_leds = user_leds = [self.platform.request("user_led", i) for i in range(8)] self.counter = counter = Signal(27) self.sync += counter.eq(counter+1) self.comb += user_leds[0].eq(counter[26]) self.add_xgmii() self.submodules.f_sample = FreqMeter(self.sys_clk_freq) self.comb += self.f_sample.clk.eq(self.xgmii.cd_clkmgt.clk) self.add_csr('f_sample') # xg_counter = Signal(27) # self.sync.xxv_eth_tx += xg_counter.eq(xg_counter+1) counter_mgt = Signal(27) self.sync.clkmgt += counter_mgt.eq(counter_mgt+1) self.comb += user_leds[2].eq(counter_mgt[26]) # self.submodules.udp_core = LiteEthUDPIPCore(self.ethphy, # 0x112233445566, # convert_ip("192.168.1.11"), # self.sys_clk_freq) # self.add_csr("udp_core") # self.submodules.etherbone = LiteEthEtherbone(self.udp_core.udp, 1234) # self.add_wb_master(self.etherbone.wishbone.bus) serial = self.platform.request("serial") self.submodules.uart = uart.UARTWishboneBridge( serial, self.clk_freq, baudrate=115200 ) self.add_wb_master(self.uart.wishbone) # self.platform.add_ip("tengbe.tcl") self.platform.add_ip("ip/ten_gig_eth_pcs_pma_0.xci") self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/self.sys_clk_freq)
def __init__(self, platform, with_cpu=True, with_sdram=True, with_etherbone=True, with_gtp=True, gtp_connector="pcie", gtp_refclk="pcie", gtp_linerate=5e9, with_gtp_bist=True, with_gtp_freqmeter=True, with_record=True): sys_clk_freq = int(100e6) # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__( self, platform, sys_clk_freq, cpu_type="vexriscv" if with_cpu else None, csr_data_width=32, with_uart=with_cpu, uart_name="crossover", integrated_rom_size=0x8000 if with_cpu else 0x0000, integrated_main_ram_size=0x1000 if not with_sdram else 0x0000, ident="PCIe Analyzer LiteX SoC", ident_version=True) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") sdram_module = K4B2G1646F(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, geom_settings=sdram_module.geom_settings, timing_settings=sdram_module.timing_settings) # Etherbone -------------------------------------------------------------------------------- if with_etherbone: # ethphy self.submodules.ethphy = LiteEthPHYRMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") # ethcore self.submodules.ethcore = LiteEthUDPIPCore( phy=self.ethphy, mac_address=0x10e2d5000000, ip_address="192.168.1.50", clk_freq=self.clk_freq) # etherbone self.submodules.etherbone = LiteEthEtherbone( self.ethcore.udp, 1234) self.add_wb_master(self.etherbone.wishbone.bus) # timing constraints self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9 / 50e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9 / 50e6) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk) # GTP RefClk ------------------------------------------------------------------------------- if with_gtp: assert gtp_refclk in ["pcie", "internal"] if gtp_refclk == "pcie": refclk = Signal() refclk_freq = 100e6 refclk_pads = platform.request("pcie_refclk") self.specials += Instance("IBUFDS_GTE2", i_CEB=0, i_I=refclk_pads.p, i_IB=refclk_pads.n, o_O=refclk) else: refclk = Signal() refclk_freq = 100e6 self.comb += refclk.eq(ClockSignal("clk100")) platform.add_platform_command( "set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]" ) # GTP PLL ---------------------------------------------------------------------------------- if with_gtp: qpll = GTPQuadPLL(refclk, refclk_freq, gtp_linerate) print(qpll) self.submodules += qpll # GTPs ------------------------------------------------------------------------------------- if with_gtp: for i in range(2): tx_pads = platform.request(gtp_connector + "_tx", i) rx_pads = platform.request(gtp_connector + "_rx", i) gtp = GTP(qpll, tx_pads, rx_pads, sys_clk_freq, data_width=20, clock_aligner=False, tx_buffer_enable=True, rx_buffer_enable=True) gtp.add_stream_endpoints() setattr(self.submodules, "gtp" + str(i), gtp) platform.add_period_constraint(gtp.cd_tx.clk, 1e9 / gtp.tx_clk_freq) platform.add_period_constraint(gtp.cd_rx.clk, 1e9 / gtp.rx_clk_freq) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, gtp.cd_tx.clk, gtp.cd_rx.clk) # GTPs FreqMeters -------------------------------------------------------------------------- if with_gtp_freqmeter: self.submodules.gtp0_tx_freq = FreqMeter(ClockSignal("gtp0_tx")) self.submodules.gtp0_rx_freq = FreqMeter(ClockSignal("gtp0_rx")) self.submodules.gtp1_tx_freq = FreqMeter(ClockSignal("gtp1_tx")) self.submodules.gtp1_rx_freq = FreqMeter(ClockSignal("gtp1_rx")) self.add_csr("gtp0_tx_freq") self.add_csr("gtp0_rx_freq") self.add_csr("gtp1_tx_freq") self.add_csr("gtp1_rx_freq") # GTPs BIST -------------------------------------------------------------------------------- if with_gtp_bist: self.submodules.gtp0_tx_bist = GTPTXBIST(self.gtp0, "gtp0_tx") self.submodules.gtp0_rx_bist = GTPRXBIST(self.gtp0, "gtp0_rx") self.submodules.gtp1_tx_bist = GTPTXBIST(self.gtp1, "gtp1_tx") self.submodules.gtp1_rx_bist = GTPRXBIST(self.gtp1, "gtp1_rx") self.add_csr("gtp0_tx_bist") self.add_csr("gtp0_rx_bist") self.add_csr("gtp1_tx_bist") self.add_csr("gtp1_rx_bist") # Record ----------------------------------------------------------------------------------- # FIXME: use better data/ctrl packing (or separate recorders) if with_record: # Convert RX stream from 16-bit@250MHz to 64-bit@sys_clk rx_converter = stream.StrideConverter([("data", 16), ("ctrl", 2)], [("data", 96), ("ctrl", 12)], reverse=False) rx_converter = ClockDomainsRenamer("gtp0_rx")(rx_converter) self.submodules.rx_converter = rx_converter rx_cdc = stream.AsyncFIFO([("data", 96), ("ctrl", 12)], 8, buffered=True) rx_cdc = ClockDomainsRenamer({ "write": "gtp0_rx", "read": "sys" })(rx_cdc) self.submodules.rx_cdc = rx_cdc # RX DMA Recorder self.submodules.rx_dma_recorder = LiteDRAMDMAWriter( self.sdram.crossbar.get_port("write", 128)) self.rx_dma_recorder.add_csr() self.add_csr("rx_dma_recorder") self.comb += [ gtp.source.connect(rx_converter.sink), rx_converter.source.connect(rx_cdc.sink), self.rx_dma_recorder.sink.valid.eq(rx_cdc.source.valid), self.rx_dma_recorder.sink.data[0:96].eq(rx_cdc.source.data), self.rx_dma_recorder.sink.data[96:108].eq(rx_cdc.source.ctrl), ]
def __init__(self, platform, *args, **kwargs): BaseSoC.__init__(self, platform, *args, **kwargs) mode = "ycbcr422" if mode == "ycbcr422": dw = 16 elif mode == "rgb": dw = 32 else: raise SystemError("Unknown pixel mode.") pix_freq = 148.50e6 # hdmi in 0 hdmi_in0_pads = platform.request("hdmi_in") self.submodules.hdmi_in0 = HDMIIn( hdmi_in0_pads, self.sdram.crossbar.get_port(mode="write"), fifo_depth=512, device="xc7", ) self.add_csr("hdmi_in0") self.add_csr("hdmi_in0_edid_mem") self.add_interrupt("hdmi_in0") self.submodules.hdmi_in0_freq = FreqMeter(period=self.clk_freq) self.add_csr("hdmi_in0_freq") self.comb += [ self.hdmi_in0_freq.clk.eq(self.hdmi_in0.clocking.cd_pix.clk), hdmi_in0_pads.txen.eq(1) ] self.platform.add_period_constraint(self.hdmi_in0.clocking.cd_pix.clk, period_ns(1 * pix_freq)) self.platform.add_period_constraint( self.hdmi_in0.clocking.cd_pix1p25x.clk, period_ns(1.25 * pix_freq)) self.platform.add_period_constraint( self.hdmi_in0.clocking.cd_pix5x.clk, period_ns(5 * pix_freq)) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.hdmi_in0.clocking.cd_pix.clk, self.hdmi_in0.clocking.cd_pix1p25x.clk, self.hdmi_in0.clocking.cd_pix5x.clk) # hdmi out 0 hdmi_out0_pads = platform.request("hdmi_out") hdmi_out0_dram_port = self.sdram.crossbar.get_port( mode="read", data_width=dw, clock_domain="hdmi_out0_pix", reverse=True, ) self.submodules.hdmi_out0 = VideoOut( platform.device, hdmi_out0_pads, hdmi_out0_dram_port, mode=mode, fifo_depth=4096, ) self.add_csr("hdmi_out0") self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.hdmi_out0.driver.clocking.cd_pix.clk) self.platform.add_period_constraint( self.hdmi_out0.driver.clocking.cd_pix.clk, period_ns(1 * pix_freq)) self.platform.add_period_constraint( self.hdmi_out0.driver.clocking.cd_pix5x.clk, period_ns(5 * pix_freq)) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.hdmi_out0.driver.clocking.cd_pix.clk, self.hdmi_out0.driver.clocking.cd_pix5x.clk) for name, value in sorted(self.platform.hdmi_infos.items()): self.add_constant(name, value)
def __init__(self, platform, with_cpu=True, with_sdram=True, with_etherbone=True, with_pcie=True, with_sdram_dmas=False, with_hdmi_in0=True, with_hdmi_out0=True): sys_clk_freq = int(100e6) # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__( self, platform, sys_clk_freq, cpu_type="vexriscv" if with_cpu else None, cpu_variant="lite", l2_size=128, csr_data_width=32, with_uart=with_cpu, uart_name="crossover", integrated_rom_size=0x8000 if with_cpu else 0x0000, integrated_main_ram_size=0x1000 if not with_sdram else 0x0000, ident="NeTV2 LiteX SoC", ident_version=True) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) self.add_csr("crg") # DNA -------------------------------------------------------------------------------------- self.submodules.dna = DNA() self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk) self.add_csr("dna") # XADC ------------------------------------------------------------------------------------- self.submodules.xadc = XADC() self.add_csr("xadc") # ICAP ------------------------------------------------------------------------------------- self.submodules.icap = ICAP(platform) self.icap.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk) self.add_csr("icap") # Flash ------------------------------------------------------------------------------------ self.submodules.flash = S7SPIFlash(platform.request("flash"), sys_clk_freq, 25e6) self.add_csr("flash") # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") sdram_module = K4B2G1646F(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, geom_settings=sdram_module.geom_settings, timing_settings=sdram_module.timing_settings) # Etherbone -------------------------------------------------------------------------------- if with_etherbone: # ethphy self.submodules.ethphy = LiteEthPHYRMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") # ethcore self.submodules.ethcore = LiteEthUDPIPCore( phy=self.ethphy, mac_address=0x10e2d5000000, ip_address="192.168.1.50", clk_freq=self.clk_freq) # etherbone self.submodules.etherbone = LiteEthEtherbone( self.ethcore.udp, 1234) self.add_wb_master(self.etherbone.wishbone.bus) # timing constraints self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9 / 50e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9 / 50e6) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk) # PCIe ------------------------------------------------------------------------------------- if with_pcie: # PHY ---------------------------------------------------------------------------------- self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), data_width=64, bar0_size=0x20000) platform.add_false_path_constraint(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") # Endpoint ----------------------------------------------------------------------------- self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) # Wishbone bridge ---------------------------------------------------------------------- self.submodules.pcie_bridge = LitePCIeWishboneBridge( self.pcie_endpoint, base_address=self.mem_map["csr"]) self.add_wb_master(self.pcie_bridge.wishbone) # DMA0 --------------------------------------------------------------------------------- self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering=True, buffering_depth=1024, with_loopback=True) self.add_csr("pcie_dma0") # DMA1 --------------------------------------------------------------------------------- self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering=True, buffering_depth=1024, with_loopback=True) self.add_csr("pcie_dma1") self.add_constant("DMA_CHANNELS", 2) # MSI ---------------------------------------------------------------------------------- self.submodules.pcie_msi = LitePCIeMSI() self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, "PCIE_DMA0_READER": self.pcie_dma0.reader.irq, "PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq, "PCIE_DMA1_READER": self.pcie_dma1.reader.irq, } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) # FIXME : Dummy counter capture, connect to HDMI In ------------------------------------ pcie_dma0_counter = Signal(32) self.sync += [ self.pcie_dma0.sink.valid.eq(1), If(self.pcie_dma0.sink.ready, pcie_dma0_counter.eq(pcie_dma0_counter + 1)), self.pcie_dma0.sink.data.eq(pcie_dma0_counter) ] pcie_dma1_counter = Signal(32) self.sync += [ self.pcie_dma1.sink.valid.eq(1), If(self.pcie_dma1.sink.ready, pcie_dma1_counter.eq(pcie_dma1_counter + 2)), self.pcie_dma1.sink.data.eq(pcie_dma1_counter) ] # SDRAM DMAs ------------------------------------------------------------------------------- if with_sdram_dmas: self.submodules.sdram_reader = LiteDRAMDMAReader( self.sdram.crossbar.get_port()) self.sdram_reader.add_csr() self.add_csr("sdram_reader") self.submodules.sdram_writer = LiteDRAMDMAReader( self.sdram.crossbar.get_port()) self.sdram_writer.add_csr() self.add_csr("sdram_writer") # HDMI In 0 -------------------------------------------------------------------------------- if with_hdmi_in0: hdmi_in0_pads = platform.request("hdmi_in", 0) self.submodules.hdmi_in0_freq = FreqMeter(period=sys_clk_freq) self.add_csr("hdmi_in0_freq") self.submodules.hdmi_in0 = HDMIIn( pads=hdmi_in0_pads, dram_port=self.sdram.crossbar.get_port(mode="write"), fifo_depth=512, device="xc7", split_mmcm=True) self.add_csr("hdmi_in0") self.add_csr("hdmi_in0_edid_mem") self.comb += self.hdmi_in0_freq.clk.eq( self.hdmi_in0.clocking.cd_pix.clk), platform.add_false_path_constraints( self.crg.cd_sys.clk, self.hdmi_in0.clocking.cd_pix.clk, self.hdmi_in0.clocking.cd_pix1p25x.clk, self.hdmi_in0.clocking.cd_pix5x.clk) self.platform.add_period_constraint( platform.lookup_request("hdmi_in", 0).clk_p, 1e9 / 74.25e6) # HDMI Out 0 ------------------------------------------------------------------------------- if with_hdmi_out0: self.submodules.hdmi_out0 = VideoOut( device=platform.device, pads=platform.request("hdmi_out", 0), dram_port=self.sdram.crossbar.get_port( mode="read", data_width=16, clock_domain="hdmi_out0_pix", reverse=True), mode="ycbcr422", fifo_depth=512) self.add_csr("hdmi_out0") platform.add_false_path_constraints( self.crg.cd_sys.clk, self.hdmi_out0.driver.clocking.cd_pix.clk, self.hdmi_out0.driver.clocking.cd_pix5x.clk)
def __init__(self, platform, with_sdram=True, with_ethernet=False, with_etherbone=True, with_sdcard=True, with_pcie=False, with_hdmi_in0=False, with_hdmi_out0=False, with_hdmi_in1=False, with_hdmi_out1=False, with_interboard_communication=False): assert not (with_pcie and with_interboard_communication) sys_clk_freq = int(100e6) sd_freq = int(100e6) SoCSDRAM.__init__(self, platform, sys_clk_freq, #cpu_type="vexriscv", l2_size=32, cpu_type=None, l2_size=32, #csr_data_width=8, csr_address_width=14, csr_data_width=32, csr_address_width=14, integrated_rom_size=0x8000, integrated_sram_size=0x4000, integrated_main_ram_size=0x8000 if not with_sdram else 0, ident="NeTV2 LiteX Test SoC", ident_version=True, reserve_nmi_interrupt=False) # crg self.submodules.crg = CRG(platform, sys_clk_freq) # dnax self.submodules.dna = dna.DNA() # xadc self.submodules.xadc = xadc.XADC() # icap self.submodules.icap = ICAP(platform) # flash self.submodules.flash = Flash(platform.request("flash"), div=math.ceil(sys_clk_freq/25e6)) # sdram if with_sdram: self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq, iodelay_clk_freq=200e6) sdram_module = MT41J128M16(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings(with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True)) # ethernet if with_ethernet: self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"), self.platform.request("eth")) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.crg.cd_eth.clk.attr.add("keep") self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.crg.cd_eth.clk) # etherbone if with_etherbone: self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"), self.platform.request("eth")) self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy, 0x10e2d5000000, convert_ip("192.168.1.50"), sys_clk_freq) self.add_cpu(LiteEthEtherbone(self.ethcore.udp, 1234, mode="master")) self.add_wb_master(self.cpu.wishbone.bus) #self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234, mode="master") #self.add_wb_master(self.etherbone.wishbone.bus) self.crg.cd_eth.clk.attr.add("keep") self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.crg.cd_eth.clk) # sdcard self.submodules.sdclk = SDClockerS7() self.submodules.sdphy = SDPHY(platform.request("sdcard"), platform.device) self.submodules.sdcore = SDCore(self.sdphy) self.submodules.sdtimer = Timer() self.submodules.bist_generator = BISTBlockGenerator(random=True) self.submodules.bist_checker = BISTBlockChecker(random=True) self.comb += [ self.sdcore.source.connect(self.bist_checker.sink), self.bist_generator.source.connect(self.sdcore.sink) ] self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq) self.platform.add_period_constraint(self.sdclk.cd_sd.clk, 1e9/sd_freq) self.platform.add_period_constraint(self.sdclk.cd_sd_fb.clk, 1e9/sd_freq) self.crg.cd_sys.clk.attr.add("keep") self.sdclk.cd_sd.clk.attr.add("keep") self.sdclk.cd_sd_fb.clk.attr.add("keep") self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.sdclk.cd_sd.clk, self.sdclk.cd_sd_fb.clk) # pcie if with_pcie: # pcie phy self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x2")) platform.add_false_path_constraints( self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) # pcie endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, with_reordering=True) # pcie wishbone bridge self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1, shadow_base=0x80000000) self.add_wb_master(self.pcie_bridge.wishbone) # pcie dma self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True) # pcie msi self.submodules.pcie_msi = LitePCIeMSI() self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, "PCIE_DMA0_READER": self.pcie_dma0.reader.irq } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) # interboard communication if with_interboard_communication: self.clock_domains.cd_refclk = ClockDomain() self.submodules.refclk_pll = refclk_pll = S7PLL() refclk_pll.register_clkin(platform.lookup_request("clk50"), 50e6) refclk_pll.create_clkout(self.cd_refclk, 125e6) platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]") # qpll qpll = GTPQuadPLL(ClockSignal("refclk"), 125e6, 1.25e9) print(qpll) self.submodules += qpll # gtp gtp = GTP(qpll, platform.request("interboard_comm_tx"), platform.request("interboard_comm_rx"), sys_clk_freq, clock_aligner=True, internal_loopback=False) self.submodules += gtp counter = Signal(32) self.sync.tx += counter.eq(counter + 1) # send counter to other-board self.comb += [ gtp.encoder.k[0].eq(1), gtp.encoder.d[0].eq((5 << 5) | 28), gtp.encoder.k[1].eq(0), gtp.encoder.d[1].eq(counter[26:]) ] # receive counter and display it on leds self.comb += [ platform.request("user_led", 3).eq(gtp.rx_ready), platform.request("user_led", 4).eq(gtp.decoders[1].d[0]), platform.request("user_led", 5).eq(gtp.decoders[1].d[1]) ] gtp.cd_tx.clk.attr.add("keep") gtp.cd_rx.clk.attr.add("keep") platform.add_period_constraint(gtp.cd_tx.clk, 1e9/gtp.tx_clk_freq) platform.add_period_constraint(gtp.cd_rx.clk, 1e9/gtp.tx_clk_freq) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, gtp.cd_tx.clk, gtp.cd_rx.clk) # hdmi in 0 if with_hdmi_in0: hdmi_in0_pads = platform.request("hdmi_in", 0) self.submodules.hdmi_in0_freq = FreqMeter(period=sys_clk_freq) self.submodules.hdmi_in0 = HDMIIn( hdmi_in0_pads, self.sdram.crossbar.get_port(mode="write"), fifo_depth=512, device="xc7", split_mmcm=True) self.comb += self.hdmi_in0_freq.clk.eq(self.hdmi_in0.clocking.cd_pix.clk), for clk in [self.hdmi_in0.clocking.cd_pix.clk, self.hdmi_in0.clocking.cd_pix1p25x.clk, self.hdmi_in0.clocking.cd_pix5x.clk]: self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk) self.platform.add_period_constraint(platform.lookup_request("hdmi_in", 0).clk_p, period_ns(148.5e6)) # hdmi out 0 if with_hdmi_out0: hdmi_out0_dram_port = self.sdram.crossbar.get_port(mode="read", dw=16, cd="hdmi_out0_pix", reverse=True) self.submodules.hdmi_out0 = VideoOut( platform.device, platform.request("hdmi_out", 0), hdmi_out0_dram_port, "ycbcr422", fifo_depth=4096) for clk in [self.hdmi_out0.driver.clocking.cd_pix.clk, self.hdmi_out0.driver.clocking.cd_pix5x.clk]: self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk) # hdmi in 1 if with_hdmi_in1: hdmi_in1_pads = platform.request("hdmi_in", 1) self.submodules.hdmi_in1_freq = FreqMeter(period=sys_clk_freq) self.submodules.hdmi_in1 = HDMIIn( hdmi_in1_pads, self.sdram.crossbar.get_port(mode="write"), fifo_depth=512, device="xc7", split_mmcm=True) self.comb += self.hdmi_in1_freq.clk.eq(self.hdmi_in1.clocking.cd_pix.clk), for clk in [self.hdmi_in1.clocking.cd_pix.clk, self.hdmi_in1.clocking.cd_pix1p25x.clk, self.hdmi_in1.clocking.cd_pix5x.clk]: self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk) self.platform.add_period_constraint(platform.lookup_request("hdmi_in", 1).clk_p, period_ns(148.5e6)) # hdmi out 1 if with_hdmi_out1: hdmi_out1_dram_port = self.sdram.crossbar.get_port(mode="read", dw=16, cd="hdmi_out1_pix", reverse=True) self.submodules.hdmi_out1 = VideoOut( platform.device, platform.request("hdmi_out", 1), hdmi_out1_dram_port, "ycbcr422", fifo_depth=4096) for clk in [self.hdmi_out1.driver.clocking.cd_pix.clk, self.hdmi_out1.driver.clocking.cd_pix5x.clk]: self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk) # led blinking (sys) sys_counter = Signal(32) self.sync.sys += sys_counter.eq(sys_counter + 1) self.comb += platform.request("user_led", 0).eq(sys_counter[26]) # led blinking (pcie) if with_pcie: pcie_counter = Signal(32) self.sync.pcie += pcie_counter.eq(pcie_counter + 1) self.comb += platform.request("user_led", 1).eq(pcie_counter[26]) # led blinking (sdcard) if with_sdcard: sd_counter = Signal(32) self.sync.sd += sd_counter.eq(sd_counter + 1) self.comb += platform.request("user_led", 1).eq(sd_counter[26])
def __init__(self, platform, *args, **kwargs): BaseSoC.__init__(self, platform, csr_data_width=32, *args, **kwargs) sys_clk_freq = int(100e6) # pcie phy self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=32 * 1024 * 1024) self.add_csr("pcie_phy") platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) # pcie endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) # pcie wishbone bridge self.submodules.pcie_bridge = LitePCIeWishboneBridge( self.pcie_endpoint, lambda a: 1, shadow_base=0x40000000) self.submodules.wb_swap = WishboneEndianSwap(self.pcie_bridge.wishbone) self.add_wb_master(self.wb_swap.wishbone) # pcie dma self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True) self.add_csr("pcie_dma0") # pcie msi self.submodules.pcie_msi = LitePCIeMSI() self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, "PCIE_DMA0_READER": self.pcie_dma0.reader.irq } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) # hdmi in 0 hdmi_in0_pads = platform.request("hdmi_in", 0) self.submodules.hdmi_in0_freq = FreqMeter(period=sys_clk_freq) self.add_csr("hdmi_in0_freq") self.submodules.hdmi_in0 = HDMIIn( hdmi_in0_pads, self.sdram.crossbar.get_port(mode="write"), fifo_depth=1024, device="xc7", split_mmcm=True) self.add_csr("hdmi_in0") self.add_csr("hdmi_in0_edid_mem") self.add_interrupt("hdmi_in0") self.comb += self.hdmi_in0_freq.clk.eq( self.hdmi_in0.clocking.cd_pix.clk), for clk in [ self.hdmi_in0.clocking.cd_pix.clk, self.hdmi_in0.clocking.cd_pix1p25x.clk, self.hdmi_in0.clocking.cd_pix5x.clk ]: self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk) self.platform.add_period_constraint( platform.lookup_request("hdmi_in", 0).clk_p, period_ns(148.5e6)) # hdmi out 0 hdmi_out0_dram_port = self.sdram.crossbar.get_port(mode="read", dw=16, cd="hdmi_out0_pix", reverse=True) self.submodules.hdmi_out0 = VideoOut(platform.device, platform.request("hdmi_out", 0), hdmi_out0_dram_port, "ycbcr422", fifo_depth=4096) self.add_csr("hdmi_out0") for clk in [ self.hdmi_out0.driver.clocking.cd_pix.clk, self.hdmi_out0.driver.clocking.cd_pix5x.clk ]: self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk) for name, value in sorted(self.platform.hdmi_infos.items()): self.add_constant(name, value)
def __init__(self, platform, f_sys, f_sample): N_CHANNELS = 4 S = 8 # S = serdes factor D = N_CHANNELS * 2 + 1 # D = number of lanes # outputs 4 x 14 bit twos complement samples self.sample_outs = [Signal((14, True)) for i in range(N_CHANNELS)] ### # Note: LTC2175 streams the MSB first and needs bit-mirroring S7_iserdes.__init__( self, S=S, D=D, # OUT0_A / _B and OUT1_A / _B are in a different clock region! clock_regions=[0, 0, 0, 0, 1, 1, 1, 1, 1], ) self.pads_dco = platform.request("LTC_DCO") self.comb += [ self.dco_p.eq(self.pads_dco.p), self.dco_n.eq(self.pads_dco.n) ] f_dco_clk = f_sample * 4 platform.add_period_constraint(self.pads_dco.p, 1e9 / f_dco_clk) dat_p = [] dat_n = [] for i, sample_out in enumerate(self.sample_outs): # For each ADC channel pads_out = platform.request("LTC_OUT", i) # Wire up the input pads to the serial serdes inputs dat_p.append(pads_out.a_p) dat_p.append(pads_out.b_p) dat_n.append(pads_out.a_n) dat_n.append(pads_out.b_n) # re-arrange parallel serdes outputs to form samples # cut the 2 lowest bits of each channel (always zero) self.comb += sample_out.eq(Cat( myzip(self.data_outs[2 * i + 1], self.data_outs[2 * i])[2:] )) # CSRs for peeking at data patterns # LVDS_B (data_outs[1]) has the LSB and needs to come first! n = 'data_peek{:d}'.format(i) data_peek = CSRStatus(14, name=n) setattr(self, n, data_peek) self.specials += MultiReg( sample_out, data_peek.status ) # Add frame signal to serial inputs pads_frm = platform.request("LTC_FR") dat_p.append(pads_frm.p) dat_n.append(pads_frm.n) self.comb += [ self.lvds_data_p.eq(Cat(dat_p)), self.lvds_data_n.eq(Cat(dat_n)) ] # CSRs for peeking at parallelized frame pattern self.frame_peek = CSRStatus(S) self.specials += MultiReg( self.data_outs[-1], self.frame_peek.status ) # Frequency counter for received sample clock self.submodules.f_sample = FreqMeter(f_sys) # CSR for moving a IDELAY2 up / down self.idelay_inc = CSR(1) self.idelay_dec = CSR(1) self.idelay_value = CSR(5) self.comb += [ self.id_inc.eq(self.idelay_inc.re), self.id_dec.eq(self.idelay_dec.re), self.idelay_value.w.eq(self.id_value) ] # one bitslip control for all ISERDESE2 in all regions # Bitslip pulse crosses clock domains in s7_iserdes.py self.bitslip_csr = CSR(1) self.comb += self.bitslip.eq(self.bitslip_csr.re) self.comb += self.f_sample.clk.eq(ClockSignal("sample"))