def __init__(self, bios_flash_offset, **kwargs): sys_clk_freq = int(24e6) platform = icebreaker.Platform() # Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM. kwargs["integrated_sram_size"] = 0 kwargs["integrated_rom_size"] = 0 # Set CPU variant / reset address kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # 128KB SPRAM (used as SRAM) --------------------------------------------------------------- self.submodules.spram = Up5kSPRAM(size=64*kB) self.register_mem("sram", self.mem_map["sram"], self.spram.bus, 64*kB) # SPI Flash -------------------------------------------------------------------------------- self.submodules.spiflash = SpiFlash(platform.request("spiflash4x"), dummy=6, endianness="little") self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=16*mB) self.add_csr("spiflash") # Add ROM linker region -------------------------------------------------------------------- self.add_memory_region("rom", self.mem_map["spiflash"] + bios_flash_offset, 32*kB, type="cached+linker") # Leds ------------------------------------------------------------------------------------- counter = Signal(32) self.sync += counter.eq(counter + 1) self.comb += platform.request("user_ledr_n").eq(counter[26]) self.comb += platform.request("user_ledg_n").eq(~counter[26])
def __init__(self, device, sys_clk_freq=int(50e6), **kwargs): assert sys_clk_freq == int(50e6) platform = max1000.Platform(device) # SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, # integrated_rom_size=0x8000, # **kwargs) # csr_map_update(SoCSDRAM.csr_map, csr_peripherals) SoCSDRAM.__init__( self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x6000, # integrated_main_ram_size=0x4000, **kwargs) self.mem_map['spiflash'] = 0x20000000 spiflash_pads = platform.request('spiflash') self.add_memory_region("spiflash", self.mem_map["spiflash"], 8 * 1024 * 1024) self.submodules.spiflash = SpiFlash(spiflash_pads, dummy=8, div=4, endianness=self.cpu.endianness) self.add_csr("spiflash") #self.spiflash.add_clk_primitive("xc7"); # 8 MB flash: W74M64FVSSIQ self.add_constant("SPIFLASH_PAGE_SIZE", 256) self.add_constant("SPIFLASH_SECTOR_SIZE", 4096) self.add_constant("FLASH_BOOT_ADDRESS", self.mem_map['spiflash']) # spi_flash.py supports max 16MB linear space self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]), self.spiflash.bus) self.submodules.crg = _CRG(platform) # self.submodules.leds = ClassicLed(Cat(platform.request("user_led", i) for i in range(7))) self.add_csr("leds", allow_user_defined=True) self.submodules.leds = ClassicLed(platform.request("user_led", 0)) # self.add_csr("gpio_leds", allow_user_defined=True) self.add_csr("gpio_leds", allow_user_defined=True) self.submodules.gpio_leds = gpio.GPIOOut(platform.request("gpio_leds")) # use micron device as winbond and ISSI not available if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) sdram_module = MT48LC4M16(self.clk_freq, "1:1") self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings)
def __init__(self, device, sys_clk_freq=int(50e6), **kwargs): assert sys_clk_freq == int(50e6) platform = max1000.Platform(device) SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x6000, **kwargs) self.mem_map['spiflash'] = 0x20000000 spiflash_pads = platform.request('spiflash') self.add_memory_region("spiflash", self.mem_map["spiflash"], 8 * 1024 * 1024) self.submodules.spiflash = SpiFlash(spiflash_pads, dummy=8, div=4, endianness=self.cpu.endianness) self.add_csr("spiflash") # 8 MB flash: W74M64FVSSIQ self.add_constant("SPIFLASH_PAGE_SIZE", 256) self.add_constant("SPIFLASH_SECTOR_SIZE", 4096) self.add_constant("FLASH_BOOT_ADDRESS", self.mem_map['spiflash']) # spi_flash.py supports max 16MB linear space self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]), self.spiflash.bus) self.submodules.crg = _CRG(platform) # self.submodules.leds = ClassicLed(Cat(platform.request("user_led", i) for i in range(7))) self.add_csr("leds", allow_user_defined=True) self.submodules.leds = ClassicLed(platform.request("user_led", 0)) # # self.add_csr("gpio_leds", allow_user_defined=True) # self.submodules.gpio_leds = gpio.GPIOOut(platform.request("gpio_leds")) # use micron device as winbond and ISSI not available if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) sdram_module = MT48LC4M16(self.clk_freq, "1:1") self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings) # include all unused pins as generic BBIO basic IP core bbio_pads = platform.request("bbio") # we can exclue any number of I/O pins to be included self.submodules.bbio = bbioBasic(bbio_pads, exclude=None) self.add_wb_slave(mem_decoder(self.mem_map["bbio"]), self.bbio.bus) self.add_memory_region("bbio", self.mem_map["bbio"], 4 * 4 * 1024)
def add_spi_flash(soc, name="spiflash", mode="4x", dummy_cycles=None, clk_freq=None): # Imports. from litex.soc.cores.spi_flash import SpiFlash # Checks. assert dummy_cycles is not None # FIXME: Get dummy_cycles from SPI Flash assert mode in ["1x", "4x"] if clk_freq is None: clk_freq = soc.clk_freq/2 # FIXME: Get max clk_freq from SPI Flash # Core. soc.check_if_exists(name) spiflash = SpiFlash( pads = soc.platform.request(name if mode == "1x" else name + mode), dummy = dummy_cycles, div = ceil(soc.clk_freq/clk_freq), with_bitbang = True, endianness = soc.cpu.endianness) spiflash.add_clk_primitive(soc.platform.device) setattr(soc.submodules, name, spiflash) spiflash_region = SoCRegion(origin=soc.mem_map.get(name, None), size=0x1000000) # FIXME: Get size from SPI Flash soc.bus.add_slave(name=name, slave=spiflash.bus, region=spiflash_region)
def add_spi_flash(self): # TODO: add spiflash1x support spiflash_pads = self.platform.request("spiflash4x") self.submodules.spiflash = SpiFlash( spiflash_pads, dummy=11, div=2, with_bitbang=True, endianness=self.cpu.endianness) self.spiflash.add_clk_primitive(self.platform.device) self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]), self.spiflash.bus) self.add_memory_region("spiflash", self.mem_map["spiflash"], 0x1000000, type="io") self.add_csr("spiflash")
def __init__(self, **kwargs): EthernetSoC.__init__(self, **kwargs) # flash-rom self.add_constant("FLASH_BOOT_ADDRESS", self.mem_map["spiflash"] + FLASH_BOOT_OFFSET) self.submodules.spiflash = SpiFlash( self.platform.request("spiflash4x"), dummy=11, div=2, with_bitbang=True, endianness=self.cpu.endianness) self.spiflash.add_clk_primitive(self.platform.device) self.add_wb_slave(self.mem_map["spiflash"], self.spiflash.bus, size=self.flash_size) self.add_memory_region("spiflash", self.mem_map["spiflash"], self.flash_size, type="io") self.add_csr("spiflash")
def __init__(self): arty.EthernetSoC.__init__(self, cpu_type="vexriscv", cpu_variant="linux") self.cpu.use_external_variant("VexRiscv.v") self.add_constant("NETBOOT_LINUX_VEXRISCV", None) # machine mode emulator ram self.submodules.emulator_ram = wishbone.SRAM(0x4000) self.register_mem("emulator_ram", self.mem_map["emulator_ram"], self.emulator_ram.bus, 0x4000) # spiflash spiflash_pads = self.platform.request("spiflash4x") spiflash_pads.clk = Signal() self.specials += Instance("STARTUPE2", i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0, i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1) self.submodules.spiflash = SpiFlash(spiflash_pads, dummy=11, div=2, endianness=self.cpu.endianness) self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]), self.spiflash.bus) self.add_memory_region("spiflash", self.mem_map["spiflash"] | self.shadow_base, 0x1000000) self.add_constant("FLASHBOOT_LINUX_VEXRISCV", None) self.add_constant("FLASH_BOOT_ADDRESS", None)
def add_spi_flash(self): # FIXME: only support 7-series for now spiflash_pads = self.platform.request("spiflash4x") spiflash_pads.clk = Signal() self.specials += Instance("STARTUPE2", i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0, i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1) self.submodules.spiflash = SpiFlash(spiflash_pads, dummy=11, div=2, endianness=self.cpu.endianness) self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]), self.spiflash.bus) self.add_memory_region("spiflash", self.mem_map["spiflash"] | self.shadow_base, 0x1000000)
def __init__(self, **kwargs): EthernetSoC.__init__(self, **kwargs) # flash-rom self.add_constant("FLASH_BOOT_ADDRESS", self.mem_map["spiflash"] + FLASH_BOOTROM_OFFSET) self.submodules.spiflash = SpiFlash( self.platform.request("spiflash4x"), dummy=11, div=2, with_bitbang=True, endianness=self.cpu.endianness) self.spiflash.add_clk_primitive(self.platform.device) self.add_wb_slave(self.mem_map["spiflash"], self.spiflash.bus, size=self.flash_size) self.add_memory_region("spiflash", self.mem_map["spiflash"], self.flash_size, type="io") self.add_csr("spiflash") # sd-card if self.fast_sd: self.submodules.sdmmc = SDCard(self.platform, "sdmmc") self.add_wb_master(self.sdmmc.master_bus) self.add_wb_slave(self.mem_map["sdmmc"], self.sdmmc.slave_bus, size=self.sdmmc.get_size()) self.add_memory_region("sdmmc", self.mem_map["sdmmc"], self.sdmmc.get_size(), type="io") self.sdmmc_cmd_irq = self.sdmmc.cmd_irq self.sdmmc_dat_irq = self.sdmmc.dat_irq self.add_interrupt("sdmmc_cmd_irq") self.add_interrupt("sdmmc_dat_irq") else: self.submodules.spim = SPIMaster(self.platform, name="sdspi", busmaster=False) if hasattr(self.spim, "master_bus"): self.add_wb_master(self.spim.master_bus) self.add_wb_slave(self.mem_map["spim"], self.spim.slave_bus, size=self.spim.get_size()) self.add_memory_region("spim", self.mem_map["spim"], self.spim.get_size(), type="io") self.add_csr("spim") self.add_interrupt("spim") # nexys4 special sdpwdn = self.platform.request("sdpwdn") self.comb += sdpwdn.eq(ResetSignal()) # gpio gpio0_signals = Cat(self.platform.request("user_led", 0), self.platform.request("user_led", 1), self.platform.request("user_led", 2), self.platform.request("user_led", 3)) self.submodules.gpio0 = GPIOOut(gpio0_signals) self.add_csr("gpio0") # AES aes = AES(self.platform) self.submodules.aes = aes self.add_wb_slave(self.mem_map["aes"], aes.bus, size=aes.get_size()) self.add_memory_region("aes", self.mem_map["aes"], aes.get_size(), type="io") # SHA1 sha1 = SHA1(self.platform) self.submodules.sha1 = sha1 self.add_wb_slave(self.mem_map["sha1"], sha1.bus, size=sha1.get_size()) self.add_memory_region("sha1", self.mem_map["sha1"], sha1.get_size(), type="io") # test self.submodules.dmatest = DMATest() self.add_wb_master(self.dmatest.master_bus) self.add_csr("dmatest")
def __init__(self, debug, flash_offset, board, revision, with_ethernet=False, with_etherbone=False, eth_phy=0, sys_clk_freq=60e6, use_internal_osc=False, sdram_rate="1:1", **kwargs): """Create a basic SoC for Colorlight 5A-75X. Returns: Newly-constructed SoC """ board = board.lower() assert board in ["5a-75b", "5a-75e"] if board == "5a-75b": platform = colorlight_5a_75b.Platform(revision=revision) elif board == "5a-75e": platform = colorlight_5a_75e.Platform(revision=revision) if board == "5a-75e" and revision == "6.0" and (with_etherbone or with_ethernet): assert use_internal_osc, "You cannot use the 25MHz clock as system clock since it is provided by the Ethernet PHY and will stop during PHY reset." # Set cpu name and variant defaults when none are provided if "cpu_variant" not in kwargs: if debug: kwargs["cpu_variant"] = "imac+debug" else: kwargs["cpu_variant"] = "imac" kwargs["integrated_main_ram_size"] = 0 kwargs["integrated_rom_size"] = 0 kwargs["csr_data_width"] = 32 # Set CPU reset address kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + flash_offset # Select "crossover" as soc uart instead of "serial" # We have to make that selection before calling the parent initializer if debug: kwargs["uart_name"] = "crossover" # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, int(sys_clk_freq), ident="LiteX SoC on Colorlight " + board.upper(), ident_version=True, **kwargs) with_rst = kwargs["uart_name"] not in [ "serial", "bridge", "crossover" ] # serial_rx shared with user_btn_n. with_usb_pll = kwargs.get("uart_name", None) == "usb_acm" self.submodules.crg = _CRG(platform, sys_clk_freq, use_internal_osc=use_internal_osc, with_usb_pll=with_usb_pll, with_rst=with_rst, sdram_rate=sdram_rate) # SDR SDRAM -------------------------------------------------------------------------------- sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY self.submodules.sdrphy = sdrphy_cls(platform.request("sdram")) if board == "5a-75e" and revision == "6.0": sdram_cls = M12L64322A sdram_size = 0x80000000 else: sdram_cls = M12L16161A sdram_size = 0x40000000 self.add_sdram("sdram", phy=self.sdrphy, module=sdram_cls(sys_clk_freq, sdram_rate), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", sdram_size), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # The litex SPI module supports memory-mapped reads, as well as a bit-banged mode # for doing writes. spiflash_size = 32 * 1024 * 1024 self.submodules.spiflash = spiflash = SpiFlash( platform.request("spiflash"), dummy=8, endianness="little") spiflash.add_clk_primitive(platform.device) self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=spiflash_size) self.add_csr("spiflash") # Add ROM linker region self.add_memory_region("rom", self.mem_map["spiflash"] + flash_offset, spiflash_size - flash_offset, type="cached+linker") # In debug mode, add a UART bridge. This takes over from the normal UART bridge, # however you can use the "crossover" UART to communicate with this over the bridge. if debug: self.submodules.uart_bridge = UARTWishboneBridge( platform.request("serial"), sys_clk_freq, baudrate=115200) self.add_wb_master(self.uart_bridge.wishbone) if hasattr(self, "cpu") and self.cpu.name == "vexriscv": self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x100) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks", eth_phy), pads=self.platform.request("eth", eth_phy)) self.add_csr("ethphy") if with_ethernet: self.add_ethernet(phy=self.ethphy) if with_etherbone: self.add_etherbone(phy=self.ethphy)
def __init__(self, sys_clk_freq=int(100e6), spiflash="spiflash_4x", **kwargs): platform = te0725.Platform() SoCCore.__init__( self, platform, clk_freq=sys_clk_freq, ident="TE0725", ident_version=True, integrated_rom_size=0x8000, # integrated_main_ram_size=0x8000, **kwargs) # can we just use the clock without PLL ? self.submodules.crg = _CRG(platform, sys_clk_freq) self.add_csr("spiflash", allow_user_defined=True) spiflash_dummy = { "spiflash_1x": 9, # not tested - need change "spiflash_4x": 6, # works but why? } spiflash_pads = platform.request(spiflash) self.submodules.spiflash = SpiFlash(spiflash_pads, dummy=spiflash_dummy[spiflash], div=4, endianness=self.cpu.endianness) self.spiflash.add_clk_primitive("xc7") #32 Mbyte spansion flash, note there is no pullup on D2, but spi flah ic has internal one? self.add_constant("SPIFLASH_PAGE_SIZE", 256) self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000) # spi_flah.py supports max 16MB linear space self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]), self.spiflash.bus) self.add_memory_region("spiflash", self.mem_map["spiflash"] | self.shadow_base, 16 * 1024 * 1024) hyperram_pads = platform.request("hyperram") self.submodules.hyperram = HyperRAM(hyperram_pads) self.add_wb_slave(mem_decoder(self.mem_map["hyperram"]), self.hyperram.bus) self.add_memory_region("hyperram", self.mem_map["hyperram"] | self.shadow_base, 8 * 1024 * 1024) self.counter = counter = Signal(32) self.sync += counter.eq(counter + 1) # led_red = platform.request("user_led", 0) self.comb += led_red.eq(counter[23])
def __init__(self, flash_offset, sys_clk_freq, **kwargs): """Create a basic SoC for iCEBreaker. Returns: Newly-constructed SoC """ platform = Platform() # Use SERV CPU buy default if "cpu_type" not in kwargs: kwargs["cpu_type"] = "serv" kwargs["cpu_variant"] = "standard" else: if kwargs["cpu_type"] == "vexriscv" and ("cpu_variant" not in kwargs): kwargs["cpu_variant"] = "minimal" # Force the SRAM size to 0, because we add our own SRAM with SPRAM kwargs["integrated_sram_size"] = 0 kwargs["integrated_rom_size"] = 0 # Set CPU reset address kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + flash_offset # SoCCore SoCCore.__init__(self, platform, sys_clk_freq, **kwargs) self.submodules.crg = _CRG(platform, sys_clk_freq) # UP5K has single port RAM, which is a dedicated 128 kilobyte block. # Use this as CPU RAM. spram_size = 128 * 1024 self.submodules.spram = Up5kSPRAM(size=spram_size) self.register_mem("sram", self.mem_map["sram"], self.spram.bus, spram_size) # The litex SPI module supports memory-mapped reads, as well as a bit-banged mode # for doing writes. spiflash_size = 16 * 1024 * 1024 self.submodules.spiflash = SpiFlash(platform.request("spiflash4x"), dummy=6, endianness="little") self.add_csr("spiflash") # SPI flash cache l2_cache_size = 8192 if l2_cache_size != 0: self.submodules.l2_cache = wishbone.Cache( cachesize=l2_cache_size // 4, master=wishbone.Interface(32), slave=self.spiflash.bus, ) self.register_mem("spiflash", self.mem_map["spiflash"], self.l2_cache.master, size=spiflash_size) else: self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=spiflash_size) # Add ROM linker region self.add_memory_region("rom", self.mem_map["spiflash"] + flash_offset, spiflash_size - flash_offset, type="cached+linker") # User button as reset reset_btn = platform.request("user_btn_n") self.comb += self.crg.reset.eq(~reset_btn) # Clock peripheral holds the actual sys_clk frequency self.submodules.clock = ClockPeripheral(sys_clk_freq) self.add_csr("clock") # GPIO peripheral pin_names = ["PMOD1A:%d" % i for i in range(8)] +\ ["PMOD1B:%d" % i for i in range(8)] +\ ["PMOD2:%d" % i for i in range(8)] gpio_extension = [("gpio", i, Pins(name), IOStandard("LVCMOS33")) for i, name in enumerate(pin_names)] platform.add_extension(gpio_extension) gpio = [] for i in range(len(pin_names)): gpio.append(platform.request("gpio")) self.submodules.gpio = GPIOPeripheral(gpio + [ platform.request("user_ledr_n"), platform.request("user_ledg_n"), ]) self.add_csr("gpio") # Suppress synthesis output assert hasattr(self.platform.toolchain, "build_template") if self.platform.toolchain.build_template[0].startswith("yosys "): self.platform.toolchain.build_template[0] = \ self.platform.toolchain.build_template[0].replace("yosys ", "yosys -q ")
def __init__(self, **kwargs): EthernetSoC.__init__(self, **kwargs) self.set_bios_ip("192.168.0.55", "192.168.0.45") # flash-rom self.add_constant("FLASH_BOOT_ADDRESS", self.mem_map["spiflash"] + FLASH_BOOTROM_OFFSET) self.submodules.spiflash = SpiFlash( self.platform.request("spiflash4x"), dummy=6, # see datasheet for dummy cycles div=2, # multiple of 2 with_bitbang=True, endianness=self.cpu.endianness, addr32bit=True) self.spiflash.add_clk_primitive(self.platform.device) self.add_memory_region("spiflash", self.mem_map["spiflash"], self.flash_size, type="io") self.add_wb_slave(self.mem_map["spiflash"], self.spiflash.bus, size=self.flash_size) self.add_csr("spiflash") if self.full_board: if self.fast_sd: self.submodules.sdmmc = SDCard(self.platform, "sdmmc") self.add_wb_master(self.sdmmc.master_bus) self.add_memory_region("sdmmc", self.mem_map["sdmmc"], self.sdmmc.get_size(), type="io") self.add_wb_slave(self.mem_map["sdmmc"], self.sdmmc.slave_bus, size=self.sdmmc.get_size()) self.sdmmc_cmd_irq = self.sdmmc.cmd_irq self.sdmmc_dat_irq = self.sdmmc.dat_irq self.add_interrupt("sdmmc_cmd_irq") self.add_interrupt("sdmmc_dat_irq") else: # SPI0: sd-card self.submodules.spi0 = SPIMaster(self.platform, name="sdspi", busmaster=False) if hasattr(self.spi0, "master_bus"): self.add_wb_master(self.spi0.master_bus) self.add_memory_region("spi0", self.mem_map["spi0"], self.spi0.get_size(), type="io") self.add_wb_slave(self.mem_map["spi0"], self.spi0.slave_bus, size=self.spi0.get_size()) self.add_csr("spi0") self.add_interrupt("spi0") sd_reset = self.platform.request("sd_reset") sd_cd = self.platform.request("sd_cd") self.comb += sd_reset.eq(0) # SPI1: waveshare35a self.submodules.spi1 = SPIMaster(self.platform, name="ws35a_spi", cs_width=2, busmaster=False) if hasattr(self.spi1, "master_bus"): self.add_wb_master((self.spi1.master_bus)) self.add_memory_region("spi1", self.mem_map["spi1"], self.spi1.get_size(), type="io") self.add_wb_slave(self.mem_map["spi1"], self.spi1.slave_bus, size=self.spi1.get_size()) self.add_csr("spi1") self.add_interrupt("spi1") # waveshare35a ws35a_rs = self.platform.request("ws35a_rs") ws35a_reset = self.platform.request("ws35a_reset") ws35a_pendown = self.platform.request("ws35a_int") self.submodules.ws35a = TouchscreenInterrupt(ws35a_pendown) self.add_interrupt("ws35a") # gpio0: leds, ws35a controls board_led = Signal() self.comb += self.platform.request("board_led").eq(~board_led) gpio0_signals = Cat( self.platform.request("user_led", 0), self.platform.request("user_led", 1), self.platform.request("user_led", 2), self.platform.request("user_led", 3), board_led, self.reset, ws35a_rs, ws35a_reset, ) self.submodules.gpio0 = GPIOOut(gpio0_signals) self.add_csr("gpio0") # gpio1: touchscreen pendown, sd-card-detect gpio1_signals = Cat(ws35a_pendown, sd_cd) self.submodules.gpio1 = GPIOIn(gpio1_signals) self.add_csr("gpio1") # timer1 self.submodules.timer1 = Timer() self.add_csr("timer1") self.add_interrupt("timer1") # AES self.submodules.aes = AES(self.platform) self.add_memory_region("aes", self.mem_map["aes"], self.aes.get_size(), type="io") self.add_wb_slave(self.mem_map["aes"], self.aes.bus, size=self.aes.get_size()) # SHA1 self.submodules.sha1 = SHA1(self.platform) self.add_memory_region("sha1", self.mem_map["sha1"], self.sha1.get_size(), type="io") self.add_wb_slave(self.mem_map["sha1"], self.sha1.bus, size=self.sha1.get_size()) # memirq channels # channel 0 self.submodules.to_sel4_master0 = MemIrq() self.add_csr("to_sel4_master0") self.add_interrupt("to_sel4_master0") self.submodules.to_sel4_slave0 = MemIrq() self.add_csr("to_sel4_slave0") self.add_interrupt("to_sel4_slave0") self.submodules.to_linux_master0 = MemIrq() self.add_csr("to_linux_master0") self.add_interrupt("to_linux_master0") self.submodules.to_linux_slave0 = MemIrq() self.add_csr("to_linux_slave0") self.add_interrupt("to_linux_slave0") # channel 1 self.submodules.to_sel4_master1 = MemIrq() self.add_csr("to_sel4_master1") self.add_interrupt("to_sel4_master1") self.submodules.to_sel4_slave1 = MemIrq() self.add_csr("to_sel4_slave1") self.add_interrupt("to_sel4_slave1") self.submodules.to_linux_master1 = MemIrq() self.add_csr("to_linux_master1") self.add_interrupt("to_linux_master1") self.submodules.to_linux_slave1 = MemIrq() self.add_csr("to_linux_slave1") self.add_interrupt("to_linux_slave1") # dma test self.submodules.dmatest = DMATest() self.add_wb_master(self.dmatest.master_bus) self.add_csr("dmatest") self.dts = None
def __init__(self, debug, flash_offset, sys_clk_freq, **kwargs): """Create a basic SoC for iCEBreaker. Create a basic SoC for iCEBreaker. The `sys` frequency will run at 12 MHz. Returns: Newly-constructed SoC """ platform = Platform() # Set cpu name and variant defaults when none are provided if "cpu_variant" not in kwargs: if debug: kwargs["cpu_variant"] = "lite+debug" else: kwargs["cpu_variant"] = "lite" # Force the SRAM size to 0, because we add our own SRAM with SPRAM kwargs["integrated_sram_size"] = 0 kwargs["integrated_rom_size"] = 0 kwargs["csr_data_width"] = 32 # Set CPU reset address kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + flash_offset # Select "crossover" as soc uart instead of "serial" # We have to make that selection before calling the parent initializer if debug: kwargs["uart_name"] = "crossover" # SoCCore SoCCore.__init__(self, platform, sys_clk_freq, **kwargs) self.submodules.crg = _CRG(platform, sys_clk_freq) # UP5K has single port RAM, which is a dedicated 128 kilobyte block. # Use this as CPU RAM. spram_size = 128 * 1024 self.submodules.spram = Up5kSPRAM(size=spram_size) self.register_mem("sram", self.mem_map["sram"], self.spram.bus, spram_size) # The litex SPI module supports memory-mapped reads, as well as a bit-banged mode # for doing writes. spiflash_size = 16 * 1024 * 1024 self.submodules.spiflash = SpiFlash(platform.request("spiflash4x"), dummy=6, endianness="little") self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=spiflash_size) self.add_csr("spiflash") # Add ROM linker region self.add_memory_region("rom", self.mem_map["spiflash"] + flash_offset, spiflash_size - flash_offset, type="cached+linker") # In debug mode, add a UART bridge. This takes over from the normal UART bridge, # however you can use the "crossover" UART to communicate with this over the bridge. if debug: self.submodules.uart_bridge = UARTWishboneBridge( platform.request("serial"), sys_clk_freq, baudrate=115200) self.add_wb_master(self.uart_bridge.wishbone) if hasattr(self, "cpu") and self.cpu.name == "vexriscv": self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x100) platform.add_extension(break_off_pmod) self.submodules.leds = Leds( Cat(platform.request("user_ledr_n"), platform.request("user_ledg_n"), platform.request("user_ledr"), platform.request("user_ledg", 0), platform.request("user_ledg", 1), platform.request("user_ledg", 2), platform.request("user_ledg", 3)), led_polarity=0x03, led_name=[["ledr", "The Red LED on the main iCEBreaker board."], ["ledg", "The Green LED on the main iCEBreaker board."], [ "hledr1", "The center Red LED #1 on the iCEBreaker head." ], ["hledg2", "Green LED #2 on the iCEBreaker head."], ["hledg3", "Green LED #3 on the iCEBreaker head."], ["hledg4", "Green LED #4 on the iCEBreaker head."], ["hledg5", "Green LED #5 on the iCEBreaker head."]]) self.add_csr("leds")
def __init__(self, platform, **kwargs): # TODO Fix the spi flash write speed in bitbang mode #sys_clk_freq = 100.295 * 1000000 sys_clk_freq = 29.498 * 1000000 SoCCore.mem_map = { "rom": 0x00000000, "sram": 0x01000000, "main_ram": 0x40000000, "spiflash": 0x60000000, "csr": 0x82000000, } # SoC with CPU SoCCore.__init__(self, platform, cpu_type="vexriscv", clk_freq=sys_clk_freq, ident="LiteX CPU Test SoC", ident_version=True, integrated_rom_size=0x4000, integrated_main_ram_size=0x2000, uart_name="uart") # Clock Reset Generation self.submodules.crg = CRG(platform.request("clk29"), ~platform.request("buttons")[3]) #self.submodules.crg = _CRG(platform, sys_clk_freq) #self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq) # FPGA identification self.submodules.dna = dna.DNA() self.add_csr("dna") # SPI Flash self.submodules.spiflash = SpiFlash(platform.request("spiflash"), dummy=8, div=4, endianness="little") self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=2 * mB) self.add_csr("spiflash") self.add_constant("SPIFLASH_PAGE_SIZE", 256) self.add_constant("SPIFLASH_SECTOR_SIZE", 4096) self.add_constant("FLASH_BOOT_ADDRESS", self.mem_map['spiflash'] + 0x100000) # Led self.submodules.led = GPIOOut( Cat([ platform.request("green_led"), platform.request("orange_led") ])) self.add_csr("led") # Display 7 Segments self.submodules.display7Seg = SevenSegmentDisplay( sys_clk_freq, platform.request("seven_seg")) self.add_csr("display7Seg") # Encoder self.submodules.encoder = RotaryEncoder(sys_clk_freq, platform.request("encoder")) self.add_csr("encoder") # ST7565 Display # TODO usar o modulo spi.py do LiteX para controlar o display pela CPU displayPins = platform.request("spi_display") self.submodules.display = St7565Display(sys_clk_freq, displayPins) self.add_csr("display")
def __init__(self, simulate, sdram_init=[], with_analyzer=False): self.simulate = simulate if simulate: platform = litex_platform_n64.N64SimPlatform() else: platform = litex_platform_n64.Platform() sys_clk_freq = int(48e6) kwargs = {} kwargs["clk_freq"] = sys_clk_freq kwargs["cpu_type"] = "vexriscv" kwargs["cpu_variant"] = "minimal" kwargs["integrated_rom_size"] = 0 kwargs["integrated_sram_size"] = 2*kB kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset if simulate: kwargs["with_uart"] = False kwargs["with_ethernet"] = False # SoCMini ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, **kwargs) if simulate: self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) self.add_csr("uart") self.add_interrupt("uart") if not self.integrated_main_ram_size: if simulate: sdram_data_width = 16 sdram_module = IS42S16320(sys_clk_freq, "1:1") phy_settings = get_sdram_phy_settings( memtype = sdram_module.memtype, data_width = sdram_data_width, clk_freq = sys_clk_freq) self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings, init=sdram_init) self.add_constant("MEMTEST_DATA_SIZE", 8*1024) self.add_constant("MEMTEST_ADDR_SIZE", 8*1024) else: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) self.add_sdram("sdram", phy = self.sdrphy, module = IS42S16320(sys_clk_freq, "1:1"), origin = self.mem_map["main_ram"], size = kwargs.get("max_sdram_size", 0x4000000), l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), l2_cache_reverse = True ) # CRG -------------------------------------------------------------------------------------- if simulate: self.submodules.crg = CRG(platform.request("sys_clk")) else: self.submodules.crg = _CRG(platform, sys_clk_freq) if simulate: integrated_rom_init = get_mem_data("build/software/bios/bios.bin", "little") self.add_rom("rom", self.cpu.reset_address, len(integrated_rom_init)*4, integrated_rom_init) else: self.submodules.spiflash = SpiFlash(platform.request("spiflash"), dummy=8, endianness="little") self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=8*mB) self.add_csr("spiflash") self.add_memory_region("rom", self.mem_map["spiflash"] + bios_flash_offset, 32*kB, type="cached+linker") # Led -------------------------------------------------------------------------------------- self.submodules.led = GPIOOut(platform.request("io0")) self.add_csr("led") # GPIOs ------------------------------------------------------------------------------------ self.submodules.gpio0 = GPIOOut(platform.request("io1")) self.add_csr("gpio0") self.submodules.gpio1 = GPIOOut(platform.request("io2")) self.add_csr("gpio1") platform.add_extension(_gpios) if with_analyzer: analyzer_signals = [ self.cpu.ibus, self.cpu.dbus ] self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512) self.add_csr("analyzer")