def add_uart(self, name, baudrate=115200):
from litex.soc.cores import uart
if name in ["stub", "stream"]:
self.submodules.uart = uart.UART()
if name == "stub":
self.comb += self.uart.sink.ready.eq(1)
elif name == "bridge":
self.submodules.uart = uart.UARTWishboneBridge(
pads = self.platform.request("serial"),
clk_freq = self.sys_clk_freq,
baudrate = baudrate)
self.bus.add_master(name="uart_bridge", master=self.uart.wishbone)
elif name == "crossover":
self.submodules.uart = uart.UARTCrossover()
else:
if name == "jtag_atlantic":
from litex.soc.cores.jtag import JTAGAtlantic
self.submodules.uart_phy = JTAGAtlantic()
elif name == "jtag_uart":
from litex.soc.cores.jtag import JTAGPHY
self.submodules.uart_phy = JTAGPHY(device=self.platform.device)
else:
self.submodules.uart_phy = uart.UARTPHY(
pads = self.platform.request(name),
clk_freq = self.sys_clk_freq,
baudrate = baudrate)
self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy))
self.csr.add("uart_phy", use_loc_if_exists=True)
self.csr.add("uart", use_loc_if_exists=True)
self.irq.add("uart", use_loc_if_exists=True)
def __init__(self, **kwargs):
print("hello_ETH BaseSoc: ", kwargs)
SoCCore.__init__(
self,
cpu_type=None,
csr_data_width=32,
with_uart=False,
with_timer=False,
integrated_rom_size=0,
integrated_main_ram_size=0,
# integrated_sram_size=0,
ident="SP605 eth demo",
ident_version=True,
**kwargs)
# Serial to Wishbone bridge
self.add_cpu(
uart.UARTWishboneBridge(self.platform.request("serial"),
self.clk_freq,
baudrate=1152000))
self.add_wb_master(self.cpu.wishbone)
# Clock Reset Generation
self.submodules.crg = _CRG(self.platform, self.clk_freq)
# FPGA identification
self.submodules.dna = dna.DNA()
def __init__(self, clk_freq, sample_tx_freq, **kwargs):
print("HelloLtc: ", kwargs)
SoCCore.__init__(
self,
clk_freq=clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
with_timer=False,
integrated_rom_size=0,
integrated_main_ram_size=0,
integrated_sram_size=0,
ident="LTC2175 demonstrator", ident_version=True,
**kwargs
)
p = self.platform
self.submodules.crg = _CRG(p, clk_freq, sample_tx_freq)
# ----------------------------
# Serial to Wishbone bridge
# ----------------------------
self.add_cpu(uart.UARTWishboneBridge(
p.request("serial"),
clk_freq,
baudrate=1152000
))
self.add_wb_master(self.cpu.wishbone)
# FPGA identification
self.submodules.dna = dna.DNA()
# ----------------------------
# FMC LPC connectivity & LTC LVDS driver
# ----------------------------
# LTCPhy will recover ADC clock and drive `sample` clock domain
p.add_extension(ltc_pads)
self.submodules.lvds = LTCPhy(p, sample_tx_freq)
# ----------------------------
# SPI master
# ----------------------------
spi_pads = p.request("LTC_SPI")
self.submodules.spi = spi.SPIMaster(spi_pads)
# ----------------------------
# Acquisition memory for ADC data
# ----------------------------
mem = Memory(16, 4096)
self.specials += mem
self.submodules.sample_ram = SRAM(mem, read_only=True)
self.register_mem("sample", 0x50000000, self.sample_ram.bus, 4096)
self.submodules.acq = Acquisition([mem])
self.specials += MultiReg(
p.request("user_btn"), self.acq.trigger
)
self.comb += [
p.request("user_led").eq(self.acq.busy),
self.acq.data_ins[0].eq(self.lvds.sample_out),
]
def __init__(self, **kwargs):
super().__init__(with_led_chaser=False, **kwargs)
self.user_leds = user_leds = [self.platform.request("user_led", i) for i in range(8)]
self.counter = counter = Signal(27)
self.sync += counter.eq(counter+1)
self.comb += user_leds[0].eq(counter[26])
self.add_xgmii()
self.submodules.f_sample = FreqMeter(self.sys_clk_freq)
self.comb += self.f_sample.clk.eq(self.xgmii.cd_clkmgt.clk)
self.add_csr('f_sample')
# xg_counter = Signal(27)
# self.sync.xxv_eth_tx += xg_counter.eq(xg_counter+1)
counter_mgt = Signal(27)
self.sync.clkmgt += counter_mgt.eq(counter_mgt+1)
self.comb += user_leds[2].eq(counter_mgt[26])
# self.submodules.udp_core = LiteEthUDPIPCore(self.ethphy,
# 0x112233445566,
# convert_ip("192.168.1.11"),
# self.sys_clk_freq)
# self.add_csr("udp_core")
# self.submodules.etherbone = LiteEthEtherbone(self.udp_core.udp, 1234)
# self.add_wb_master(self.etherbone.wishbone.bus)
serial = self.platform.request("serial")
self.submodules.uart = uart.UARTWishboneBridge(
serial,
self.clk_freq,
baudrate=115200
)
self.add_wb_master(self.uart.wishbone)
# self.platform.add_ip("tengbe.tcl")
self.platform.add_ip("ip/ten_gig_eth_pcs_pma_0.xci")
self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/self.sys_clk_freq)
def __init__(self, platform, connector="sma"):
assert connector in ["sma", "pcie"]
sys_clk_freq = int(100e6)
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self, platform, sys_clk_freq,
ident="TdrSoc", ident_version=True)
# CRG --------------------------------------------------------------------------------------
linerate = 2500e6
refclk_from_pll = False
refclk_freq = 156.25e6
crg = CRG(platform, sys_clk_freq, refclk_from_pll, refclk_freq)
self.submodules.crg = crg
# SerDes RefClk ----------------------------------------------------------------------------
if refclk_from_pll:
refclk = self.crg.cd_ref.clk
else:
refclk_pads = platform.request("refclk", 1)
self.comb += platform.request("refclk_en").eq(1)
self.comb += platform.request("refclk_rst_n").eq(1)
refclk = Signal()
self.specials.extref0 = Instance("EXTREFB",
i_REFCLKP=refclk_pads.p,
i_REFCLKN=refclk_pads.n,
o_REFCLKO=refclk,
p_REFCK_PWDNB="0b1",
p_REFCK_RTERM="0b1", # 100 Ohm
)
self.extref0.attr.add(("LOC", "EXTREF0"))
# SerDes PLL -------------------------------------------------------------------------------
serdes_pll = SerDesECP5PLL(
refclk, refclk_freq=refclk_freq, linerate=linerate)
self.submodules += serdes_pll
# SerDes -----------------------------------------------------------------------------------
tx_pads = platform.request(connector + "_tx")
rx_pads = platform.request(connector + "_rx")
channel = 1 if connector == "sma" else 0
serdes = SerDesECP5(serdes_pll, tx_pads, rx_pads,
channel=channel,
data_width=20)
serdes.add_base_control()
self.submodules.serdes = serdes
self.add_csr("serdes")
platform.add_period_constraint(serdes.txoutclk, 1e9/serdes.tx_clk_freq)
platform.add_period_constraint(serdes.rxoutclk, 1e9/serdes.rx_clk_freq)
self.clock_domains.cd_tx = ClockDomain(reset_less=True)
self.comb += self.cd_tx.clk.eq(serdes.txoutclk)
self.clock_domains.cd_rx = ClockDomain(reset_less=True)
self.comb += self.cd_rx.clk.eq(serdes.rxoutclk)
# DAC
spi_pads = platform.request("spidac_io")
spi_master = spi.SPIMaster(spi_pads, 16, sys_clk_freq, 1e6)
self.submodules.spidac = spi_master
self.add_csr("spidac")
# DAQ --------------------------------------------------------------------------------------
mem_depth = 256
data_width = 20
daq = Daq(tx_clk=serdes.rxoutclk, tx_data=serdes.tx_data, rx_clk=serdes.rxoutclk,
rx_data=serdes.rx_data, data_width=data_width, mem_depth=mem_depth)
self.submodules.daq = daq
self.comb += serdes.ldr_tx_data.eq(daq.tx)
# define the memory region size/location
# memdepth is the depth of the memory inferred in your logic block
# the length is in bytes, so for example if the data_width of your memory
# block is 32 bits, the total length is memdepth * 4
self.add_memory_region(
"daq_memory", self.mem_map["daq_memory"], mem_depth * data_width//8)
# add the wishbone slave mapping to the mem_map entry made above
self.add_wb_slave(self.mem_map["daq_memory"], self.daq.bus)
self.add_csr("daq")
# Leds -------------------------------------------------------------------------------------
sys_counter = Signal(32)
self.sync.sys += sys_counter.eq(sys_counter + 1)
tx_counter = Signal(32)
self.sync.tx += tx_counter.eq(tx_counter + 1)
rx_counter = Signal(32)
self.sync.rx += rx_counter.eq(rx_counter + 1)
refclk_counter = Signal(32)
self.comb += [
platform.request("user_led", 0).eq(~sys_counter[26]),
platform.request("user_led", 1).eq(~serdes.tx_enable),
platform.request("user_led", 2).eq(~serdes.tx_ready),
platform.request("user_led", 3).eq(~serdes.rx_ready),
platform.request("user_led", 4).eq(~serdes.rx_data[0]),
platform.request("user_led", 5).eq(~serdes.rx_lol),
platform.request("user_led", 6).eq(~tx_counter[26]),
platform.request("user_led", 7).eq(~rx_counter[26]),
]
# UART bridge
uart_bridge = uart.UARTWishboneBridge(
pads=platform.request("serial"),
clk_freq=self.clk_freq,
baudrate=115200)
self.submodules += uart_bridge
self.add_wb_master(uart_bridge.wishbone)
analyzer_groups = {}
analyzer_groups[0] = [
serdes.analyzer_signals,
daq.analyzer_signals,
]
from litescope import LiteScopeAnalyzer
self.submodules.analyzer = LiteScopeAnalyzer(serdes.analyzer_signals+daq.analyzer_signals,
depth=256,
clock_domain="rx",
csr_csv="analyzer.csv")
self.add_csr("analyzer")
def __init__(
self,
platform,
clk_freq,
# CPU parameters
cpu_type="vexriscv",
cpu_reset_address=0x00000000,
cpu_variant=None,
# ROM parameters
integrated_rom_size=0,
integrated_rom_init=[],
# SRAM parameters
integrated_sram_size=0x1000,
integrated_sram_init=[],
# MAIN_RAM parameters
integrated_main_ram_size=0,
integrated_main_ram_init=[],
# CSR parameters
csr_data_width=8,
csr_alignment=32,
csr_address_width=14,
# Identifier parameters
ident="",
ident_version=False,
# UART parameters
with_uart=True,
uart_name="serial",
uart_baudrate=115200,
# Timer parameters
with_timer=True,
# Controller parameters
with_ctrl=True,
# Wishbone parameters
with_wishbone=True,
wishbone_timeout_cycles=1e6,
**kwargs):
self.platform = platform
self.clk_freq = clk_freq
# SoC's CSR/Mem/Interrupt mapping (default or user defined + dynamically allocateds)
self.soc_csr_map = {}
self.soc_interrupt_map = {}
self.soc_mem_map = self.mem_map
self.soc_io_regions = self.io_regions
# SoC's Config/Constants/Regions
self.config = {}
self.constants = {}
self.mem_regions = {}
self.csr_regions = {}
# Wishbone masters/slaves lists
self._wb_masters = []
self._wb_slaves = []
# CSR masters list
self._csr_masters = []
self.add_retro_compat(kwargs)
# Parameters managment ---------------------------------------------------------------------
if cpu_type == "None":
cpu_type = None
if not with_wishbone:
self.soc_mem_map["csr"] = 0x00000000
self.cpu_type = cpu_type
self.cpu_variant = cpu.check_format_cpu_variant(cpu_variant)
self.integrated_rom_size = integrated_rom_size
self.integrated_rom_initialized = integrated_rom_init != []
self.integrated_sram_size = integrated_sram_size
self.integrated_main_ram_size = integrated_main_ram_size
assert csr_data_width in [8, 16, 32]
self.csr_data_width = csr_data_width
self.csr_address_width = csr_address_width
assert csr_alignment in [32, 64]
self.with_ctrl = with_ctrl
self.with_uart = with_uart
self.uart_baudrate = uart_baudrate
self.with_wishbone = with_wishbone
self.wishbone_timeout_cycles = wishbone_timeout_cycles
# Modules instances ------------------------------------------------------------------------
# Add user's CSRs (needs to be done before the first dynamic allocation)
for _name, _id in self.csr_map.items():
self.add_csr(_name, _id)
# Add SoCController
if with_ctrl:
self.submodules.ctrl = SoCController()
self.add_csr("ctrl", allow_user_defined=True)
# Add CPU
self.config["CPU_TYPE"] = str(cpu_type).upper()
if cpu_type is not None:
if cpu_variant is not None:
self.config["CPU_VARIANT"] = str(
cpu_variant.split('+')[0]).upper()
# Check type
if cpu_type not in cpu.CPUS.keys():
raise ValueError(
"Unsupported CPU type: {} -- supported CPU types: {}".
format(cpu_type, ", ".join(cpu.CPUS.keys())))
# Declare the CPU
self.submodules.cpu = cpu.CPUS[cpu_type](platform,
self.cpu_variant)
if cpu_type == "microwatt":
self.add_constant("UART_POLLING", None)
# Update Memory Map (if defined by CPU)
self.soc_mem_map.update(self.cpu.mem_map)
# Update IO Regions (if defined by CPU)
self.soc_io_regions.update(self.cpu.io_regions)
# Set reset address
self.cpu.set_reset_address(
self.soc_mem_map["rom"]
if integrated_rom_size else cpu_reset_address)
self.config["CPU_RESET_ADDR"] = self.cpu.reset_address
# Add CPU buses as 32-bit Wishbone masters
for cpu_bus in self.cpu.buses:
assert cpu_bus.data_width in [32, 64, 128]
soc_bus = wishbone.Interface(data_width=32)
self.submodules += wishbone.Converter(cpu_bus, soc_bus)
self.add_wb_master(soc_bus)
# Add CPU CSR (dynamic)
self.add_csr("cpu", allow_user_defined=True)
# Add CPU interrupts
for _name, _id in self.cpu.interrupts.items():
self.add_interrupt(_name, _id)
# Allow SoCController to reset the CPU
if with_ctrl:
self.comb += self.cpu.reset.eq(self.ctrl.reset)
assert csr_alignment <= self.cpu.data_width
csr_alignment = self.cpu.data_width
else:
self.submodules.cpu = cpu.CPUNone()
self.soc_io_regions.update(self.cpu.io_regions)
# Add user's interrupts (needs to be done after CPU interrupts are allocated)
for _name, _id in self.interrupt_map.items():
self.add_interrupt(_name, _id)
# Add integrated ROM
if integrated_rom_size:
self.submodules.rom = wishbone.SRAM(integrated_rom_size,
read_only=True,
init=integrated_rom_init)
self.register_rom(self.rom.bus, integrated_rom_size)
# Add integrated SRAM
if integrated_sram_size:
self.submodules.sram = wishbone.SRAM(integrated_sram_size,
init=integrated_sram_init)
self.register_mem("sram", self.soc_mem_map["sram"], self.sram.bus,
integrated_sram_size)
# Add integrated MAIN_RAM (only useful when no external SRAM/SDRAM is available)
if integrated_main_ram_size:
self.submodules.main_ram = wishbone.SRAM(
integrated_main_ram_size, init=integrated_main_ram_init)
self.register_mem("main_ram", self.soc_mem_map["main_ram"],
self.main_ram.bus, integrated_main_ram_size)
# Add UART
if with_uart:
if uart_name in ["stub", "stream"]:
self.submodules.uart = uart.UART()
if uart_name == "stub":
self.comb += self.uart.sink.ready.eq(1)
elif uart_name == "bridge":
self.submodules.uart = uart.UARTWishboneBridge(
platform.request("serial"), clk_freq, uart_baudrate)
self.add_wb_master(self.uart.wishbone)
elif uart_name == "crossover":
self.submodules.uart = uart.UARTCrossover()
else:
if uart_name == "jtag_atlantic":
from litex.soc.cores.jtag import JTAGAtlantic
self.submodules.uart_phy = JTAGAtlantic()
elif uart_name == "jtag_uart":
from litex.soc.cores.jtag import JTAGPHY
self.submodules.uart_phy = JTAGPHY(device=platform.device)
else:
self.submodules.uart_phy = uart.UARTPHY(
platform.request(uart_name), clk_freq, uart_baudrate)
self.submodules.uart = ResetInserter()(uart.UART(
self.uart_phy))
self.add_csr("uart_phy", allow_user_defined=True)
self.add_csr("uart", allow_user_defined=True)
self.add_interrupt("uart", allow_user_defined=True)
# Add Identifier
if ident:
if ident_version:
ident = ident + " " + get_version()
self.submodules.identifier = identifier.Identifier(ident)
self.add_csr("identifier_mem", allow_user_defined=True)
self.config["CLOCK_FREQUENCY"] = int(clk_freq)
# Add Timer
if with_timer:
self.submodules.timer0 = timer.Timer()
self.add_csr("timer0", allow_user_defined=True)
self.add_interrupt("timer0", allow_user_defined=True)
# Add Wishbone to CSR bridge
self.config["CSR_DATA_WIDTH"] = csr_data_width
self.config["CSR_ALIGNMENT"] = csr_alignment
assert csr_data_width <= csr_alignment
self.csr_data_width = csr_data_width
self.csr_alignment = csr_alignment
if with_wishbone:
self.submodules.wishbone2csr = wishbone2csr.WB2CSR(
bus_csr=csr_bus.Interface(address_width=csr_address_width,
data_width=csr_data_width))
self.add_csr_master(self.wishbone2csr.csr)
self.register_mem("csr", self.soc_mem_map["csr"],
self.wishbone2csr.wishbone,
2**(csr_address_width + 2))
def __init__(self, platform, **kwargs):
dict_set_max(kwargs, 'integrated_rom_size', 0x8000)
dict_set_max(kwargs, 'integrated_sram_size', 0x8000)
#kwargs['uart_name']="stub" #stub
#kwargs['with_uart'] = False
sys_clk_freq = 50*1000000
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
self.submodules.uartbone = uart.UARTWishboneBridge(
pads = self.platform.request("serial"),
clk_freq = self.sys_clk_freq,
baudrate = 115200)
self.bus.add_master(name="uartbone", master=self.uartbone.wishbone)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq)
#self.submodules.uartbone = uart.UARTWishboneBridge(
# pads = self.platform.request("serial"),
# clk_freq = self.sys_clk_freq,
# baudrate = 115200)
#self.bus.add_master(name="uartbone", master=self.uartbone.wishbone)
# DDR2 SDRAM -------------------------------------------------------------------------------
#if True:
# sdram_module = MT46H64M16(50*1000000, "1:2") #P3R1GE4JGF MT46H64M16
# self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
# platform.request("ddram"),
# memtype = sdram_module.memtype,
# rd_bitslip = 0, #0 1
# wr_bitslip = 4, #4 3
# dqs_ddr_alignment="C0") #C0 C1
# self.add_csr("ddrphy")
# controller_settings = ControllerSettings(
# with_bandwidth=True)
# self.register_sdram(
# self.ddrphy,
# geom_settings = sdram_module.geom_settings,
# timing_settings = sdram_module.timing_settings,
# controller_settings=controller_settings)
# print(sdram_module.timing_settings.__dict__)
## print(sdram_module.geom_settings.__dict__)
# self.comb += [
# self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
# self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
# ]
# Basic peripherals ------------------------------------------------------------------------
# info module
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.add_csr("info")
# control and status module
#self.submodules.cas = cas.ControlAndStatus(platform, sys_clk_freq)
self.add_csr("cas")
# Add debug interface if the CPU has one ---------------------------------------------------
#if hasattr(self.cpu, "debug_bus"):
#self.register_mem(
# name="vexriscv_debug",
# address=0xf00f0000,
# interface=self.cpu.debug_bus, #debug_bus,
# size=0x100)
#analyzer_signals = [
# #self.ddrphy.sys_clk,
# #platform.lookup_request("ddram").a,
# platform.lookup_request("ddram").ba
# platform.lookup_request("ddram").ras_n,
# platform.lookup_request("ddram").cas_n,
# platform.lookup_request("ddram").we_n,
# platform.lookup_request("ddram").cs_n,
# platform.lookup_request("ddram").cke,
#self.cpu.ibus.stb,
# self.cpu.ibus.cyc
#]
#self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
# depth = 4096, # 512
# clock_domain = "sys",
# csr_csv = "analyzer.csv")
#self.add_csr("analyzer")
# Memory mapped SPI Flash ------------------------------------------------------------------
#self.submodules.spiflash = spi_flash.SpiFlash(
# platform.request("spiflash"),
# dummy=platform.spiflash_read_dummy_bits,
# div=platform.spiflash_clock_div,
# endianness=self.cpu.endianness)
#self.add_csr("spiflash")
#self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
#self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size)
#self.add_constant("SPIFLASH_TOTAL_SIZE", platform.spiflash_total_size)
#self.add_wb_slave(
# self.mem_map["spiflash"],
# self.spiflash.bus,
# platform.spiflash_total_size)
#self.add_memory_region(
# "spiflash",
# self.mem_map["spiflash"],
# platform.spiflash_total_size)
bios_size = 0x8000