def add_axi_gp_master(self, n=0, data_width=32):
assert n < 3 and self.axi_gp_masters[n] is None
assert data_width in [32, 64, 128]
axi_gpn = axi.AXIInterface(data_width=data_width,
address_width=32,
id_width=16)
self.config[f'PSU__USE__M_AXI_GP{n}'] = 1
self.config[f'PSU__MAXIGP{n}__DATA_WIDTH'] = data_width
self.axi_gp_masters.append(axi_gpn)
xpd = {0: "fpd", 1: "fpd", 2: "lpd"}[n]
self.cpu_params[f"i_maxihpm0_{xpd}_aclk"] = ClockSignal("ps")
layout = axi_gpn.layout_flat()
dir_map = {DIR_M_TO_S: 'o', DIR_S_TO_M: 'i'}
for group, signal, direction in layout:
sig_name = group + signal
if sig_name in [
'bfirst', 'blast', 'rfirst', 'arfirst', 'arlast',
'awfirst', 'awlast', 'wfirst', 'wid'
]:
continue
direction = dir_map[direction]
self.cpu_params[
f'{direction}_maxigp{n}_{group}{signal}'] = getattr(
getattr(axi_gpn, group), signal)
return axi_gpn
def add_hp0(self):
self.axi_hp0 = axi_hp0 = axi.AXIInterface(data_width=64, address_width=32, id_width=6)
self.axi_hp0_fifo_ctrl = axi_hp0_fifo_ctrl = Record(axi_fifo_ctrl_layout())
self.ps7_params.update(
# axi hp0 aw
i_S_AXI_HP0_AWVALID=axi_hp0.aw.valid,
o_S_AXI_HP0_AWREADY=axi_hp0.aw.ready,
i_S_AXI_HP0_AWADDR=axi_hp0.aw.addr,
i_S_AXI_HP0_AWBURST=axi_hp0.aw.burst,
i_S_AXI_HP0_AWLEN=axi_hp0.aw.len,
i_S_AXI_HP0_AWSIZE=axi_hp0.aw.size,
i_S_AXI_HP0_AWID=axi_hp0.aw.id,
i_S_AXI_HP0_AWLOCK=axi_hp0.aw.lock,
i_S_AXI_HP0_AWPROT=axi_hp0.aw.prot,
i_S_AXI_HP0_AWCACHE=axi_hp0.aw.cache,
i_S_AXI_HP0_AWQOS=axi_hp0.aw.qos,
# axi hp0 w
i_S_AXI_HP0_WVALID=axi_hp0.w.valid,
i_S_AXI_HP0_WLAST=axi_hp0.w.last,
o_S_AXI_HP0_WREADY=axi_hp0.w.ready,
i_S_AXI_HP0_WID=axi_hp0.w.id,
i_S_AXI_HP0_WDATA=axi_hp0.w.data,
i_S_AXI_HP0_WSTRB=axi_hp0.w.strb,
# axi hp0 b
o_S_AXI_HP0_BVALID=axi_hp0.b.valid,
i_S_AXI_HP0_BREADY=axi_hp0.b.ready,
o_S_AXI_HP0_BID=axi_hp0.b.id,
o_S_AXI_HP0_BRESP=axi_hp0.b.resp,
# axi hp0 ar
i_S_AXI_HP0_ARVALID=axi_hp0.ar.valid,
o_S_AXI_HP0_ARREADY=axi_hp0.ar.ready,
i_S_AXI_HP0_ARADDR=axi_hp0.ar.addr,
i_S_AXI_HP0_ARBURST=axi_hp0.ar.burst,
i_S_AXI_HP0_ARLEN=axi_hp0.ar.len,
i_S_AXI_HP0_ARID=axi_hp0.ar.id,
i_S_AXI_HP0_ARLOCK=axi_hp0.ar.lock,
i_S_AXI_HP0_ARSIZE=axi_hp0.ar.size,
i_S_AXI_HP0_ARPROT=axi_hp0.ar.prot,
i_S_AXI_HP0_ARCACHE=axi_hp0.ar.cache,
i_S_AXI_HP0_ARQOS=axi_hp0.ar.qos,
# axi hp0 r
o_S_AXI_HP0_RVALID=axi_hp0.r.valid,
i_S_AXI_HP0_RREADY=axi_hp0.r.ready,
o_S_AXI_HP0_RLAST=axi_hp0.r.last,
o_S_AXI_HP0_RID=axi_hp0.r.id,
o_S_AXI_HP0_RRESP=axi_hp0.r.resp,
o_S_AXI_HP0_RDATA=axi_hp0.r.data,
# axi hp0 fifo ctrl
o_S_AXI_HP0_RACOUNT=axi_hp0_fifo_ctrl.racount,
o_S_AXI_HP0_RCOUNT=axi_hp0_fifo_ctrl.rcount,
i_S_AXI_HP0_RDISSUECAP1_EN=axi_hp0_fifo_ctrl.rdissuecapen,
o_S_AXI_HP0_WACOUNT=axi_hp0_fifo_ctrl.wacount,
o_S_AXI_HP0_WCOUNT=axi_hp0_fifo_ctrl.wcount,
i_S_AXI_HP0_WRISSUECAP1_EN=axi_hp0_fifo_ctrl.wrissuecapen
)
def add_axi_gp_master(self):
assert len(self.axi_gp_masters) < 2
n = len(self.axi_gp_masters)
axi_gpn = axi.AXIInterface(data_width=32,
address_width=32,
id_width=12)
self.axi_gp_masters.append(axi_gpn)
self.cpu_params.update({
# AXI GP clk
f"i_M_AXI_GP{n}_ACLK": ClockSignal("ps7"),
# AXI GP aw
f"o_M_AXI_GP{n}_AWVALID": axi_gpn.aw.valid,
f"i_M_AXI_GP{n}_AWREADY": axi_gpn.aw.ready,
f"o_M_AXI_GP{n}_AWADDR": axi_gpn.aw.addr,
f"o_M_AXI_GP{n}_AWBURST": axi_gpn.aw.burst,
f"o_M_AXI_GP{n}_AWLEN": axi_gpn.aw.len,
f"o_M_AXI_GP{n}_AWSIZE": axi_gpn.aw.size,
f"o_M_AXI_GP{n}_AWID": axi_gpn.aw.id,
f"o_M_AXI_GP{n}_AWLOCK": axi_gpn.aw.lock,
f"o_M_AXI_GP{n}_AWPROT": axi_gpn.aw.prot,
f"o_M_AXI_GP{n}_AWCACHE": axi_gpn.aw.cache,
f"o_M_AXI_GP{n}_AWQOS": axi_gpn.aw.qos,
# AXI GP w
f"o_M_AXI_GP{n}_WVALID": axi_gpn.w.valid,
f"o_M_AXI_GP{n}_WLAST": axi_gpn.w.last,
f"i_M_AXI_GP{n}_WREADY": axi_gpn.w.ready,
f"o_M_AXI_GP{n}_WID": axi_gpn.w.id,
f"o_M_AXI_GP{n}_WDATA": axi_gpn.w.data,
f"o_M_AXI_GP{n}_WSTRB": axi_gpn.w.strb,
# AXI GP b
f"i_M_AXI_GP{n}_BVALID": axi_gpn.b.valid,
f"o_M_AXI_GP{n}_BREADY": axi_gpn.b.ready,
f"i_M_AXI_GP{n}_BID": axi_gpn.b.id,
f"i_M_AXI_GP{n}_BRESP": axi_gpn.b.resp,
# AXI GP ar
f"o_M_AXI_GP{n}_ARVALID": axi_gpn.ar.valid,
f"i_M_AXI_GP{n}_ARREADY": axi_gpn.ar.ready,
f"o_M_AXI_GP{n}_ARADDR": axi_gpn.ar.addr,
f"o_M_AXI_GP{n}_ARBURST": axi_gpn.ar.burst,
f"o_M_AXI_GP{n}_ARLEN": axi_gpn.ar.len,
f"o_M_AXI_GP{n}_ARID": axi_gpn.ar.id,
f"o_M_AXI_GP{n}_ARLOCK": axi_gpn.ar.lock,
f"o_M_AXI_GP{n}_ARSIZE": axi_gpn.ar.size,
f"o_M_AXI_GP{n}_ARPROT": axi_gpn.ar.prot,
f"o_M_AXI_GP{n}_ARCACHE": axi_gpn.ar.cache,
f"o_M_AXI_GP{n}_ARQOS": axi_gpn.ar.qos,
# AXI GP r
f"i_M_AXI_GP{n}_RVALID": axi_gpn.r.valid,
f"o_M_AXI_GP{n}_RREADY": axi_gpn.r.ready,
f"i_M_AXI_GP{n}_RLAST": axi_gpn.r.last,
f"i_M_AXI_GP{n}_RID": axi_gpn.r.id,
f"i_M_AXI_GP{n}_RRESP": axi_gpn.r.resp,
f"i_M_AXI_GP{n}_RDATA": axi_gpn.r.data,
})
return axi_gpn
def add_axi_hp_slave(self):
assert len(self.axi_hp_slaves) < 4
n = len(self.axi_hp_slaves)
axi_hpn = axi.AXIInterface(data_width=64, address_width=32, id_width=6)
self.axi_hp_slaves.append(axi_hpn)
self.cpu_params.update({
# AXI HP0 clk.
f"i_S_AXI_HP{n}_ACLK": ClockSignal("ps7"),
# AXI HP0 aw.
f"i_S_AXI_HP{n}_AWVALID": axi_hpn.aw.valid,
f"o_S_AXI_HP{n}_AWREADY": axi_hpn.aw.ready,
f"i_S_AXI_HP{n}_AWADDR": axi_hpn.aw.addr,
f"i_S_AXI_HP{n}_AWBURST": axi_hpn.aw.burst,
f"i_S_AXI_HP{n}_AWLEN": axi_hpn.aw.len,
f"i_S_AXI_HP{n}_AWSIZE": axi_hpn.aw.size,
f"i_S_AXI_HP{n}_AWID": axi_hpn.aw.id,
f"i_S_AXI_HP{n}_AWLOCK": axi_hpn.aw.lock,
f"i_S_AXI_HP{n}_AWPROT": axi_hpn.aw.prot,
f"i_S_AXI_HP{n}_AWCACHE": axi_hpn.aw.cache,
f"i_S_AXI_HP{n}_AWQOS": axi_hpn.aw.qos,
# AXI HP0 w.
f"i_S_AXI_HP{n}_WVALID": axi_hpn.w.valid,
f"i_S_AXI_HP{n}_WLAST": axi_hpn.w.last,
f"o_S_AXI_HP{n}_WREADY": axi_hpn.w.ready,
f"i_S_AXI_HP{n}_WID": axi_hpn.w.id,
f"i_S_AXI_HP{n}_WDATA": axi_hpn.w.data,
f"i_S_AXI_HP{n}_WSTRB": axi_hpn.w.strb,
# AXI HP0 b.
f"o_S_AXI_HP{n}_BVALID": axi_hpn.b.valid,
f"i_S_AXI_HP{n}_BREADY": axi_hpn.b.ready,
f"o_S_AXI_HP{n}_BID": axi_hpn.b.id,
f"o_S_AXI_HP{n}_BRESP": axi_hpn.b.resp,
# AXI HP0 ar.
f"i_S_AXI_HP{n}_ARVALID": axi_hpn.ar.valid,
f"o_S_AXI_HP{n}_ARREADY": axi_hpn.ar.ready,
f"i_S_AXI_HP{n}_ARADDR": axi_hpn.ar.addr,
f"i_S_AXI_HP{n}_ARBURST": axi_hpn.ar.burst,
f"i_S_AXI_HP{n}_ARLEN": axi_hpn.ar.len,
f"i_S_AXI_HP{n}_ARID": axi_hpn.ar.id,
f"i_S_AXI_HP{n}_ARLOCK": axi_hpn.ar.lock,
f"i_S_AXI_HP{n}_ARSIZE": axi_hpn.ar.size,
f"i_S_AXI_HP{n}_ARPROT": axi_hpn.ar.prot,
f"i_S_AXI_HP{n}_ARCACHE": axi_hpn.ar.cache,
f"i_S_AXI_HP{n}_ARQOS": axi_hpn.ar.qos,
# AXI HP0 r.
f"o_S_AXI_HP{n}_RVALID": axi_hpn.r.valid,
f"i_S_AXI_HP{n}_RREADY": axi_hpn.r.ready,
f"o_S_AXI_HP{n}_RLAST": axi_hpn.r.last,
f"o_S_AXI_HP{n}_RID": axi_hpn.r.id,
f"o_S_AXI_HP{n}_RRESP": axi_hpn.r.resp,
f"o_S_AXI_HP{n}_RDATA": axi_hpn.r.data,
})
return axi_hpn
def add_gp0(self):
self.axi_gp0 = axi_gp0 = axi.AXIInterface(data_width=32,
address_width=32,
id_width=12)
self.ps7_params.update(
# axi gp0 clk
i_M_AXI_GP0_ACLK=ClockSignal("sys"),
# axi gp0 aw
o_M_AXI_GP0_AWVALID=axi_gp0.aw.valid,
i_M_AXI_GP0_AWREADY=axi_gp0.aw.ready,
o_M_AXI_GP0_AWADDR=axi_gp0.aw.addr,
o_M_AXI_GP0_AWBURST=axi_gp0.aw.burst,
o_M_AXI_GP0_AWLEN=axi_gp0.aw.len,
o_M_AXI_GP0_AWSIZE=axi_gp0.aw.size,
o_M_AXI_GP0_AWID=axi_gp0.aw.id,
o_M_AXI_GP0_AWLOCK=axi_gp0.aw.lock,
o_M_AXI_GP0_AWPROT=axi_gp0.aw.prot,
o_M_AXI_GP0_AWCACHE=axi_gp0.aw.cache,
o_M_AXI_GP0_AWQOS=axi_gp0.aw.qos,
# axi gp0 w
o_M_AXI_GP0_WVALID=axi_gp0.w.valid,
o_M_AXI_GP0_WLAST=axi_gp0.w.last,
i_M_AXI_GP0_WREADY=axi_gp0.w.ready,
o_M_AXI_GP0_WID=axi_gp0.w.id,
o_M_AXI_GP0_WDATA=axi_gp0.w.data,
o_M_AXI_GP0_WSTRB=axi_gp0.w.strb,
# axi gp0 b
i_M_AXI_GP0_BVALID=axi_gp0.b.valid,
o_M_AXI_GP0_BREADY=axi_gp0.b.ready,
i_M_AXI_GP0_BID=axi_gp0.b.id,
i_M_AXI_GP0_BRESP=axi_gp0.b.resp,
# axi gp0 ar
o_M_AXI_GP0_ARVALID=axi_gp0.ar.valid,
i_M_AXI_GP0_ARREADY=axi_gp0.ar.ready,
o_M_AXI_GP0_ARADDR=axi_gp0.ar.addr,
o_M_AXI_GP0_ARBURST=axi_gp0.ar.burst,
o_M_AXI_GP0_ARLEN=axi_gp0.ar.len,
o_M_AXI_GP0_ARID=axi_gp0.ar.id,
o_M_AXI_GP0_ARLOCK=axi_gp0.ar.lock,
o_M_AXI_GP0_ARSIZE=axi_gp0.ar.size,
o_M_AXI_GP0_ARPROT=axi_gp0.ar.prot,
o_M_AXI_GP0_ARCACHE=axi_gp0.ar.cache,
o_M_AXI_GP0_ARQOS=axi_gp0.ar.qos,
# axi gp0 r
i_M_AXI_GP0_RVALID=axi_gp0.r.valid,
o_M_AXI_GP0_RREADY=axi_gp0.r.ready,
i_M_AXI_GP0_RLAST=axi_gp0.r.last,
i_M_AXI_GP0_RID=axi_gp0.r.id,
i_M_AXI_GP0_RRESP=axi_gp0.r.resp,
i_M_AXI_GP0_RDATA=axi_gp0.r.data,
)
def _add_axi(self, name, data_width=128, address_width=40, id_width=16):
assert data_width <= 128
assert address_width <= 40
assert id_width <= 16
ax = axi.AXIInterface(data_width=data_width,
address_width=address_width,
id_width=id_width)
self.params.update({
f'o_{name}ACLK': ClockSignal(),
# aw
f'o_{name}AWVALID': ax.aw.valid,
f'i_{name}AWREADY': ax.aw.ready,
f'o_{name}AWADDR': ax.aw.addr,
f'o_{name}AWBURST': ax.aw.burst,
f'o_{name}AWLEN': ax.aw.len,
f'o_{name}AWSIZE': ax.aw.size[:3], # need to match size exactly
f'o_{name}AWID': ax.aw.id,
f'o_{name}AWLOCK': ax.aw.lock[:1], # need to match size exactly
f'o_{name}AWPROT': ax.aw.prot,
f'o_{name}AWCACHE': ax.aw.cache,
f'o_{name}AWQOS': ax.aw.qos,
# w
f'o_{name}WVALID': ax.w.valid,
f'o_{name}WLAST': ax.w.last,
f'i_{name}WREADY': ax.w.ready,
# f'o_{name}WID': ax.w.id, # does not exist
f'o_{name}WDATA': ax.w.data,
f'o_{name}WSTRB': ax.w.strb,
# b
f'i_{name}BVALID': ax.b.valid,
f'o_{name}BREADY': ax.b.ready,
f'i_{name}BID': ax.b.id,
f'i_{name}BRESP': ax.b.resp,
# ar
f'o_{name}ARVALID': ax.ar.valid,
f'i_{name}ARREADY': ax.ar.ready,
f'o_{name}ARADDR': ax.ar.addr,
f'o_{name}ARBURST': ax.ar.burst,
f'o_{name}ARLEN': ax.ar.len,
f'o_{name}ARID': ax.ar.id,
f'o_{name}ARLOCK': ax.ar.lock[:1],
f'o_{name}ARSIZE': ax.ar.size[:3],
f'o_{name}ARPROT': ax.ar.prot,
f'o_{name}ARCACHE': ax.ar.cache,
f'o_{name}ARQOS': ax.ar.qos,
# r
f'i_{name}RVALID': ax.r.valid,
f'o_{name}RREADY': ax.r.ready,
f'i_{name}RLAST': ax.r.last,
f'i_{name}RID': ax.r.id,
f'i_{name}RRESP': ax.r.resp,
f'i_{name}RDATA': ax.r.data,
})
return ax
def __init__(self, platform, variant="standard"):
assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
self.platform = platform
self.variant = variant
self.reset = Signal()
self.interrupt = Signal(4)
mem_dw, mmio_dw = AXI_DATA_WIDTHS[self.variant]
self.mem_axi = mem_axi = axi.AXIInterface(data_width= mem_dw, address_width=32, id_width=4)
self.mmio_axi = mmio_axi = axi.AXIInterface(data_width=mmio_dw, address_width=32, id_width=4)
self.mmio_wb = mmio_wb = wishbone.Interface(data_width=mmio_dw, adr_width=32-log2_int(mmio_dw//8))
self.periph_buses = [mmio_wb]
self.memory_buses = [mem_axi]
# # #
self.cpu_params = dict(
# clock, reset
i_clock=ClockSignal(),
i_reset=ResetSignal() | self.reset,
# debug (ignored)
#o_debug_clockeddmi_dmi_req_ready = ,
i_debug_clockeddmi_dmi_req_valid = 0,
i_debug_clockeddmi_dmi_req_bits_addr = 0,
i_debug_clockeddmi_dmi_req_bits_data = 0,
i_debug_clockeddmi_dmi_req_bits_op = 0,
i_debug_clockeddmi_dmi_resp_ready = 0,
#o_debug_clockeddmi_dmi_resp_valid = ,
#o_debug_clockeddmi_dmi_resp_bits_data = ,
#o_debug_clockeddmi_dmi_resp_bits_resp = ,
i_debug_clockeddmi_dmiClock = 0,
i_debug_clockeddmi_dmiReset = 0,
#o_debug_ndreset = ,
#o_debug_dmactive = ,
# irq
i_interrupts=self.interrupt,
# axi memory (L1-cached)
i_mem_axi4_0_aw_ready = mem_axi.aw.ready,
o_mem_axi4_0_aw_valid = mem_axi.aw.valid,
o_mem_axi4_0_aw_bits_id = mem_axi.aw.id,
o_mem_axi4_0_aw_bits_addr = mem_axi.aw.addr,
o_mem_axi4_0_aw_bits_len = mem_axi.aw.len,
o_mem_axi4_0_aw_bits_size = mem_axi.aw.size,
o_mem_axi4_0_aw_bits_burst = mem_axi.aw.burst,
o_mem_axi4_0_aw_bits_lock = mem_axi.aw.lock,
o_mem_axi4_0_aw_bits_cache = mem_axi.aw.cache,
o_mem_axi4_0_aw_bits_prot = mem_axi.aw.prot,
o_mem_axi4_0_aw_bits_qos = mem_axi.aw.qos,
i_mem_axi4_0_w_ready = mem_axi.w.ready,
o_mem_axi4_0_w_valid = mem_axi.w.valid,
o_mem_axi4_0_w_bits_data = mem_axi.w.data,
o_mem_axi4_0_w_bits_strb = mem_axi.w.strb,
o_mem_axi4_0_w_bits_last = mem_axi.w.last,
o_mem_axi4_0_b_ready = mem_axi.b.ready,
i_mem_axi4_0_b_valid = mem_axi.b.valid,
i_mem_axi4_0_b_bits_id = mem_axi.b.id,
i_mem_axi4_0_b_bits_resp = mem_axi.b.resp,
i_mem_axi4_0_ar_ready = mem_axi.ar.ready,
o_mem_axi4_0_ar_valid = mem_axi.ar.valid,
o_mem_axi4_0_ar_bits_id = mem_axi.ar.id,
o_mem_axi4_0_ar_bits_addr = mem_axi.ar.addr,
o_mem_axi4_0_ar_bits_len = mem_axi.ar.len,
o_mem_axi4_0_ar_bits_size = mem_axi.ar.size,
o_mem_axi4_0_ar_bits_burst = mem_axi.ar.burst,
o_mem_axi4_0_ar_bits_lock = mem_axi.ar.lock,
o_mem_axi4_0_ar_bits_cache = mem_axi.ar.cache,
o_mem_axi4_0_ar_bits_prot = mem_axi.ar.prot,
o_mem_axi4_0_ar_bits_qos = mem_axi.ar.qos,
o_mem_axi4_0_r_ready = mem_axi.r.ready,
i_mem_axi4_0_r_valid = mem_axi.r.valid,
i_mem_axi4_0_r_bits_id = mem_axi.r.id,
i_mem_axi4_0_r_bits_data = mem_axi.r.data,
i_mem_axi4_0_r_bits_resp = mem_axi.r.resp,
i_mem_axi4_0_r_bits_last = mem_axi.r.last,
# axi mmio (not cached)
i_mmio_axi4_0_aw_ready = mmio_axi.aw.ready,
o_mmio_axi4_0_aw_valid = mmio_axi.aw.valid,
o_mmio_axi4_0_aw_bits_id = mmio_axi.aw.id,
o_mmio_axi4_0_aw_bits_addr = mmio_axi.aw.addr,
o_mmio_axi4_0_aw_bits_len = mmio_axi.aw.len,
o_mmio_axi4_0_aw_bits_size = mmio_axi.aw.size,
o_mmio_axi4_0_aw_bits_burst = mmio_axi.aw.burst,
o_mmio_axi4_0_aw_bits_lock = mmio_axi.aw.lock,
o_mmio_axi4_0_aw_bits_cache = mmio_axi.aw.cache,
o_mmio_axi4_0_aw_bits_prot = mmio_axi.aw.prot,
o_mmio_axi4_0_aw_bits_qos = mmio_axi.aw.qos,
i_mmio_axi4_0_w_ready = mmio_axi.w.ready,
o_mmio_axi4_0_w_valid = mmio_axi.w.valid,
o_mmio_axi4_0_w_bits_data = mmio_axi.w.data,
o_mmio_axi4_0_w_bits_strb = mmio_axi.w.strb,
o_mmio_axi4_0_w_bits_last = mmio_axi.w.last,
o_mmio_axi4_0_b_ready = mmio_axi.b.ready,
i_mmio_axi4_0_b_valid = mmio_axi.b.valid,
i_mmio_axi4_0_b_bits_id = mmio_axi.b.id,
i_mmio_axi4_0_b_bits_resp = mmio_axi.b.resp,
i_mmio_axi4_0_ar_ready = mmio_axi.ar.ready,
o_mmio_axi4_0_ar_valid = mmio_axi.ar.valid,
o_mmio_axi4_0_ar_bits_id = mmio_axi.ar.id,
o_mmio_axi4_0_ar_bits_addr = mmio_axi.ar.addr,
o_mmio_axi4_0_ar_bits_len = mmio_axi.ar.len,
o_mmio_axi4_0_ar_bits_size = mmio_axi.ar.size,
o_mmio_axi4_0_ar_bits_burst = mmio_axi.ar.burst,
o_mmio_axi4_0_ar_bits_lock = mmio_axi.ar.lock,
o_mmio_axi4_0_ar_bits_cache = mmio_axi.ar.cache,
o_mmio_axi4_0_ar_bits_prot = mmio_axi.ar.prot,
o_mmio_axi4_0_ar_bits_qos = mmio_axi.ar.qos,
o_mmio_axi4_0_r_ready = mmio_axi.r.ready,
i_mmio_axi4_0_r_valid = mmio_axi.r.valid,
i_mmio_axi4_0_r_bits_id = mmio_axi.r.id,
i_mmio_axi4_0_r_bits_data = mmio_axi.r.data,
i_mmio_axi4_0_r_bits_resp = mmio_axi.r.resp,
i_mmio_axi4_0_r_bits_last = mmio_axi.r.last,
)
# adapt axi interfaces to wishbone
# NOTE: AXI2Wishbone FSMs must be reset with the CPU!
mmio_a2w = ResetInserter()(axi.AXI2Wishbone(mmio_axi, mmio_wb,
base_address=0))
self.comb += mmio_a2w.reset.eq(ResetSignal() | self.reset)
self.submodules += mmio_a2w
# add verilog sources
self.add_sources(platform, variant)
def __init__(self, platform, variant="standard"):
self.platform = platform
self.variant = variant
self.reset = Signal()
self.interrupt = Signal(8)
mem_dw, mmio_dw, num_cores = CPU_SIZE_PARAMS[self.variant]
self.mem_axi = mem_axi = axi.AXIInterface(data_width=mem_dw,
address_width=32,
id_width=4)
self.mmio_axi = mmio_axi = axi.AXIInterface(data_width=mmio_dw,
address_width=32,
id_width=4)
self.l2fb_axi = l2fb_axi = axi.AXIInterface(data_width=mmio_dw,
address_width=32,
id_width=4)
self.mmio_wb = mmio_wb = wishbone.Interface(data_width=mmio_dw,
adr_width=32 -
log2_int(mmio_dw // 8))
self.l2fb_wb = l2fb_wb = wishbone.Interface(data_width=mmio_dw,
adr_width=32 -
log2_int(mmio_dw // 8))
self.memory_buses = [
mem_axi
] # Peripheral buses (Connected to main SoC's bus).
self.periph_buses = [
mmio_wb
] # Memory buses (Connected directly to LiteDRAM).
self.dma_bus = l2fb_wb # DMA bus (Arbitrated and connected to SoC's bus).
# # #
self.cpu_params = dict(
# Clk / Rst.
i_clock=ClockSignal("sys"),
i_reset=ResetSignal("sys") | self.reset,
# Debug (ignored).
i_debug_clock=0,
i_debug_reset=ResetSignal() | self.reset,
o_debug_clockeddmi_dmi_req_ready=Open(),
i_debug_clockeddmi_dmi_req_valid=0,
i_debug_clockeddmi_dmi_req_bits_addr=0,
i_debug_clockeddmi_dmi_req_bits_data=0,
i_debug_clockeddmi_dmi_req_bits_op=0,
i_debug_clockeddmi_dmi_resp_ready=0,
o_debug_clockeddmi_dmi_resp_valid=Open(),
o_debug_clockeddmi_dmi_resp_bits_data=Open(),
o_debug_clockeddmi_dmi_resp_bits_resp=Open(),
i_debug_clockeddmi_dmiClock=0,
i_debug_clockeddmi_dmiReset=ResetSignal() | self.reset,
o_debug_ndreset=Open(),
o_debug_dmactive=Open(),
i_debug_dmactiveAck=0,
# IRQ.
i_interrupts=self.interrupt,
# AXI Memory (L1-cached).
i_mem_axi4_0_aw_ready=mem_axi.aw.ready,
o_mem_axi4_0_aw_valid=mem_axi.aw.valid,
o_mem_axi4_0_aw_bits_id=mem_axi.aw.id,
o_mem_axi4_0_aw_bits_addr=mem_axi.aw.addr,
o_mem_axi4_0_aw_bits_len=mem_axi.aw.len,
o_mem_axi4_0_aw_bits_size=mem_axi.aw.size,
o_mem_axi4_0_aw_bits_burst=mem_axi.aw.burst,
o_mem_axi4_0_aw_bits_lock=mem_axi.aw.lock,
o_mem_axi4_0_aw_bits_cache=mem_axi.aw.cache,
o_mem_axi4_0_aw_bits_prot=mem_axi.aw.prot,
o_mem_axi4_0_aw_bits_qos=mem_axi.aw.qos,
i_mem_axi4_0_w_ready=mem_axi.w.ready,
o_mem_axi4_0_w_valid=mem_axi.w.valid,
o_mem_axi4_0_w_bits_data=mem_axi.w.data,
o_mem_axi4_0_w_bits_strb=mem_axi.w.strb,
o_mem_axi4_0_w_bits_last=mem_axi.w.last,
o_mem_axi4_0_b_ready=mem_axi.b.ready,
i_mem_axi4_0_b_valid=mem_axi.b.valid,
i_mem_axi4_0_b_bits_id=mem_axi.b.id,
i_mem_axi4_0_b_bits_resp=mem_axi.b.resp,
i_mem_axi4_0_ar_ready=mem_axi.ar.ready,
o_mem_axi4_0_ar_valid=mem_axi.ar.valid,
o_mem_axi4_0_ar_bits_id=mem_axi.ar.id,
o_mem_axi4_0_ar_bits_addr=mem_axi.ar.addr,
o_mem_axi4_0_ar_bits_len=mem_axi.ar.len,
o_mem_axi4_0_ar_bits_size=mem_axi.ar.size,
o_mem_axi4_0_ar_bits_burst=mem_axi.ar.burst,
o_mem_axi4_0_ar_bits_lock=mem_axi.ar.lock,
o_mem_axi4_0_ar_bits_cache=mem_axi.ar.cache,
o_mem_axi4_0_ar_bits_prot=mem_axi.ar.prot,
o_mem_axi4_0_ar_bits_qos=mem_axi.ar.qos,
o_mem_axi4_0_r_ready=mem_axi.r.ready,
i_mem_axi4_0_r_valid=mem_axi.r.valid,
i_mem_axi4_0_r_bits_id=mem_axi.r.id,
i_mem_axi4_0_r_bits_data=mem_axi.r.data,
i_mem_axi4_0_r_bits_resp=mem_axi.r.resp,
i_mem_axi4_0_r_bits_last=mem_axi.r.last,
# AXI MMIO (not cached).
i_mmio_axi4_0_aw_ready=mmio_axi.aw.ready,
o_mmio_axi4_0_aw_valid=mmio_axi.aw.valid,
o_mmio_axi4_0_aw_bits_id=mmio_axi.aw.id,
o_mmio_axi4_0_aw_bits_addr=mmio_axi.aw.addr,
o_mmio_axi4_0_aw_bits_len=mmio_axi.aw.len,
o_mmio_axi4_0_aw_bits_size=mmio_axi.aw.size,
o_mmio_axi4_0_aw_bits_burst=mmio_axi.aw.burst,
o_mmio_axi4_0_aw_bits_lock=mmio_axi.aw.lock,
o_mmio_axi4_0_aw_bits_cache=mmio_axi.aw.cache,
o_mmio_axi4_0_aw_bits_prot=mmio_axi.aw.prot,
o_mmio_axi4_0_aw_bits_qos=mmio_axi.aw.qos,
i_mmio_axi4_0_w_ready=mmio_axi.w.ready,
o_mmio_axi4_0_w_valid=mmio_axi.w.valid,
o_mmio_axi4_0_w_bits_data=mmio_axi.w.data,
o_mmio_axi4_0_w_bits_strb=mmio_axi.w.strb,
o_mmio_axi4_0_w_bits_last=mmio_axi.w.last,
o_mmio_axi4_0_b_ready=mmio_axi.b.ready,
i_mmio_axi4_0_b_valid=mmio_axi.b.valid,
i_mmio_axi4_0_b_bits_id=mmio_axi.b.id,
i_mmio_axi4_0_b_bits_resp=mmio_axi.b.resp,
i_mmio_axi4_0_ar_ready=mmio_axi.ar.ready,
o_mmio_axi4_0_ar_valid=mmio_axi.ar.valid,
o_mmio_axi4_0_ar_bits_id=mmio_axi.ar.id,
o_mmio_axi4_0_ar_bits_addr=mmio_axi.ar.addr,
o_mmio_axi4_0_ar_bits_len=mmio_axi.ar.len,
o_mmio_axi4_0_ar_bits_size=mmio_axi.ar.size,
o_mmio_axi4_0_ar_bits_burst=mmio_axi.ar.burst,
o_mmio_axi4_0_ar_bits_lock=mmio_axi.ar.lock,
o_mmio_axi4_0_ar_bits_cache=mmio_axi.ar.cache,
o_mmio_axi4_0_ar_bits_prot=mmio_axi.ar.prot,
o_mmio_axi4_0_ar_bits_qos=mmio_axi.ar.qos,
o_mmio_axi4_0_r_ready=mmio_axi.r.ready,
i_mmio_axi4_0_r_valid=mmio_axi.r.valid,
i_mmio_axi4_0_r_bits_id=mmio_axi.r.id,
i_mmio_axi4_0_r_bits_data=mmio_axi.r.data,
i_mmio_axi4_0_r_bits_resp=mmio_axi.r.resp,
i_mmio_axi4_0_r_bits_last=mmio_axi.r.last,
# AXI L2FB (Slave, for e.g., DMA).
o_l2_frontend_bus_axi4_0_aw_ready=l2fb_axi.aw.ready,
i_l2_frontend_bus_axi4_0_aw_valid=l2fb_axi.aw.valid,
i_l2_frontend_bus_axi4_0_aw_bits_id=l2fb_axi.aw.id,
i_l2_frontend_bus_axi4_0_aw_bits_addr=l2fb_axi.aw.addr,
i_l2_frontend_bus_axi4_0_aw_bits_len=l2fb_axi.aw.len,
i_l2_frontend_bus_axi4_0_aw_bits_size=l2fb_axi.aw.size,
i_l2_frontend_bus_axi4_0_aw_bits_burst=l2fb_axi.aw.burst,
i_l2_frontend_bus_axi4_0_aw_bits_lock=l2fb_axi.aw.lock,
i_l2_frontend_bus_axi4_0_aw_bits_cache=l2fb_axi.aw.cache,
i_l2_frontend_bus_axi4_0_aw_bits_prot=l2fb_axi.aw.prot,
i_l2_frontend_bus_axi4_0_aw_bits_qos=l2fb_axi.aw.qos,
o_l2_frontend_bus_axi4_0_w_ready=l2fb_axi.w.ready,
i_l2_frontend_bus_axi4_0_w_valid=l2fb_axi.w.valid,
i_l2_frontend_bus_axi4_0_w_bits_data=l2fb_axi.w.data,
i_l2_frontend_bus_axi4_0_w_bits_strb=l2fb_axi.w.strb,
i_l2_frontend_bus_axi4_0_w_bits_last=l2fb_axi.w.last,
i_l2_frontend_bus_axi4_0_b_ready=l2fb_axi.b.ready,
o_l2_frontend_bus_axi4_0_b_valid=l2fb_axi.b.valid,
o_l2_frontend_bus_axi4_0_b_bits_id=l2fb_axi.b.id,
o_l2_frontend_bus_axi4_0_b_bits_resp=l2fb_axi.b.resp,
o_l2_frontend_bus_axi4_0_ar_ready=l2fb_axi.ar.ready,
i_l2_frontend_bus_axi4_0_ar_valid=l2fb_axi.ar.valid,
i_l2_frontend_bus_axi4_0_ar_bits_id=l2fb_axi.ar.id,
i_l2_frontend_bus_axi4_0_ar_bits_addr=l2fb_axi.ar.addr,
i_l2_frontend_bus_axi4_0_ar_bits_len=l2fb_axi.ar.len,
i_l2_frontend_bus_axi4_0_ar_bits_size=l2fb_axi.ar.size,
i_l2_frontend_bus_axi4_0_ar_bits_burst=l2fb_axi.ar.burst,
i_l2_frontend_bus_axi4_0_ar_bits_lock=l2fb_axi.ar.lock,
i_l2_frontend_bus_axi4_0_ar_bits_cache=l2fb_axi.ar.cache,
i_l2_frontend_bus_axi4_0_ar_bits_prot=l2fb_axi.ar.prot,
i_l2_frontend_bus_axi4_0_ar_bits_qos=l2fb_axi.ar.qos,
i_l2_frontend_bus_axi4_0_r_ready=l2fb_axi.r.ready,
o_l2_frontend_bus_axi4_0_r_valid=l2fb_axi.r.valid,
o_l2_frontend_bus_axi4_0_r_bits_id=l2fb_axi.r.id,
o_l2_frontend_bus_axi4_0_r_bits_data=l2fb_axi.r.data,
o_l2_frontend_bus_axi4_0_r_bits_resp=l2fb_axi.r.resp,
o_l2_frontend_bus_axi4_0_r_bits_last=l2fb_axi.r.last,
)
# additional per-core debug signals:
self.cpu_params.update({
'i_resetctrl_hartIsInReset_%s' % i: Open()
for i in range(num_cores)
})
# Adapt AXI interfaces to Wishbone.
mmio_a2w = axi.AXI2Wishbone(mmio_axi, mmio_wb, base_address=0)
self.submodules += mmio_a2w
l2fb_a2w = axi.Wishbone2AXI(l2fb_wb, l2fb_axi, base_address=0)
self.submodules += l2fb_a2w
# Add Verilog sources.
self.add_sources(platform, variant)
def __init__(self, platform, variant="standard"):
self.platform = platform
self.reset = Signal()
self.interrupt = Signal(2)
ibus = axi.AXILiteInterface(data_width=32, address_width=32)
dbus = axi.AXILiteInterface(data_width=32, address_width=32)
self.periph_buses = [ibus, dbus]
self.memory_buses = []
# Peripheral Bus AXI <-> AXILite conversion.
ibus_axi = axi.AXIInterface(data_width=self.data_width,
address_width=32)
self.submodules += axi.AXI2AXILite(ibus_axi, ibus)
dbus_axi = axi.AXIInterface(data_width=self.data_width,
address_width=32)
self.submodules += axi.AXI2AXILite(dbus_axi, dbus)
# CPU Instance.
self.cpu_params = dict(
# Clk/Rst.
i_HCLK=ClockSignal("sys"),
i_SYSRESETn=~(ResetSignal() | self.reset),
# Control/Status.
p_MPU_PRESENT=0,
p_TRACE_LVL=0,
p_DEBUG_LVL=2,
# Interrupts.
p_NUM_IRQ=len(self.interrupt),
i_IRQ=self.interrupt,
# Embedded ROM/SRAM.
p_ITCM_SIZE=0, # Use LiteX's ROM.
p_DTCM_SIZE=0, # Use LiteX's RAM.
i_CFGITCMEN=0, # 1 = alias ITCM at 0x0
# Debug.
i_DBGRESETn=~(ResetSignal() | self.reset),
# Instruction Bus (AXI).
o_AWVALIDC=ibus_axi.aw.valid,
i_AWREADYC=ibus_axi.aw.ready,
o_AWADDRC=ibus_axi.aw.addr,
o_AWBURSTC=ibus_axi.aw.burst,
o_AWCACHEC=ibus_axi.aw.cache,
o_AWLENC=ibus_axi.aw.len,
o_AWLOCKC=ibus_axi.aw.lock,
o_AWPROTC=ibus_axi.aw.prot,
o_AWSIZEC=ibus_axi.aw.size,
o_WVALIDC=ibus_axi.w.valid,
i_WREADYC=ibus_axi.w.ready,
o_WLASTC=ibus_axi.w.last,
o_WSTRBC=ibus_axi.w.strb,
o_HWDATAC=ibus_axi.w.data,
i_BVALIDC=ibus_axi.b.valid,
o_BREADYC=ibus_axi.b.ready,
i_BRESPC=ibus_axi.b.resp,
o_ARVALIDC=ibus_axi.ar.valid,
i_ARREADYC=ibus_axi.ar.ready,
o_ARADDRC=ibus_axi.ar.addr,
o_ARBURSTC=ibus_axi.ar.burst,
o_ARCACHEC=ibus_axi.ar.cache,
o_ARLENC=ibus_axi.ar.len,
o_ARLOCKC=ibus_axi.ar.lock,
o_ARPROTC=ibus_axi.ar.prot,
o_ARSIZEC=ibus_axi.ar.size,
i_RVALIDC=ibus_axi.r.valid,
o_RREADYC=ibus_axi.r.ready,
i_RLASTC=ibus_axi.r.last,
i_RRESPC=ibus_axi.r.resp,
i_HRDATAC=ibus_axi.r.data,
# Data Bus (AXI).
o_AWVALIDS=dbus_axi.aw.valid,
i_AWREADYS=dbus_axi.aw.ready,
o_AWADDRS=dbus_axi.aw.addr,
o_AWBURSTS=dbus_axi.aw.burst,
o_AWCACHES=dbus_axi.aw.cache,
o_AWLENS=dbus_axi.aw.len,
o_AWLOCKS=dbus_axi.aw.lock,
o_AWPROTS=dbus_axi.aw.prot,
o_AWSIZES=dbus_axi.aw.size,
o_WVALIDS=dbus_axi.w.valid,
i_WREADYS=dbus_axi.w.ready,
o_WLASTS=dbus_axi.w.last,
o_WSTRBS=dbus_axi.w.strb,
o_HWDATAS=dbus_axi.w.data,
i_BVALIDS=dbus_axi.b.valid,
o_BREADYS=dbus_axi.b.ready,
i_BRESPS=dbus_axi.b.resp,
o_ARVALIDS=dbus_axi.ar.valid,
i_ARREADYS=dbus_axi.ar.ready,
o_ARADDRS=dbus_axi.ar.addr,
o_ARBURSTS=dbus_axi.ar.burst,
o_ARCACHES=dbus_axi.ar.cache,
o_ARLENS=dbus_axi.ar.len,
o_ARLOCKS=dbus_axi.ar.lock,
o_ARPROTS=dbus_axi.ar.prot,
o_ARSIZES=dbus_axi.ar.size,
i_RVALIDS=dbus_axi.r.valid,
o_RREADYS=dbus_axi.r.ready,
i_RLASTS=dbus_axi.r.last,
i_RRESPS=dbus_axi.r.resp,
i_HRDATAS=dbus_axi.r.data,
)
platform.add_source_dir(
"AT426-BU-98000-r0p1-00rel0/vivado/Arm_ipi_repository/CM3DbgAXI/rtl"
)
def __init__(self, endpoint, data_width=32, id_width=1):
self.axi = axi.AXIInterface(data_width=data_width, id_width=id_width)
# # #
aw_id = Signal(id_width)
ar_id = Signal(id_width)
r_len = Signal(8)
desc_rd = stream.Endpoint(descriptor_layout())
desc_wr = stream.Endpoint(descriptor_layout())
port_rd = endpoint.crossbar.get_master_port(read_only=True)
port_wr = endpoint.crossbar.get_master_port(write_only=True)
# AXI Write Path ---------------------------------------------------------------------------
# DMA / FIFO / Converter
self.submodules.dma_wr = dma_wr = LitePCIeDMAWriter(endpoint=endpoint,
port=port_wr,
with_table=False)
self.submodules.fifo_wr = fifo_wr = stream.SyncFIFO(
descriptor_layout(), 16)
self.submodules.conv_wr = conv_wr = stream.Converter(
nbits_from=data_width, nbits_to=endpoint.phy.data_width)
# Flow
self.comb += [
desc_wr.connect(fifo_wr.sink),
fifo_wr.source.connect(dma_wr.desc_sink),
conv_wr.source.connect(dma_wr.sink),
]
# FSM (Convert AXI Write Requests to LitePCIe's DMA Descriptors).
self.comb += desc_wr.address.eq(
self.axi.aw.addr) # Start address (byte addressed)
self.comb += desc_wr.length.eq(
(self.axi.aw.len + 1) *
(data_width // 8)) # Transfer length (in bytes)
self.submodules.fsm_wr = fsm_wr = FSM(reset_state="WRITE-IDLE")
fsm_wr.act(
"WRITE-IDLE",
self.axi.aw.ready.eq(desc_wr.ready),
desc_wr.valid.eq(self.axi.aw.valid),
If(
self.axi.aw.valid & self.axi.aw.ready,
NextValue(aw_id,
self.axi.aw.id), # Save id to use it on b channel.
NextState("WRITE-MONITOR"),
))
self.comb += [
conv_wr.sink.data.eq(self.axi.w.data),
conv_wr.sink.last.eq(self.axi.w.last),
]
fsm_wr.act(
"WRITE-MONITOR", conv_wr.sink.valid.eq(self.axi.w.valid),
self.axi.w.ready.eq(conv_wr.sink.ready),
If(
self.axi.w.valid & self.axi.w.ready & self.axi.w.last,
NextState("WRITE-RESP"),
))
self.comb += [
self.axi.b.id.eq(aw_id),
self.axi.b.resp.eq(0),
]
fsm_wr.act(
"WRITE-RESP",
self.axi.b.valid.eq(1),
If(
self.axi.b.ready,
NextState("WRITE-IDLE"), # Write done
))
# AXI Read Path ----------------------------------------------------------------------------
# DMA / FIFO / Converter
self.submodules.dma_rd = dma_rd = LitePCIeDMAReader(endpoint=endpoint,
port=port_rd,
with_table=False)
self.submodules.fifo_rd = fifo_rd = stream.SyncFIFO(
descriptor_layout(), 16)
self.submodules.conv_rd = conv_rd = stream.Converter(
nbits_from=endpoint.phy.data_width, nbits_to=data_width)
# Flow
self.comb += [
desc_rd.connect(fifo_rd.sink),
fifo_rd.source.connect(dma_rd.desc_sink),
dma_rd.source.connect(conv_rd.sink),
]
# FSM (Convert AXI Read Requests to LitePCIe's DMA Descriptors).
self.comb += desc_rd.address.eq(
self.axi.ar.addr) # Starting address (byte addressed)
self.comb += desc_rd.length.eq(
(self.axi.ar.len + 1) *
(data_width // 8)) # Transfer length (in bytes)
self.submodules.fsm_rd = fsm_rd = FSM(reset_state="READ-IDLE")
fsm_rd.act(
"READ-IDLE",
self.axi.ar.ready.eq(desc_rd.ready),
desc_rd.valid.eq(self.axi.ar.valid),
If(
self.axi.ar.valid & self.axi.ar.ready,
NextValue(ar_id,
self.axi.ar.id), # Save id to use it on r channel.
NextValue(r_len, self.axi.ar.len),
NextState("READ-MONITOR"),
))
self.comb += [
self.axi.r.data.eq(conv_rd.source.data),
self.axi.r.last.eq(r_len == 0),
# We need to provide the same id that was provided on aw channel for the duration of the transfer.
self.axi.r.id.eq(ar_id),
self.axi.r.resp.eq(0),
]
fsm_rd.act(
"READ-MONITOR",
self.axi.r.valid.eq(conv_rd.source.valid),
conv_rd.source.ready.eq(self.axi.r.ready),
If(
self.axi.r.ready & self.axi.r.valid,
NextValue(r_len, r_len - 1),
If(
self.axi.r.
last, # Check if we finished the whole AXI transaction.
NextState("READ-IDLE"),
)))
def __init__(self, platform, cpu_reset_addr, variant="standard"):
assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
assert cpu_reset_addr == 0x10000000, "cpu_reset_addr hardcoded in Chisel elaboration!"
self.platform = platform
self.variant = variant
self.reset = Signal()
self.interrupt = Signal(4)
self.mem_axi = mem_axi = axi.AXIInterface(
data_width=64, address_width=32, id_width=4)
self.mmio_axi = mmio_axi = axi.AXIInterface(
data_width=64, address_width=32, id_width=4)
self.mem_wb = mem_wb = wishbone.Interface(data_width=64, adr_width=29)
self.mmio_wb = mmio_wb = wishbone.Interface(data_width=64, adr_width=29)
self.ibus = ibus = wishbone.Interface()
self.dbus = dbus = wishbone.Interface()
# # #
self.specials += Instance("ExampleRocketSystem",
# clock, reset
i_clock=ClockSignal(),
i_reset=ResetSignal() | self.reset,
# debug (ignored)
#o_debug_clockeddmi_dmi_req_ready=,
i_debug_clockeddmi_dmi_req_valid=0,
i_debug_clockeddmi_dmi_req_bits_addr=0,
i_debug_clockeddmi_dmi_req_bits_data=0,
i_debug_clockeddmi_dmi_req_bits_op=0,
i_debug_clockeddmi_dmi_resp_ready=0,
#o_debug_clockeddmi_dmi_resp_valid=,
#o_debug_clockeddmi_dmi_resp_bits_data=,
#o_debug_clockeddmi_dmi_resp_bits_resp=,
i_debug_clockeddmi_dmiClock=0,
i_debug_clockeddmi_dmiReset=0,
#o_debug_ndreset=,
#o_debug_dmactive=,
# irq
i_interrupts=self.interrupt,
# axi memory (L1-cached)
i_mem_axi4_0_aw_ready=mem_axi.aw.ready,
o_mem_axi4_0_aw_valid=mem_axi.aw.valid,
o_mem_axi4_0_aw_bits_id=mem_axi.aw.id,
o_mem_axi4_0_aw_bits_addr=mem_axi.aw.addr,
o_mem_axi4_0_aw_bits_len=mem_axi.aw.len,
o_mem_axi4_0_aw_bits_size=mem_axi.aw.size,
o_mem_axi4_0_aw_bits_burst=mem_axi.aw.burst,
o_mem_axi4_0_aw_bits_lock=mem_axi.aw.lock,
o_mem_axi4_0_aw_bits_cache=mem_axi.aw.cache,
o_mem_axi4_0_aw_bits_prot=mem_axi.aw.prot,
o_mem_axi4_0_aw_bits_qos=mem_axi.aw.qos,
i_mem_axi4_0_w_ready=mem_axi.w.ready,
o_mem_axi4_0_w_valid=mem_axi.w.valid,
o_mem_axi4_0_w_bits_data=mem_axi.w.data,
o_mem_axi4_0_w_bits_strb=mem_axi.w.strb,
o_mem_axi4_0_w_bits_last=mem_axi.w.last,
o_mem_axi4_0_b_ready=mem_axi.b.ready,
i_mem_axi4_0_b_valid=mem_axi.b.valid,
i_mem_axi4_0_b_bits_id=mem_axi.b.id,
i_mem_axi4_0_b_bits_resp=mem_axi.b.resp,
i_mem_axi4_0_ar_ready=mem_axi.ar.ready,
o_mem_axi4_0_ar_valid=mem_axi.ar.valid,
o_mem_axi4_0_ar_bits_id=mem_axi.ar.id,
o_mem_axi4_0_ar_bits_addr=mem_axi.ar.addr,
o_mem_axi4_0_ar_bits_len=mem_axi.ar.len,
o_mem_axi4_0_ar_bits_size=mem_axi.ar.size,
o_mem_axi4_0_ar_bits_burst=mem_axi.ar.burst,
o_mem_axi4_0_ar_bits_lock=mem_axi.ar.lock,
o_mem_axi4_0_ar_bits_cache=mem_axi.ar.cache,
o_mem_axi4_0_ar_bits_prot=mem_axi.ar.prot,
o_mem_axi4_0_ar_bits_qos=mem_axi.ar.qos,
o_mem_axi4_0_r_ready=mem_axi.r.ready,
i_mem_axi4_0_r_valid=mem_axi.r.valid,
i_mem_axi4_0_r_bits_id=mem_axi.r.id,
i_mem_axi4_0_r_bits_data=mem_axi.r.data,
i_mem_axi4_0_r_bits_resp=mem_axi.r.resp,
i_mem_axi4_0_r_bits_last=mem_axi.r.last,
# axi mmio (not cached)
i_mmio_axi4_0_aw_ready=mmio_axi.aw.ready,
o_mmio_axi4_0_aw_valid=mmio_axi.aw.valid,
o_mmio_axi4_0_aw_bits_id=mmio_axi.aw.id,
o_mmio_axi4_0_aw_bits_addr=mmio_axi.aw.addr,
o_mmio_axi4_0_aw_bits_len=mmio_axi.aw.len,
o_mmio_axi4_0_aw_bits_size=mmio_axi.aw.size,
o_mmio_axi4_0_aw_bits_burst=mmio_axi.aw.burst,
o_mmio_axi4_0_aw_bits_lock=mmio_axi.aw.lock,
o_mmio_axi4_0_aw_bits_cache=mmio_axi.aw.cache,
o_mmio_axi4_0_aw_bits_prot=mmio_axi.aw.prot,
o_mmio_axi4_0_aw_bits_qos=mmio_axi.aw.qos,
i_mmio_axi4_0_w_ready=mmio_axi.w.ready,
o_mmio_axi4_0_w_valid=mmio_axi.w.valid,
o_mmio_axi4_0_w_bits_data=mmio_axi.w.data,
o_mmio_axi4_0_w_bits_strb=mmio_axi.w.strb,
o_mmio_axi4_0_w_bits_last=mmio_axi.w.last,
o_mmio_axi4_0_b_ready=mmio_axi.b.ready,
i_mmio_axi4_0_b_valid=mmio_axi.b.valid,
i_mmio_axi4_0_b_bits_id=mmio_axi.b.id,
i_mmio_axi4_0_b_bits_resp=mmio_axi.b.resp,
i_mmio_axi4_0_ar_ready=mmio_axi.ar.ready,
o_mmio_axi4_0_ar_valid=mmio_axi.ar.valid,
o_mmio_axi4_0_ar_bits_id=mmio_axi.ar.id,
o_mmio_axi4_0_ar_bits_addr=mmio_axi.ar.addr,
o_mmio_axi4_0_ar_bits_len=mmio_axi.ar.len,
o_mmio_axi4_0_ar_bits_size=mmio_axi.ar.size,
o_mmio_axi4_0_ar_bits_burst=mmio_axi.ar.burst,
o_mmio_axi4_0_ar_bits_lock=mmio_axi.ar.lock,
o_mmio_axi4_0_ar_bits_cache=mmio_axi.ar.cache,
o_mmio_axi4_0_ar_bits_prot=mmio_axi.ar.prot,
o_mmio_axi4_0_ar_bits_qos=mmio_axi.ar.qos,
o_mmio_axi4_0_r_ready=mmio_axi.r.ready,
i_mmio_axi4_0_r_valid=mmio_axi.r.valid,
i_mmio_axi4_0_r_bits_id=mmio_axi.r.id,
i_mmio_axi4_0_r_bits_data=mmio_axi.r.data,
i_mmio_axi4_0_r_bits_resp=mmio_axi.r.resp,
i_mmio_axi4_0_r_bits_last=mmio_axi.r.last,
)
# adapt axi interfaces to wishbone
mem_a2w = ResetInserter()(
axi.AXI2Wishbone(mem_axi, mem_wb, base_address=0))
mmio_a2w = ResetInserter()(
axi.AXI2Wishbone(mmio_axi, mmio_wb, base_address=0))
# NOTE: AXI2Wishbone FSMs must be reset with the CPU!
self.comb += [
mem_a2w.reset.eq(ResetSignal() | self.reset),
mmio_a2w.reset.eq(ResetSignal() | self.reset),
]
# down-convert wishbone from 64 to 32 bit data width
mem_dc = wishbone.Converter(mem_wb, ibus)
mmio_dc = wishbone.Converter(mmio_wb, dbus)
self.submodules += mem_a2w, mem_dc, mmio_a2w, mmio_dc
# add verilog sources
self.add_sources(platform)
def __init__(self, platform, variant="standard"):
self.platform = platform
self.variant = variant
self.reset = Signal()
self.interrupt = Signal(32)
self.axi_if = axi.AXIInterface(data_width=64,
address_width=32,
id_width=4)
self.periph_buses = [
self.axi_if
] # Peripheral buses (Connected to main SoC's bus).
self.memory_buses = [
] # Memory buses (Connected directly to LiteDRAM).
# # #
# CPU Instance.
self.cpu_params = dict(
# Clk / Rst.
i_clk_i=ClockSignal("sys"),
i_rst_n=~ResetSignal("sys") | self.reset,
# AXI interface.
o_AWVALID_o=self.axi_if.aw.valid,
i_AWREADY_i=self.axi_if.aw.ready,
o_AWID_o=self.axi_if.aw.id,
o_AWADDR_o=self.axi_if.aw.addr,
o_AWLEN_o=self.axi_if.aw.len,
o_AWSIZE_o=self.axi_if.aw.size,
o_AWBURST_o=self.axi_if.aw.burst,
o_AWLOCK_o=self.axi_if.aw.lock,
o_AWCACHE_o=self.axi_if.aw.cache,
o_AWPROT_o=self.axi_if.aw.prot,
o_AWQOS_o=self.axi_if.aw.qos,
o_AWREGION_o=Open(),
o_AWUSER_o=Open(),
o_WVALID_o=self.axi_if.w.valid,
i_WREADY_i=self.axi_if.w.ready,
o_WDATA_o=self.axi_if.w.data,
o_WSTRB_o=self.axi_if.w.strb,
o_WLAST_o=self.axi_if.w.last,
o_WUSER_o=Open(),
i_BVALID_i=self.axi_if.b.valid,
o_BREADY_o=self.axi_if.b.ready,
i_BID_i=self.axi_if.b.id,
i_BRESP_i=self.axi_if.b.resp,
i_BUSER_i=0,
o_ARVALID_o=self.axi_if.ar.valid,
i_ARREADY_i=self.axi_if.ar.ready,
o_ARID_o=self.axi_if.ar.id,
o_ARADDR_o=self.axi_if.ar.addr,
o_ARLEN_o=self.axi_if.ar.len,
o_ARSIZE_o=self.axi_if.ar.size,
o_ARBURST_o=self.axi_if.ar.burst,
o_ARLOCK_o=self.axi_if.ar.lock,
o_ARCACHE_o=self.axi_if.ar.cache,
o_ARPROT_o=self.axi_if.ar.prot,
o_ARQOS_o=self.axi_if.ar.qos,
o_ARUSER_o=Open(),
o_ARREGION_o=Open(),
i_RVALID_i=self.axi_if.r.valid,
o_RREADY_o=self.axi_if.r.ready,
i_RID_i=self.axi_if.r.id,
i_RDATA_i=self.axi_if.r.data,
i_RRESP_i=self.axi_if.r.resp,
i_RLAST_i=self.axi_if.r.last,
i_RUSER_i=0,
)
# Add Verilog sources.
# TODO: use Flist.cv64a6_imafdc_sv39 and Flist.cv32a6_imac_sv0 instead
add_manifest_sources(platform, "Flist.cv64a6_imafdc_sv39")
add_manifest_sources(platform, "Flist.cva6_wrapper")
def __init__(self, platform, variant="standard"):
self.platform = platform
self.variant = variant
self.reset = Signal()
self.interrupt = Signal(240)
self.axi_if = axi.AXIInterface(data_width=64, address_width=40)
self.periph_buses = [
self.axi_if
] # Peripheral buses (Connected to main SoC's bus).
self.memory_buses = [
] # Memory buses (Connected directly to LiteDRAM).
# # #
# Cycle count
cycle_count = Signal(64)
self.sync += cycle_count.eq(cycle_count + 1)
# CPU Instance.
self.cpu_params = dict(
# Clk / Rst.
i_pll_core_cpuclk=ClockSignal("sys"),
i_pad_cpu_rst_b=~ResetSignal("sys") | self.reset,
i_axim_clk_en=1,
# Debug (ignored).
i_sys_apb_clk=0,
i_sys_apb_rst_b=0,
# Interrupts.
i_pad_cpu_apb_base=Signal(40, reset=0x9000_0000),
i_pad_plic_int_cfg=0,
i_pad_plic_int_vld=self.interrupt,
# Integrated timer.
i_pad_cpu_sys_cnt=cycle_count,
# AXI.
o_biu_pad_awvalid=self.axi_if.aw.valid,
i_pad_biu_awready=self.axi_if.aw.ready,
o_biu_pad_awid=self.axi_if.aw.id,
o_biu_pad_awaddr=self.axi_if.aw.addr,
o_biu_pad_awlen=self.axi_if.aw.len,
o_biu_pad_awsize=self.axi_if.aw.size,
o_biu_pad_awburst=self.axi_if.aw.burst,
o_biu_pad_awlock=self.axi_if.aw.lock,
o_biu_pad_awcache=self.axi_if.aw.cache,
o_biu_pad_awprot=self.axi_if.aw.prot,
o_biu_pad_wvalid=self.axi_if.w.valid,
i_pad_biu_wready=self.axi_if.w.ready,
o_biu_pad_wdata=self.axi_if.w.data,
o_biu_pad_wstrb=self.axi_if.w.strb,
o_biu_pad_wlast=self.axi_if.w.last,
i_pad_biu_bvalid=self.axi_if.b.valid,
o_biu_pad_bready=self.axi_if.b.ready,
i_pad_biu_bid=self.axi_if.b.id,
i_pad_biu_bresp=self.axi_if.b.resp,
o_biu_pad_arvalid=self.axi_if.ar.valid,
i_pad_biu_arready=self.axi_if.ar.ready,
o_biu_pad_arid=self.axi_if.ar.id,
o_biu_pad_araddr=self.axi_if.ar.addr,
o_biu_pad_arlen=self.axi_if.ar.len,
o_biu_pad_arsize=self.axi_if.ar.size,
o_biu_pad_arburst=self.axi_if.ar.burst,
o_biu_pad_arlock=self.axi_if.ar.lock,
o_biu_pad_arcache=self.axi_if.ar.cache,
o_biu_pad_arprot=self.axi_if.ar.prot,
i_pad_biu_rvalid=self.axi_if.r.valid,
o_biu_pad_rready=self.axi_if.r.ready,
i_pad_biu_rid=self.axi_if.r.id,
i_pad_biu_rdata=self.axi_if.r.data,
i_pad_biu_rresp=self.axi_if.r.resp,
i_pad_biu_rlast=self.axi_if.r.last,
)
# Add Verilog sources.
add_manifest_sources(platform, "gen_rtl/filelists/C906_asic_rtl.fl")
from litex.build.xilinx import XilinxPlatform
if isinstance(platform, XilinxPlatform):
# Import a filelist for Xilinx FPGAs
add_manifest_sources(platform, "gen_rtl/filelists/xilinx_fpga.fl")
else:
# Import a filelist for generic platforms
add_manifest_sources(platform, "gen_rtl/filelists/generic_fpga.fl")
def __init__(self, platform, clk_freq, ps7_name, **kwargs):
SoCCore.__init__(self,
platform,
clk_freq,
cpu_type=None,
shadow_base=0x00000000,
**kwargs)
# PS7 --------------------------------------------------------------------------------------
self.axi_gp0 = axi_gp0 = axi.AXIInterface(data_width=32,
address_width=32,
id_width=12)
ps7_ddram_pads = platform.request("ps7_ddram")
self.specials += Instance(
ps7_name,
# clk/rst
io_PS_CLK=platform.request("ps7_clk"),
io_PS_PORB=platform.request("ps7_porb"),
io_PS_SRSTB=platform.request("ps7_srstb"),
# mio
io_MIO=platform.request("ps7_mio"),
# ddram
io_DDR_Addr=ps7_ddram_pads.addr,
io_DDR_BankAddr=ps7_ddram_pads.ba,
io_DDR_CAS_n=ps7_ddram_pads.cas_n,
io_DDR_Clk_n=ps7_ddram_pads.ck_n,
io_DDR_Clk=ps7_ddram_pads.ck_p,
io_DDR_CKE=ps7_ddram_pads.cke,
io_DDR_CS_n=ps7_ddram_pads.cs_n,
io_DDR_DM=ps7_ddram_pads.dm,
io_DDR_DQ=ps7_ddram_pads.dq,
io_DDR_DQS_n=ps7_ddram_pads.dqs_n,
io_DDR_DQS=ps7_ddram_pads.dqs_p,
io_DDR_ODT=ps7_ddram_pads.odt,
io_DDR_RAS_n=ps7_ddram_pads.ras_n,
io_DDR_DRSTB=ps7_ddram_pads.reset_n,
io_DDR_WEB=ps7_ddram_pads.we_n,
io_DDR_VRN=ps7_ddram_pads.vrn,
io_DDR_VRP=ps7_ddram_pads.vrp,
# ethernet
i_ENET0_MDIO_I=0,
# sdio0
i_SDIO0_WP=0,
# usb0
i_USB0_VBUS_PWRFAULT=0,
# fabric clk
o_FCLK_CLK0=ClockSignal("sys"),
# axi clk
i_M_AXI_GP0_ACLK=ClockSignal("sys"),
# axi aw
o_M_AXI_GP0_AWVALID=axi_gp0.aw.valid,
i_M_AXI_GP0_AWREADY=axi_gp0.aw.ready,
o_M_AXI_GP0_AWADDR=axi_gp0.aw.addr,
o_M_AXI_GP0_AWBURST=axi_gp0.aw.burst,
o_M_AXI_GP0_AWLEN=axi_gp0.aw.len,
o_M_AXI_GP0_AWSIZE=axi_gp0.aw.size,
o_M_AXI_GP0_AWID=axi_gp0.aw.id,
#o_M_AXI_GP0_AWLOCK =,
#o_M_AXI_GP0_AWPROT =,
#o_M_AXI_GP0_AWCACHE =,
#o_M_AXI_GP0_AWQOS =,
# axi w
o_M_AXI_GP0_WVALID=axi_gp0.w.valid,
o_M_AXI_GP0_WLAST=axi_gp0.w.last,
i_M_AXI_GP0_WREADY=axi_gp0.w.ready,
#o_M_AXI_GP0_WID=,
o_M_AXI_GP0_WDATA=axi_gp0.w.data,
o_M_AXI_GP0_WSTRB=axi_gp0.w.strb,
# axi b
i_M_AXI_GP0_BVALID=axi_gp0.b.valid,
o_M_AXI_GP0_BREADY=axi_gp0.b.ready,
i_M_AXI_GP0_BID=axi_gp0.b.id,
i_M_AXI_GP0_BRESP=axi_gp0.b.resp,
# axi ar
o_M_AXI_GP0_ARVALID=axi_gp0.ar.valid,
i_M_AXI_GP0_ARREADY=axi_gp0.ar.ready,
o_M_AXI_GP0_ARADDR=axi_gp0.ar.addr,
o_M_AXI_GP0_ARBURST=axi_gp0.ar.burst,
o_M_AXI_GP0_ARLEN=axi_gp0.ar.len,
o_M_AXI_GP0_ARID=axi_gp0.ar.id,
#o_M_AXI_GP0_ARLOCK=,
#o_M_AXI_GP0_ARSIZE=,
#o_M_AXI_GP0_ARPROT=,
#o_M_AXI_GP0_ARCACHE=,
#o_M_AXI_GP0_ARQOS=,
# axi r
i_M_AXI_GP0_RVALID=axi_gp0.r.valid,
o_M_AXI_GP0_RREADY=axi_gp0.r.ready,
i_M_AXI_GP0_RLAST=axi_gp0.r.last,
i_M_AXI_GP0_RID=axi_gp0.r.id,
i_M_AXI_GP0_RRESP=axi_gp0.r.resp,
i_M_AXI_GP0_RDATA=axi_gp0.r.data,
)
platform.add_ip(os.path.join("ip", ps7_name + ".xci"))
# AXI to Wishbone --------------------------------------------------------------------------
self.wb_gp0 = wb_gp0 = wishbone.Interface()
axi2wishbone = axi.AXI2Wishbone(axi_gp0,
wb_gp0,
base_address=0x43c00000)
self.submodules += axi2wishbone
self.add_wb_master(wb_gp0)
def __init__(self,
sys_clk_freq=int(75e6),
with_spi_flash=False,
with_ethernet=False,
with_etherbone=False,
eth_phy=0,
eth_ip="192.168.1.50",
with_led_chaser=True,
**kwargs):
platform = efinix_trion_t120_bga576_dev_kit.Platform()
# USBUART PMOD as Serial--------------------------------------------------------------------
platform.add_extension(
efinix_trion_t120_bga576_dev_kit.usb_pmod_io("pmod_e"))
kwargs["uart_name"] = "usb_uart"
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Efinix Trion T120 BGA576 Dev Kit",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import W25Q128JV
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="4x",
module=W25Q128JV(Codes.READ_1_1_4),
with_master=True)
platform.toolchain.excluded_ios.append(
platform.lookup_request("spiflash4x").dq)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
# Tristate Test ----------------------------------------------------------------------------
from litex.build.generic_platform import Subsignal, Pins, Misc, IOStandard
from litex.soc.cores.bitbang import I2CMaster
platform.add_extension([(
"i2c",
0,
Subsignal("sda", Pins("T12")),
Subsignal("scl", Pins("V11")),
IOStandard("3.3_V_LVTTL_/_LVCMOS"),
)])
self.submodules.i2c = I2CMaster(pads=platform.request("i2c"))
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
platform=platform,
clock_pads=platform.request("eth_clocks", eth_phy),
pads=platform.request("eth", eth_phy),
with_hw_init_reset=False)
if with_ethernet:
self.add_ethernet(phy=self.ethphy, software_debug=False)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# FIXME: Avoid this.
platform.toolchain.excluded_ios.append(
platform.lookup_request("eth_clocks").tx)
platform.toolchain.excluded_ios.append(
platform.lookup_request("eth_clocks").rx)
platform.toolchain.excluded_ios.append(
platform.lookup_request("eth").tx_data)
platform.toolchain.excluded_ios.append(
platform.lookup_request("eth").rx_data)
platform.toolchain.excluded_ios.append(
platform.lookup_request("eth").mdio)
# LPDDR3 SDRAM -----------------------------------------------------------------------------
if not self.integrated_main_ram_size:
# DRAM / PLL Blocks.
# ------------------
dram_pll_refclk = platform.request("dram_pll_refclk")
platform.toolchain.excluded_ios.append(dram_pll_refclk)
self.platform.toolchain.additional_sdc_commands.append(
f"create_clock -period {1e9/50e6} dram_pll_refclk")
from litex.build.efinix import InterfaceWriterBlock, InterfaceWriterXMLBlock
import xml.etree.ElementTree as et
class PLLDRAMBlock(InterfaceWriterBlock):
@staticmethod
def generate():
return """
design.create_block("dram_pll", block_type="PLL")
design.set_property("dram_pll", {"REFCLK_FREQ":"50.0"}, block_type="PLL")
design.gen_pll_ref_clock("dram_pll", pll_res="PLL_BR0", refclk_src="EXTERNAL", refclk_name="dram_pll_clkin", ext_refclk_no="0")
design.set_property("dram_pll","LOCKED_PIN","dram_pll_locked", block_type="PLL")
design.set_property("dram_pll","RSTN_PIN","dram_pll_rst_n", block_type="PLL")
design.set_property("dram_pll", {"CLKOUT0_PIN" : "dram_pll_CLKOUT0"}, block_type="PLL")
design.set_property("dram_pll","CLKOUT0_PHASE","0","PLL")
calc_result = design.auto_calc_pll_clock("dram_pll", {"CLKOUT0_FREQ": "400.0"})
"""
platform.toolchain.ifacewriter.blocks.append(PLLDRAMBlock())
class DRAMXMLBlock(InterfaceWriterXMLBlock):
@staticmethod
def generate(root, namespaces):
# CHECKME: Switch to DDRDesignService?
ddr_info = root.find("efxpt:ddr_info", namespaces)
ddr = et.SubElement(ddr_info,
"efxpt:ddr",
name="ddr_inst1",
ddr_def="DDR_0",
cs_preset_id="173",
cs_mem_type="LPDDR3",
cs_ctrl_width="x32",
cs_dram_width="x32",
cs_dram_density="8G",
cs_speedbin="800",
target0_enable="true",
target1_enable="true",
ctrl_type="none")
gen_pin_target0 = et.SubElement(ddr,
"efxpt:gen_pin_target0")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_wdata",
type_name=f"WDATA_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_wready",
type_name=f"WREADY_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_wid",
type_name=f"WID_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_bready",
type_name=f"BREADY_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_rdata",
type_name=f"RDATA_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_aid",
type_name=f"AID_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_bvalid",
type_name=f"BVALID_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_rlast",
type_name=f"RLAST_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_bid",
type_name=f"BID_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_asize",
type_name=f"ASIZE_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_atype",
type_name=f"ATYPE_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_aburst",
type_name=f"ABURST_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_wvalid",
type_name=f"WVALID_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_wlast",
type_name=f"WLAST_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_aaddr",
type_name=f"AADDR_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_rid",
type_name=f"RID_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_avalid",
type_name=f"AVALID_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_rvalid",
type_name=f"RVALID_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_alock",
type_name=f"ALOCK_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_rready",
type_name=f"RREADY_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_rresp",
type_name=f"RRESP_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_wstrb",
type_name=f"WSTRB_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_aready",
type_name=f"AREADY_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_alen",
type_name=f"ALEN_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi_clk",
type_name=f"ACLK_0",
is_bus="false",
is_clk="true",
is_clk_invert="false")
gen_pin_target1 = et.SubElement(ddr,
"efxpt:gen_pin_target1")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_wdata",
type_name=f"WDATA_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_wready",
type_name=f"WREADY_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_wid",
type_name=f"WID_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_bready",
type_name=f"BREADY_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_rdata",
type_name=f"RDATA_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_aid",
type_name=f"AID_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_bvalid",
type_name=f"BVALID_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_rlast",
type_name=f"RLAST_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_bid",
type_name=f"BID_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_asize",
type_name=f"ASIZE_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_atype",
type_name=f"ATYPE_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_aburst",
type_name=f"ABURST_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_wvalid",
type_name=f"WVALID_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_wlast",
type_name=f"WLAST_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_aaddr",
type_name=f"AADDR_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_rid",
type_name=f"RID_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_avalid",
type_name=f"AVALID_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_rvalid",
type_name=f"RVALID_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_alock",
type_name=f"ALOCK_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_rready",
type_name=f"RREADY_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_rresp",
type_name=f"RRESP_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_wstrb",
type_name=f"WSTRB_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_aready",
type_name=f"AREADY_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_alen",
type_name=f"ALEN_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi_clk",
type_name=f"ACLK_1",
is_bus="false",
is_clk="true",
is_clk_invert="false")
gen_pin_config = et.SubElement(ddr, "efxpt:gen_pin_config")
et.SubElement(gen_pin_config,
"efxpt:pin",
name="",
type_name="CFG_SEQ_RST",
is_bus="false")
et.SubElement(gen_pin_config,
"efxpt:pin",
name="",
type_name="CFG_SCL_IN",
is_bus="false")
et.SubElement(gen_pin_config,
"efxpt:pin",
name="",
type_name="CFG_SEQ_START",
is_bus="false")
et.SubElement(gen_pin_config,
"efxpt:pin",
name="",
type_name="RSTN",
is_bus="false")
et.SubElement(gen_pin_config,
"efxpt:pin",
name="",
type_name="CFG_SDA_IN",
is_bus="false")
et.SubElement(gen_pin_config,
"efxpt:pin",
name="",
type_name="CFG_SDA_OEN",
is_bus="false")
cs_fpga = et.SubElement(ddr, "efxpt:cs_fpga")
et.SubElement(cs_fpga,
"efxpt:param",
name="FPGA_ITERM",
value="120",
value_type="str")
et.SubElement(cs_fpga,
"efxpt:param",
name="FPGA_OTERM",
value="34",
value_type="str")
cs_memory = et.SubElement(ddr, "efxpt:cs_memory")
et.SubElement(cs_memory,
"efxpt:param",
name="RTT_NOM",
value="RZQ/2",
value_type="str")
et.SubElement(cs_memory,
"efxpt:param",
name="MEM_OTERM",
value="40",
value_type="str")
et.SubElement(cs_memory,
"efxpt:param",
name="CL",
value="RL=6/WL=3",
value_type="str")
timing = et.SubElement(ddr, "efxpt:cs_memory_timing")
et.SubElement(timing,
"efxpt:param",
name="tRAS",
value="42.000",
value_type="float")
et.SubElement(timing,
"efxpt:param",
name="tRC",
value="60.000",
value_type="float")
et.SubElement(timing,
"efxpt:param",
name="tRP",
value="18.000",
value_type="float")
et.SubElement(timing,
"efxpt:param",
name="tRCD",
value="18.000",
value_type="float")
et.SubElement(timing,
"efxpt:param",
name="tREFI",
value="3.900",
value_type="float")
et.SubElement(timing,
"efxpt:param",
name="tRFC",
value="210.000",
value_type="float")
et.SubElement(timing,
"efxpt:param",
name="tRTP",
value="10.000",
value_type="float")
et.SubElement(timing,
"efxpt:param",
name="tWTR",
value="10.000",
value_type="float")
et.SubElement(timing,
"efxpt:param",
name="tRRD",
value="10.000",
value_type="float")
et.SubElement(timing,
"efxpt:param",
name="tFAW",
value="50.000",
value_type="float")
cs_control = et.SubElement(ddr, "efxpt:cs_control")
et.SubElement(cs_control,
"efxpt:param",
name="AMAP",
value="ROW-COL_HIGH-BANK-COL_LOW",
value_type="str")
et.SubElement(cs_control,
"efxpt:param",
name="EN_AUTO_PWR_DN",
value="Off",
value_type="str")
et.SubElement(cs_control,
"efxpt:param",
name="EN_AUTO_SELF_REF",
value="No",
value_type="str")
cs_gate_delay = et.SubElement(ddr, "efxpt:cs_gate_delay")
et.SubElement(cs_gate_delay,
"efxpt:param",
name="EN_DLY_OVR",
value="No",
value_type="str")
et.SubElement(cs_gate_delay,
"efxpt:param",
name="GATE_C_DLY",
value="3",
value_type="int")
et.SubElement(cs_gate_delay,
"efxpt:param",
name="GATE_F_DLY",
value="0",
value_type="int")
platform.toolchain.ifacewriter.xml_blocks.append(DRAMXMLBlock())
# DRAM Rst.
# ---------
dram_pll_rst_n = platform.add_iface_io("dram_pll_rst_n")
self.comb += dram_pll_rst_n.eq(platform.request("user_btn", 1))
# DRAM AXI-Ports.
# --------------
for n, data_width in {
0: 256, # target0: 256-bit.
1: 128, # target1: 128-bit
}.items():
axi_port = axi.AXIInterface(data_width=data_width,
address_width=28,
id_width=8) # 256MB.
ios = [(
f"axi{n}",
0,
Subsignal("wdata", Pins(data_width)),
Subsignal("wready", Pins(1)),
Subsignal("wid", Pins(8)),
Subsignal("bready", Pins(1)),
Subsignal("rdata", Pins(data_width)),
Subsignal("aid", Pins(8)),
Subsignal("bvalid", Pins(1)),
Subsignal("rlast", Pins(1)),
Subsignal("bid", Pins(8)),
Subsignal("asize", Pins(3)),
Subsignal("atype", Pins(1)),
Subsignal("aburst", Pins(2)),
Subsignal("wvalid", Pins(1)),
Subsignal("aaddr", Pins(32)),
Subsignal("rid", Pins(8)),
Subsignal("avalid", Pins(1)),
Subsignal("rvalid", Pins(1)),
Subsignal("alock", Pins(2)),
Subsignal("rready", Pins(1)),
Subsignal("rresp", Pins(2)),
Subsignal("wstrb", Pins(data_width // 8)),
Subsignal("aready", Pins(1)),
Subsignal("alen", Pins(8)),
Subsignal("wlast", Pins(1)),
)]
io = platform.add_iface_ios(ios)
rw_n = axi_port.ar.valid
self.comb += [
# Pseudo AW/AR Channels.
io.atype.eq(~rw_n),
io.aaddr.eq(Mux(rw_n, axi_port.ar.addr, axi_port.aw.addr)),
io.aid.eq(Mux(rw_n, axi_port.ar.id, axi_port.aw.id)),
io.alen.eq(Mux(rw_n, axi_port.ar.len, axi_port.aw.len)),
io.asize.eq(Mux(rw_n, axi_port.ar.size, axi_port.aw.size)),
io.aburst.eq(
Mux(rw_n, axi_port.ar.burst, axi_port.aw.burst)),
io.alock.eq(Mux(rw_n, axi_port.ar.lock, axi_port.aw.lock)),
io.avalid.eq(
Mux(rw_n, axi_port.ar.valid, axi_port.aw.valid)),
axi_port.aw.ready.eq(~rw_n & io.aready),
axi_port.ar.ready.eq(rw_n & io.aready),
# R Channel.
axi_port.r.id.eq(io.rid),
axi_port.r.data.eq(io.rdata),
axi_port.r.last.eq(io.rlast),
axi_port.r.resp.eq(io.rresp),
axi_port.r.valid.eq(io.rvalid),
io.rready.eq(axi_port.r.ready),
# W Channel.
io.wid.eq(axi_port.w.id),
io.wstrb.eq(axi_port.w.strb),
io.wdata.eq(axi_port.w.data),
io.wlast.eq(axi_port.w.last),
io.wvalid.eq(axi_port.w.valid),
axi_port.w.ready.eq(io.wready),
# B Channel.
axi_port.b.id.eq(io.bid),
axi_port.b.valid.eq(io.bvalid),
io.bready.eq(axi_port.b.ready),
]
# Connect AXI interface to the main bus of the SoC.
axi_lite_port = axi.AXILiteInterface(data_width=data_width,
address_width=28)
self.submodules += axi.AXILite2AXI(axi_lite_port, axi_port)
self.bus.add_slave(f"target{n}", axi_lite_port,
SoCRegion(origin=0x4000_0000 +
0x1000_0000 * n,
size=0x1000_0000)) # 256MB.
# Use DRAM's target0 port as Main Ram -----------------------------------------------------
self.bus.add_region(
"main_ram",
SoCRegion(
origin=0x4000_0000,
size=0x1000_0000, # 256MB.
linker=True))
def add_memory_buses(self, address_width, data_width):
nax_data_width = 64
nax_burst_size = 64
assert data_width >= nax_data_width # FIXME: Only supporting up-conversion for now.
assert data_width <= nax_burst_size*8 # FIXME: AXIUpConverter doing assumptions on minimal burst_size.
ibus = axi.AXIInterface(
data_width = nax_data_width,
address_width = 32,
id_width = 1,
)
dbus = axi.AXIInterface(
data_width = nax_data_width,
address_width = 32,
id_width = 4,
)
self.memory_buses.append(ibus)
self.memory_buses.append(dbus)
self.cpu_params.update(
# Instruction Memory Bus (Master).
o_ram_ibus_arvalid = ibus.ar.valid,
i_ram_ibus_arready = ibus.ar.ready,
o_ram_ibus_araddr = ibus.ar.addr,
o_ram_ibus_arlen = ibus.ar.len,
o_ram_ibus_arsize = ibus.ar.size,
o_ram_ibus_arburst = ibus.ar.burst,
i_ram_ibus_rvalid = ibus.r.valid,
o_ram_ibus_rready = ibus.r.ready,
i_ram_ibus_rdata = ibus.r.data,
i_ram_ibus_rresp = ibus.r.resp,
i_ram_ibus_rlast = ibus.r.last,
# Data Memory Bus (Master).
o_ram_dbus_awvalid = dbus.aw.valid,
i_ram_dbus_awready = dbus.aw.ready,
o_ram_dbus_awaddr = dbus.aw.addr,
o_ram_dbus_awid = dbus.aw.id,
o_ram_dbus_awlen = dbus.aw.len,
o_ram_dbus_awsize = dbus.aw.size,
o_ram_dbus_awburst = dbus.aw.burst,
o_ram_dbus_wvalid = dbus.w.valid,
i_ram_dbus_wready = dbus.w.ready,
o_ram_dbus_wdata = dbus.w.data,
o_ram_dbus_wstrb = dbus.w.strb,
o_ram_dbus_wlast = dbus.w.last,
i_ram_dbus_bvalid = dbus.b.valid,
o_ram_dbus_bready = dbus.b.ready,
i_ram_dbus_bid = dbus.b.id,
i_ram_dbus_bresp = dbus.b.resp,
o_ram_dbus_arvalid = dbus.ar.valid,
i_ram_dbus_arready = dbus.ar.ready,
o_ram_dbus_araddr = dbus.ar.addr,
o_ram_dbus_arid = dbus.ar.id,
o_ram_dbus_arlen = dbus.ar.len,
o_ram_dbus_arsize = dbus.ar.size,
o_ram_dbus_arburst = dbus.ar.burst,
i_ram_dbus_rvalid = dbus.r.valid,
o_ram_dbus_rready = dbus.r.ready,
i_ram_dbus_rdata = dbus.r.data,
i_ram_dbus_rid = dbus.r.id,
i_ram_dbus_rresp = dbus.r.resp,
i_ram_dbus_rlast = dbus.r.last,
)
def __init__(self, platform, variant="standard"):
self.platform = platform
self.reset = Signal()
self.interrupt = Signal(2)
pbus = axi.AXILiteInterface(data_width=32, address_width=32)
self.periph_buses = [pbus]
self.memory_buses = []
# Peripheral Bus AXI <-> AXILite conversion.
pbus_axi = axi.AXIInterface(data_width=self.data_width, address_width=32)
self.submodules += axi.AXI2AXILite(pbus_axi, pbus)
# CPU Instance.
self.cpu_params = dict(
# Clk/Rst.
i_HCLK = ClockSignal("sys"),
i_SYSRESETn = ~(ResetSignal() | self.reset),
# Control/Status.
o_LOCKUP = Open(),
o_HALTED = Open(),
o_SYSRESETREQ = Open(),
i_NMI = 0,
i_EDBGRQ = 0,
# Embedded ROM/SRAM.
p_ITCM_SIZE = 0, # Use LiteX's ROM.
p_DTCM_SIZE = 0, # Use LiteX's SRAM.
i_CFGITCMEN = 0, # 1 = alias ITCM at 0x0
# Interrupts.
p_NUM_IRQ = len(self.interrupt),
i_IRQ = self.interrupt,
# Debug.
p_SMALL_DEBUG = True,
i_DBGRESTART = 0,
i_DBGRESETn = ~(ResetSignal() | self.reset),
p_DEBUG_SEL = 1, # JTAG
o_DBGRESTARTED = Open(),
# Peripheral Bus (AXI).
o_AWVALID = pbus_axi.aw.valid,
i_AWREADY = pbus_axi.aw.ready,
o_AWADDR = pbus_axi.aw.addr,
o_AWBURST = pbus_axi.aw.burst,
o_AWCACHE = pbus_axi.aw.cache,
o_AWLEN = pbus_axi.aw.len,
o_AWLOCK = pbus_axi.aw.lock,
o_AWPROT = pbus_axi.aw.prot,
o_AWSIZE = pbus_axi.aw.size,
o_WVALID = pbus_axi.w.valid,
i_WREADY = pbus_axi.w.ready,
o_WLAST = pbus_axi.w.last,
o_WSTRB = pbus_axi.w.strb,
o_HWDATA = pbus_axi.w.data,
i_BVALID = pbus_axi.b.valid,
o_BREADY = pbus_axi.b.ready,
i_BRESP = pbus_axi.b.resp,
o_ARVALID = pbus_axi.ar.valid,
i_ARREADY = pbus_axi.ar.ready,
o_ARADDR = pbus_axi.ar.addr,
o_ARBURST = pbus_axi.ar.burst,
o_ARCACHE = pbus_axi.ar.cache,
o_ARLEN = pbus_axi.ar.len,
o_ARLOCK = pbus_axi.ar.lock,
o_ARPROT = pbus_axi.ar.prot,
o_ARSIZE = pbus_axi.ar.size,
i_RVALID = pbus_axi.r.valid,
o_RREADY = pbus_axi.r.ready,
i_RLAST = pbus_axi.r.last,
i_RRESP = pbus_axi.r.resp,
i_HRDATA = pbus_axi.r.data,
)
platform.add_source_dir("AT472-BU-98000-r0p1-00rel0/vivado/Arm_ipi_repository/CM1DbgAXI/logical/rtl")
