def __init__(self, clock_domain="sys", phy_dw=16):
self.sink = stream.Endpoint([("data", phy_dw), ("ctrl", phy_dw//8)])
self.source = stream.Endpoint([("data", 32), ("ctrl", 4)])
# # #
converter = stream.StrideConverter(
[("data", phy_dw), ("ctrl", phy_dw//8)],
[("data", 32), ("ctrl", 4)],
reverse=False)
converter = stream.BufferizeEndpoints({"sink": stream.DIR_SINK})(converter)
converter = ClockDomainsRenamer(clock_domain)(converter)
self.submodules.converter = converter
cdc = stream.AsyncFIFO([("data", 32), ("ctrl", 4)], 8, buffered=True)
cdc = ClockDomainsRenamer({"write": clock_domain, "read": "sys"})(cdc)
self.submodules.cdc = cdc
skip_remover = RXSKPRemover()
self.submodules.skip_remover = skip_remover
word_aligner = RXWordAligner()
word_aligner = stream.BufferizeEndpoints({"source": stream.DIR_SOURCE})(word_aligner)
self.submodules.word_aligner = word_aligner
self.comb += [
self.sink.connect(converter.sink),
converter.source.connect(cdc.sink),
cdc.source.connect(skip_remover.sink),
skip_remover.source.connect(word_aligner.sink),
word_aligner.source.connect(self.source),
]
def __init__(self, clock_domain="sys", phy_dw=16):
self.sink = stream.Endpoint([("data", 32), ("ctrl", 4)])
self.source = stream.Endpoint([("data", phy_dw),
("ctrl", phy_dw // 8)])
# # #
# Clock compensation
skip_inserter = TXSKPInserter()
self.submodules += skip_inserter
# Clock domain crossing
cdc = stream.AsyncFIFO([("data", 32), ("ctrl", 4)], 8, buffered=True)
cdc = ClockDomainsRenamer({"write": "sys", "read": clock_domain})(cdc)
self.submodules.cdc = cdc
# Data-width adaptation
converter = stream.StrideConverter([("data", 32), ("ctrl", 4)],
[("data", phy_dw),
("ctrl", phy_dw // 8)],
reverse=False)
converter = stream.BufferizeEndpoints({"source":
stream.DIR_SOURCE})(converter)
converter = ClockDomainsRenamer(clock_domain)(converter)
self.submodules.converter = converter
# Flow
self.comb += [
self.sink.connect(skip_inserter.sink),
skip_inserter.source.connect(cdc.sink),
cdc.source.connect(converter.sink),
converter.source.connect(self.source)
]
def __init__(self, serdes, sys_clk_freq, with_scrambling=True, with_endianness_swap=True):
assert sys_clk_freq >= 125e6
self.ready = Signal() # o
self.sink = stream.Endpoint([("data", 32), ("ctrl", 4)])
self.source = stream.Endpoint([("data", 32), ("ctrl", 4)])
# # #
# Endianness Swap --------------------------------------------------------------------------
if with_endianness_swap:
sink = stream.Endpoint([("data", 32), ("ctrl", 4)])
source = stream.Endpoint([("data", 32), ("ctrl", 4)])
sink_swap = EndiannessSwap(self.sink, sink)
source_swap = EndiannessSwap(source, self.source)
self.submodules += sink_swap, source_swap
else:
sink = self.sink
source = self.source
# LFPS -------------------------------------------------------------------------------------
lfps = LFPSUnit(sys_clk_freq=sys_clk_freq, serdes=serdes)
self.submodules.lfps = lfps
# TS----------------------------------------------------------------------------------------
ts = TSUnit(serdes=serdes)
self.submodules.ts = ts
# LTSSM ------------------------------------------------------------------------------------
ltssm = LTSSM(serdes=serdes, lfps_unit=lfps, ts_unit=ts, sys_clk_freq=sys_clk_freq)
self.submodules.ltssm = ltssm
self.comb += self.ready.eq(ltssm.polling.idle)
# Scrambling -------------------------------------------------------------------------------
if with_scrambling:
scrambler = Scrambler()
scrambler = ResetInserter()(scrambler)
self.comb += scrambler.reset.eq(~ltssm.polling.tx_ready)
self.submodules.scrambler = scrambler
self.comb += [
sink.connect(scrambler.sink),
If(ltssm.polling.tx_ready, scrambler.source.connect(serdes.sink))
]
descrambler = Descrambler()
descrambler = ResetInserter()(descrambler)
descrambler = stream.BufferizeEndpoints({"source": stream.DIR_SOURCE})(descrambler)
self.comb += descrambler.reset.eq(~ltssm.polling.rx_ready)
self.submodules.descrambler = descrambler
self.comb += [
serdes.source.connect(descrambler.sink, keep={"data", "ctrl"}),
If(ltssm.polling.rx_ready, serdes.source.connect(descrambler.sink, omit={"data", "ctrl"})),
descrambler.source.connect(source),
]
else:
self.comb += If(ltssm.polling.tx_ready, sink.connect(serdes.sink))
self.comb += If(ltssm.polling.rx_ready, serdes.source.connect(source))