def wishbone_test(self, data_width, nwords=64):
wr_datas = [seed_to_data(i, True) for i in range(nwords)]
rd_datas = []
def main_generator(dut):
# Write ndatas to the Wishbone SRAM
for i in range(nwords):
yield from dut.host.chipset.wr32(i, [wr_datas[i]])
# Read ndatas from the Wishbone SRAM
for i in range(nwords):
yield from dut.host.chipset.rd32(i)
rd_datas.append(dut.host.chipset.rd32_data[0])
class DUT(Module):
def __init__(self, data_width):
self.submodules.host = Host(data_width, root_id, endpoint_id)
self.submodules.endpoint = LitePCIeEndpoint(self.host.phy)
self.submodules.wishbone_bridge = LitePCIeWishboneBridge(self.endpoint, lambda a: 1)
self.submodules.sram = wishbone.SRAM(nwords*4, bus=self.wishbone_bridge.wishbone)
dut = DUT(data_width)
generators = {
"sys" : [
main_generator(dut),
dut.host.chipset.phy.phy_sink.generator(),
dut.host.chipset.phy.phy_source.generator(),
]
}
clocks = {"sys": 10}
run_simulation(dut, generators, clocks)
# Verify Write/Read datas match
self.assertEqual(wr_datas, rd_datas)
def main_generator(dut):
wr_datas = [seed_to_data(i, True) for i in range(64)]
for i in range(64):
yield from dut.host.chipset.wr32(i, [wr_datas[i]])
rd_datas = []
for i in range(64):
yield from dut.host.chipset.rd32(i)
rd_datas.append(dut.host.chipset.rd32_data[0])
s, l, e = check(wr_datas, rd_datas)
print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
def main_generator(dut):
wr_datas = [seed_to_data(i, True) for i in range(64)]
for i in range(64):
yield from dut.host.chipset.wr32(i, [wr_datas[i]])
rd_datas = []
for i in range(64):
yield from dut.host.chipset.rd32(i)
rd_datas.append(dut.host.chipset.rd32_data[0])
s, l, e = check(wr_datas, rd_datas)
print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
def __init__(self):
self.submodules.host = Host(64,
root_id,
endpoint_id,
phy_debug=False,
chipset_debug=False,
host_debug=False)
self.submodules.endpoint = LitePCIeEndpoint(self.host.phy)
self.submodules.wishbone_bridge = LitePCIeWishboneBridge(
self.endpoint, lambda a: 1)
self.submodules.sram = wishbone.SRAM(1024,
bus=self.wishbone_bridge.wishbone)
wr_datas = [seed_to_data(i, True) for i in range(64)]
rd_datas = []
def main_generator(dut):
for i in range(64):
yield from dut.host.chipset.wr32(i, [wr_datas[i]])
for i in range(64):
yield from dut.host.chipset.rd32(i)
rd_datas.append(dut.host.chipset.rd32_data[0])
class TestBIST(unittest.TestCase):
def test(self):
dut = DUT()
def dma_test(self, data_width, test_size=1024):
host_data = [seed_to_data(i, True) for i in range(test_size//4)]
loopback_data = []
def main_generator(dut, nreads=8, nwrites=8):
# Allocate Host's memory
dut.host.malloc(0x00000000, test_size*2)
# Enable Chipset
dut.host.chipset.enable()
# Fill initial Host's memory
dut.host.write_mem(0x00000000, host_data)
# DMA Reader/Writer control models
dma_reader_driver = DMADriver("dma_reader", dut)
dma_writer_driver = DMADriver("dma_writer", dut)
# Program DMA Reader descriptors
yield from dma_reader_driver.set_prog_mode()
yield from dma_reader_driver.flush()
for i in range(nreads):
yield from dma_reader_driver.program_descriptor((test_size//8)*i, test_size//8)
# Program DMA Writer descriptors
yield from dma_writer_driver.set_prog_mode()
yield from dma_writer_driver.flush()
for i in range(nwrites):
yield from dma_writer_driver.program_descriptor(test_size + (test_size//8)*i, test_size//8)
# Enable MSI
yield dut.msi.enable.storage.eq(DMA_READER_IRQ | DMA_WRITER_IRQ)
# Enable DMA Reader & Writer
yield from dma_reader_driver.enable()
yield from dma_writer_driver.enable()
# Wait for all writes
while dut.msi_handler.dma_writer_irq_count != nwrites:
yield
# Delay to ensure all the data has been written
for i in range(1024):
yield
for data in dut.host.read_mem(test_size, test_size):
loopback_data.append(data)
class DUT(Module):
def __init__(self, data_width):
self.submodules.host = Host(data_width, root_id, endpoint_id,
phy_debug = False,
chipset_debug = False,
chipset_split = True,
chipset_reordering = True,
host_debug = True)
# Endpoint -------------------------------------------------------------------------
self.submodules.endpoint = LitePCIeEndpoint(self.host.phy, max_pending_requests=8)
# DMA Reader/Writer ----------------------------------------------------------------
dma_reader_port = self.endpoint.crossbar.get_master_port(read_only=True)
dma_writer_port = self.endpoint.crossbar.get_master_port(write_only=True)
self.submodules.dma_reader = LitePCIeDMAReader(self.endpoint, dma_reader_port)
self.submodules.dma_writer = LitePCIeDMAWriter(self.endpoint, dma_writer_port)
self.comb += self.dma_reader.source.connect(self.dma_writer.sink)
# MSI ------------------------------------------------------------------------------
self.submodules.msi = LitePCIeMSI(2)
self.comb += [
self.msi.irqs[log2_int(DMA_READER_IRQ)].eq(self.dma_reader.irq),
self.msi.irqs[log2_int(DMA_WRITER_IRQ)].eq(self.dma_writer.irq)
]
self.submodules.msi_handler = MSIHandler(debug=False)
self.comb += self.msi.source.connect(self.msi_handler.sink)
dut = DUT(data_width)
generators = {
"sys" : [
main_generator(dut),
dut.msi_handler.generator(dut),
dut.host.generator(),
dut.host.chipset.generator(),
dut.host.phy.phy_sink.generator(),
dut.host.phy.phy_source.generator()
]
}
clocks = {"sys": 10}
run_simulation(dut, generators, clocks, vcd_name="test_dma.vcd")
self.assertEqual(host_data, loopback_data)
self.down_converter,
self.up_converter,
self.dma_writer)
else:
self.comb += self.dma_reader.source.connect(self.dma_writer.sink)
self.submodules.msi = LitePCIeMSI(2)
self.comb += [
self.msi.irqs[log2_int(DMA_READER_IRQ)].eq(self.dma_reader.irq),
self.msi.irqs[log2_int(DMA_WRITER_IRQ)].eq(self.dma_writer.irq)
]
self.submodules.msi_handler = MSIHandler(debug=False)
self.comb += self.msi.source.connect(self.msi_handler.sink)
host_datas = [seed_to_data(i, True) for i in range(test_size // 4)]
loopback_datas = []
def main_generator(dut):
dut.host.malloc(0x00000000, test_size * 2)
dut.host.chipset.enable()
dut.host.write_mem(0x00000000, host_datas)
dma_reader_driver = DMADriver("dma_reader", dut)
dma_writer_driver = DMADriver("dma_writer", dut)
yield from dma_reader_driver.set_prog_mode()
yield from dma_reader_driver.flush()
for i in range(8):
