def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, **kwargs):
platform = arty.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Arty A7",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K128M16(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
def __init__(self, sys_clk_freq=int(100e6), **kwargs):
platform = arty.Platform()
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
# sdram
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = MT41K128M16(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self,
variant="a7-35",
toolchain="vivado",
sys_clk_freq=int(100e6),
no_pll=True,
**kwargs):
platform = arty.Platform(variant=variant, toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Arty A7 - S7PLL Power Tests",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, with_pll=not no_pll)
def __init__(self, sys_clk_freq=int(100e6), **kwargs):
platform = arty.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = MT41K128M16(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
def __init__(self):
platform = arty.Platform()
# BaseSoC ----------------------------------------------------------------------------------
BaseSoC.__init__(
self,
integrated_rom_size=0x8000,
with_etherbone=True,
)
# LiteScope Analyzer -----------------------------------------------------------------------
count = Signal(8)
self.sync += count.eq(count + 1)
analyzer_signals = [
self.cpu.ibus,
count,
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth=1024,
clock_domain="sys",
csr_csv="analyzer.csv")
self.add_csr("analyzer")
def __init__(self, **kwargs):
platform = arty.Platform()
# BenchPHY ---------------------------------------------------------------------------------
BaseSoC.__init__(self,
sys_clk_freq=int(100e6),
cpu_type=None,
integrated_main_ram_size=0x100)
# SDCard on PMODD with Digilent's Pmod MicroSD ---------------------------------------------
self.platform.add_extension(arty._sdcard_pmod_io)
from litesdcard.phy import SDPHY
self.submodules.sd_phy = SDPHY(self.platform.request("sdcard"),
platform.device, self.clk_freq)
self.add_csr("sd_phy")
# Send a command with button to verify timings ---------------------------------------------
self.comb += [
If(
self.platform.request("user_btn", 0),
self.sd_phy.cmdw.sink.valid.eq(1),
self.sd_phy.cmdw.sink.data.eq(0x5a),
)
]
def __init__(self,
variant="a7-35",
toolchain="vivado",
sys_clk_freq=int(100e6),
with_ethernet=False,
with_etherbone=False,
eth_ip="192.168.1.50",
eth_dynamic_ip=False,
ident_version=True,
with_jtagbone=True,
with_mapped_flash=False,
**kwargs):
platform = arty.Platform(variant=variant, toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Arty A7",
ident_version=ident_version,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, with_mapped_flash)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K128M16(sys_clk_freq, "1:4"),
l2_cache_size=kwargs.get("l2_size", 8192))
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# Jtagbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# Flash (through LiteSPI, experimental).
if with_mapped_flash:
self.submodules.spiflash_phy = LiteSPIPHY(
platform.request("spiflash4x"), S25FL128L(Codes.READ_1_1_4))
self.submodules.spiflash_mmap = LiteSPI(
self.spiflash_phy,
clk_freq=sys_clk_freq,
mmap_endianness=self.cpu.endianness)
spiflash_region = SoCRegion(origin=self.mem_map.get(
"spiflash", None),
size=S25FL128L.total_size,
cached=False)
self.bus.add_slave(name="spiflash",
slave=self.spiflash_mmap.bus,
region=spiflash_region)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self,
variant="a7-35",
toolchain="vivado",
sys_clk_freq=int(100e6),
with_ethernet=False,
with_etherbone=False,
eth_ip="192.168.1.50",
eth_dynamic_ip=False,
ident_version=True,
analyzer_csv="analyzer.csv",
**kwargs):
platform = arty.Platform(variant=variant, toolchain=toolchain)
kwargs["integrated_rom_size"] = 0x10000 if with_etherbone else 0x8000
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Arty A7",
ident_version = ident_version,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K128M16(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
_dws1000_ardu_io = [
("dw1000_spi", 0,
Subsignal("clk", Pins("ck_io:ck_io13")),
Subsignal("mosi", Pins("ck_io:ck_io11")),
Subsignal("cs_n", Pins("ck_io:ck_io10")),
Subsignal("miso", Pins("ck_io:ck_io12")),
Subsignal("pha", Pins("ck_io:ck_io0"), Misc("PULLDOWN True")),
Subsignal("pol", Pins("ck_io:ck_io1"), Misc("PULLDOWN True")),
Misc("SLEW=FAST"),
IOStandard("LVCMOS33"),
),
("dw1000_led", 0, Pins("ck_io:ck_io3"), IOStandard("LVCMOS33")), # TX LED on the DWS1000 module
("dw1000_led", 1, Pins("ck_io:ck_io4"), IOStandard("LVCMOS33")), # RX LED on the DWS1000 module
("dw1000_info", 0,
Subsignal("exton", Pins("ck_io:ck_a0")),
Subsignal("wakeup", Pins("ck_io:ck_io9")),
Subsignal("irq", Pins("ck_io:ck_io8")),
IOStandard("LVCMOS33"),
),
("dw1000_rstn", 0,
Pins("ck_io:ck_io7"),
IOStandard("LVCMOS33"),
),
]
platform.add_extension(_dws1000_ardu_io)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("dw1000_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
self.submodules.dw1000_rstn = GPIOTristate(platform.request("dw1000_rstn", 0))
self.add_csr("dw1000_rstn")
self.submodules.dw1000_info = GPIOIn(platform.request("dw1000_info"))
self.add_csr("dw1000_info")
# SPI with LiteScope
self.add_spi_master()
print(dir(self.cpu.ibus))
analyzer_signals = [
self.spi_master._control.storage,
self.spi_master._status.status,
self.spi_master._cs.storage,
self.spi_master.mosi,
self.spi_master.miso,
self.spi_master.pads.clk,
self.spi_master.pads.cs_n,
self.spi_master.pads.mosi,
self.spi_master.pads.miso,
self.dw1000_rstn._oe.storage,
self.dw1000_rstn._in.status,
self.dw1000_rstn._out.storage,
self.dw1000_info._in.status,
self.cpu.ibus.adr,
self.cpu.ibus.stb,
self.cpu.ibus.dat_w,
self.cpu.ibus.dat_r
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth=1024,
clock_domain="sys",
csr_csv=analyzer_csv
)
self.add_csr("analyzer")
def __init__(self,
sys_clk_freq=int(100e6),
with_ethernet=False,
cpu_variant="1c",
**kwargs):
platform = arty.Platform()
platform.add_extension(arty._sdcard_pmod_io) # MicroSD PMOD on JB.
# SoCCore ----------------------------------------------------------------------------------
kwargs["integrated_rom_size"] = 0x10000
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
cpu_cls=VexRiscvSMP,
cpu_variant=cpu_variant,
**kwargs)
# PLIC ------------------------------------------------------------------------------------
self.bus.add_slave("plic",
self.cpu.plicbus,
region=SoCRegion(origin=0xf0C00000,
size=0x400000,
cached=False))
# CLINT ------------------------------------------------------------------------------------
self.bus.add_slave("clint",
self.cpu.cbus,
region=SoCRegion(origin=0xf0010000,
size=0x10000,
cached=False))
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K128M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True,
controller_settings=ControllerSettings(
cmd_buffer_buffered=False,
with_auto_precharge=False))
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# JTAG ---------------------------------------------------------------------------------
self.submodules.jtag = S7JTAG()
self.comb += self.cpu.jtag_clk.eq(self.jtag.tck)
self.comb += self.cpu.jtag_enable.eq(1)
self.comb += self.cpu.jtag_capture.eq(self.jtag.capture)
self.comb += self.cpu.jtag_shift.eq(self.jtag.shift)
self.comb += self.cpu.jtag_update.eq(self.jtag.update)
self.comb += self.cpu.jtag_reset.eq(self.jtag.reset)
self.comb += self.cpu.jtag_tdi.eq(self.jtag.tdi)
self.comb += self.jtag.tdo.eq(self.cpu.jtag_tdo)
def __init__(self,
sys_clk_freq=int(100e6),
with_ethernet=False,
with_etherbone=False,
with_spiflash=False,
**kwargs):
platform = arty.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq,
interface_type="MEMORY")
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K128M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# SPIFlash ---------------------------------------------------------------------------------
if with_spiflash:
self.submodules.spiflash_phy = LiteSPIPHY(
platform.request("spiflash"), S25FL128S(Codes.READ_1_1_1))
self.submodules.spiflash_mmap = LiteSPI(
phy=self.spiflash_phy,
clk_freq=sys_clk_freq,
mmap_endianness=self.cpu.endianness)
self.add_csr("spiflash_mmap")
self.add_csr("spiflash_phy")
spiflash_size = 1024 * 1024 * 16
spiflash_region = SoCRegion(origin=self.mem_map.get(
"spiflash", None),
size=spiflash_size,
cached=False)
self.bus.add_slave(name="spiflash",
slave=self.spiflash_mmap.bus,
region=spiflash_region)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy)
def __init__(self,
variant="a7-35",
toolchain="vivado",
sys_clk_freq=int(100e6),
with_ethernet=False,
with_etherbone=False,
eth_ip="192.168.1.50",
eth_dynamic_ip=False,
with_led_chaser=True,
with_jtagbone=True,
with_spi_flash=False,
with_pmod_gpio=False,
**kwargs):
platform = arty.Platform(variant=variant, toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Arty A7",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform,
sys_clk_freq,
with_dram=not self.integrated_main_ram_size)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K128M16(sys_clk_freq, "1:4"),
l2_cache_size=kwargs.get("l2_size", 8192))
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# Jtagbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import S25FL128L
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="4x",
module=S25FL128L(Codes.READ_1_1_4),
rate="1:2",
with_master=True)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
# GPIOs ------------------------------------------------------------------------------------
if with_pmod_gpio:
platform.add_extension(arty.raw_pmod_io("pmoda"))
self.submodules.gpio = GPIOTristate(platform.request("pmoda"))
def __init__(self,
variant="minimal",
with_sampler=False,
with_analyzer=False,
host_ip="192.168.1.100",
host_udp_port=2000):
platform = arty.Platform()
# BenchSoC ---------------------------------------------------------------------------------
bench_kwargs = {
"minimal": dict(cpu_variant="minimal",
integrated_main_ram_size=0x1000),
"standard": dict(),
}[variant]
BaseSoC.__init__(self,
sys_clk_freq=int(100e6),
integrated_rom_size=0x10000,
integrated_rom_mode="rw",
**bench_kwargs)
# SDCard on PMODD with Digilent's Pmod MicroSD ---------------------------------------------
self.platform.add_extension(arty._sdcard_pmod_io)
self.add_sdcard("sdcard")
if with_sampler or with_analyzer:
# Etherbone ----------------------------------------------------------------------------
from liteeth.phy.mii import LiteEthPHYMII
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy)
if with_sampler:
# PMODB Sampler (connected to PmodTPH2 with Pmode Cable Kit) ---------------------------
_la_pmod_ios = [("la_pmod", 0,
Pins("pmoda:0 pmoda:1 pmoda:2 pmoda:3",
"pmoda:4 pmoda:5 pmoda:6 pmoda:7"),
IOStandard("LVCMOS33"))]
self.platform.add_extension(_la_pmod_ios)
self.submodules.sampler = Sampler(self.platform.request("la_pmod"))
self.add_csr("sampler")
# DRAMFIFO -----------------------------------------------------------------------------
from litedram.frontend.fifo import LiteDRAMFIFO
self.submodules.fifo = LiteDRAMFIFO(
data_width=8,
base=0x00000000,
depth=0x01000000, # 16MB
write_port=self.sdram.crossbar.get_port(mode="write",
data_width=8),
read_port=self.sdram.crossbar.get_port(mode="read",
data_width=8),
)
# UDPStreamer --------------------------------------------------------------------------
from liteeth.common import convert_ip
from liteeth.frontend.stream import LiteEthStream2UDPTX
udp_port = self.ethcore.udp.crossbar.get_port(host_udp_port, dw=8)
udp_streamer = LiteEthStream2UDPTX(ip_address=convert_ip(host_ip),
udp_port=host_udp_port,
fifo_depth=1024)
udp_streamer = ClockDomainsRenamer("eth_tx")(udp_streamer)
self.submodules += udp_streamer
udp_cdc = stream.ClockDomainCrossing([("data", 8)], "sys",
"eth_tx")
self.submodules += udp_cdc
# Sampler/FIFO/UDPStreamer flow -------------------------------------------------------------
self.comb += self.sampler.source.connect(self.fifo.sink)
self.comb += self.fifo.source.connect(udp_cdc.sink)
self.comb += udp_cdc.source.connect(udp_streamer.sink)
self.comb += udp_streamer.source.connect(udp_port.sink)
if with_analyzer:
from litescope import LiteScopeAnalyzer
analyzer_signals = [
self.sdphy.sdpads,
self.sdphy.cmdw.sink,
self.sdphy.cmdr.sink,
self.sdphy.cmdr.source,
self.sdphy.dataw.sink,
self.sdphy.dataw.stop,
self.sdphy.dataw.crc.source,
self.sdphy.dataw.status.status,
self.sdphy.datar.sink,
self.sdphy.datar.source,
self.sdphy.clocker.ce,
self.sdphy.clocker.stop,
]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals,
depth=2048,
clock_domain="sys",
csr_csv="analyzer.csv")
self.add_csr("analyzer")
def __init__(self,
uart="crossover",
sys_clk_freq=int(125e6),
with_bist=False,
with_analyzer=False):
platform = arty.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
ident="LiteDRAM bench on Arty",
ident_version=True,
integrated_rom_size=0x10000,
integrated_rom_mode="rw",
uart_name=uart)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.add_csr("crg")
# DDR3 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K128M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
with_bist=with_bist)
# UARTBone ---------------------------------------------------------------------------------
if uart != "serial":
self.add_uartbone(name="serial",
clk_freq=100e6,
baudrate=115200,
cd="uart")
# Etherbone --------------------------------------------------------------------------------
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
with_hw_init_reset=False)
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
from litescope import LiteScopeAnalyzer
analyzer_signals = [self.ddrphy.dfi]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals,
depth=256,
clock_domain="sys",
csr_csv="analyzer.csv")
self.add_csr("analyzer")
# Leds -------------------------------------------------------------------------------------
from litex.soc.cores.led import LedChaser
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def get_platform(self):
return arty.Platform(variant=self.variant, toolchain=self.toolchain)
def __init__(self,
variant="a7-35",
toolchain="vivado",
sys_clk_freq=int(100e6),
with_ethernet=False,
with_etherbone=False,
eth_ip="192.168.1.50",
eth_dynamic_ip=False,
ident_version=True,
with_jtagbone=True,
with_mapped_flash=False,
**kwargs):
platform = arty.Platform(variant=variant, toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
kwargs["cpu_type"] = "vexriscv_smp"
kwargs["cpu_variant"] = "linux"
kwargs["cpu_cls"] = VexRiscvSMP
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Arty A7",
ident_version=ident_version,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, with_mapped_flash)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K128M16(sys_clk_freq, "1:4"),
l2_cache_size=kwargs.get("l2_size", 8192))
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# Jtagbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# Flash (through LiteSPI, experimental).
if with_mapped_flash:
self.submodules.spiflash_phy = LiteSPIPHY(
platform.request("spiflash4x"), S25FL128L(Codes.READ_1_1_4))
self.submodules.spiflash_mmap = LiteSPI(
self.spiflash_phy,
clk_freq=sys_clk_freq,
mmap_endianness=self.cpu.endianness)
spiflash_region = SoCRegion(origin=self.mem_map.get(
"spiflash", None),
size=S25FL128L.total_size,
cached=False)
self.bus.add_slave(name="spiflash",
slave=self.spiflash_mmap.bus,
region=spiflash_region)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
# USB Host ---------------------------------------------------------------------------------
from litex.soc.cores.usb_ohci import USBOHCI
from litex.build.generic_platform import Subsignal, Pins, IOStandard
_usb_pmod_ios = [(
"usb_pmoda",
0,
Subsignal("dp", Pins("pmoda:0")),
Subsignal("dm", Pins("pmoda:4")),
IOStandard("LVCMOS33"),
)]
platform.add_extension(_usb_pmod_ios)
self.submodules.usb_ohci = USBOHCI(platform,
platform.request("usb_pmoda"),
usb_clk_freq=int(48e6))
self.bus.add_slave("usb_ohci_ctrl",
self.usb_ohci.wb_ctrl,
region=SoCRegion(origin=self.mem_map["usb_ohci"],
size=0x100000,
cached=False)) # FIXME: Mapping.
self.dma_bus.add_master("usb_ohci_dma", master=self.usb_ohci.wb_dma)
self.comb += self.cpu.interrupt[16].eq(self.usb_ohci.interrupt)
def __init__(self,
sys_clk_freq=int(100e6),
cpu_count=1,
with_ethernet=False,
with_analyzer=False,
**kwargs):
VexRiscvSMP.litedram_width = 128
VexRiscvSMP.ibus_width = 64
VexRiscvSMP.dbus_width = 64
VexRiscvSMP.coherent_dma = True
platform = arty.Platform()
platform.add_extension(arty._sdcard_pmod_io) # MicroSD PMOD on JD.
platform.add_extension(arty._usb_uart_pmod_io) # USB UART PMOD on JA.
# SoCCore ----------------------------------------------------------------------------------
kwargs["integrated_rom_size"] = 0x10000
kwargs["csr_data_width"] = 8
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
cpu_cls=VexRiscvSMP,
cpu_variant="default",
**kwargs)
self.add_constant("config_cpu_count", cpu_count) # for dts generation
# PLIC ------------------------------------------------------------------------------------
self.bus.add_slave("plic",
self.cpu.plicbus,
region=SoCRegion(origin=0xf0C00000,
size=0x400000,
cached=False))
# CLINT ------------------------------------------------------------------------------------
self.bus.add_slave("clint",
self.cpu.cbus,
region=SoCRegion(origin=0xf0010000,
size=0x10000,
cached=False))
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K128M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True,
controller_settings=ControllerSettings(
cmd_buffer_buffered=False,
with_auto_precharge=False))
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# JTAG ---------------------------------------------------------------------------------
self.submodules.jtag = S7JTAG()
self.comb += self.cpu.jtag_clk.eq(self.jtag.tck)
self.comb += self.cpu.jtag_enable.eq(1)
self.comb += self.cpu.jtag_capture.eq(self.jtag.capture)
self.comb += self.cpu.jtag_shift.eq(self.jtag.shift)
self.comb += self.cpu.jtag_update.eq(self.jtag.update)
self.comb += self.cpu.jtag_reset.eq(self.jtag.reset)
self.comb += self.cpu.jtag_tdi.eq(self.jtag.tdi)
self.comb += self.jtag.tdo.eq(self.cpu.jtag_tdo)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
from litescope import LiteScopeAnalyzer
self.add_uartbone("usb_uart")
analyzer_signals = [self.cpu.dma_buses[0]]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals,
depth=512,
clock_domain="sys",
csr_csv="analyzer.csv")
self.add_csr("analyzer")
def __init__(self, sys_clk_freq=int(50e6)):
platform = arty.Platform()
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self,
platform,
clk_freq=sys_clk_freq,
ident="LiteEth bench on Arty",
ident_version=True)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# Etherbone --------------------------------------------------------------------------------
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
with_hw_init_reset=False)
self.add_etherbone(phy=self.ethphy, buffer_depth=255)
# SRAM -------------------------------------------------------------------------------------
self.add_ram("sram", 0x20000000, 0x1000)
# UDP Streamer -----------------------------------------------------------------------------
from liteeth.frontend.stream import LiteEthUDPStreamer
self.submodules.udp_streamer = udp_streamer = LiteEthUDPStreamer(
udp=self.ethcore.udp,
ip_address="192.168.1.100",
udp_port=6000,
)
# Leds -------------------------------------------------------------------------------------
leds_pads = platform.request_all("user_led")
# Led Chaser (Default).
chaser_leds = Signal(len(leds_pads))
self.submodules.leds = LedChaser(pads=chaser_leds,
sys_clk_freq=sys_clk_freq)
# Led Control from UDP Streamer RX.
udp_leds = Signal(len(leds_pads))
self.comb += udp_streamer.source.ready.eq(1)
self.sync += If(udp_streamer.rx.source.valid,
udp_leds.eq(udp_streamer.source.data))
# Led Mux: Switch to received UDP value for 1s then switch back to Led Chaser.
self.submodules.leds_timer = leds_timer = WaitTimer(sys_clk_freq)
self.comb += [
leds_timer.wait.eq(~udp_streamer.rx.source.valid
), # Reload Timer on new UDP value.
If(leds_timer.done,
leds_pads.eq(chaser_leds)).Else(leds_pads.eq(udp_leds))
]
# Switches ---------------------------------------------------------------------------------
if False:
# Resynchronize Swiches inputs.
switches_pads = platform.request_all("user_sw")
switches = Signal(len(switches_pads))
self.specials += MultiReg(switches_pads, switches)
# Send Switches value on UDP Streamer TX every 500ms.
switches_timer = WaitTimer(int(500e-3 * sys_clk_freq))
switches_fsm = FSM(reset_state="IDLE")
self.submodules += switches_timer, switches_fsm
switches_fsm.act("IDLE", switches_timer.wait.eq(1),
If(switches_timer.done, NextState("SEND")))
switches_fsm.act("SEND", udp_streamer.sink.valid.eq(1),
udp_streamer.sink.data.eq(switches),
If(udp_streamer.sink.ready, NextState("IDLE")))
