def __init__(self, board, revision, sys_clk_freq=60e6, with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_phy=0, use_internal_osc=False, sdram_rate="1:1", **kwargs):
board = board.lower()
assert board in ["5a-75b", "5a-75e"]
if board == "5a-75b":
platform = colorlight_5a_75b.Platform(revision=revision)
elif board == "5a-75e":
platform = colorlight_5a_75e.Platform(revision=revision)
if board == "5a-75e" and revision == "6.0" and (with_etherbone or with_ethernet):
assert use_internal_osc, "You cannot use the 25MHz clock as system clock since it is provided by the Ethernet PHY and will stop during PHY reset."
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, int(sys_clk_freq),
ident = "LiteX SoC on Colorlight " + board.upper(),
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
with_rst = kwargs["uart_name"] not in ["serial", "bridge"] # serial_rx shared with user_btn_n.
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
self.submodules.crg = _CRG(platform, sys_clk_freq, use_internal_osc=use_internal_osc, with_usb_pll=with_usb_pll,with_rst=with_rst, sdram_rate=sdram_rate)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
if board == "5a-75e" and revision == "6.0":
sdram_cls = M12L64322A
sdram_size = 0x80000000
else:
sdram_cls = M12L16161A
sdram_size = 0x40000000
self.add_sdram("sdram",
phy = self.sdrphy,
module = sdram_cls(sys_clk_freq, sdram_rate),
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", sdram_size),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks", eth_phy),
pads = self.platform.request("eth", eth_phy),
tx_delay = 0e-9)
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# Leds -------------------------------------------------------------------------------------
if platform.lookup_request("serial", loose=True) is None: # Disable leds when serial is used.
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led_n"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
def __init__(self, sys_clk_freq=int(50e6)):
platform = colorlight_5a_75b.Platform()
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self,
platform,
clk_freq=sys_clk_freq,
ident="LiteEth bench on ColorLight 5A-75B",
ident_version=True)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# Etherbone --------------------------------------------------------------------------------
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
tx_delay=0e-9,
with_hw_init_reset=False)
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy, buffer_depth=255)
# SRAM -------------------------------------------------------------------------------------
self.add_ram("sram", 0x20000000, 0x1000)
# Leds -------------------------------------------------------------------------------------
from litex.soc.cores.led import LedChaser
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led_n"), sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self, revision):
platform = colorlight_5a_75b.Platform(revision)
sys_clk_freq = int(25e6)
# custom serial using j1 pins instead of led & button
platform.add_extension(_serialx)
# SoC with CPU
SoCCore.__init__(self,
platform,
cpu_type="vexriscv",
clk_freq=25e6,
ident="LiteX CPU Test SoC 5A-75B",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=0x4000,
uart_name="serialJx")
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk25"), 0)
# Led
user_leds = Cat(*[platform.request("user_led_n", i) for i in range(1)])
self.submodules.leds = Led(user_leds)
self.add_csr("leds")
def __init__(self, revision, cpu, freq, ip, mac, **kwargs):
platform = colorlight_5a_75b.Platform(revision)
sys_clk_freq = freq
# SoC with CPU
SoCCore.__init__(self,
platform,
cpu_type=cpu,
clk_freq=sys_clk_freq,
ident="LiteX SoC with Ethernet on Colorlight 5A-75B",
ident_version=True,
integrated_main_ram_size=0x4000,
**kwargs)
# Clock Reset Generation and PLL
self.submodules.crg = _CRG(platform, sys_clk_freq)
# Ethernet
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
tx_delay=0e-9)
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy,
ip_address=ip,
mac_address=int(mac, 0))
def __init__(self,
board,
revision,
with_ethernet=False,
with_etherbone=False,
sys_clk_freq=60e6,
sdram_rate="1:1",
**kwargs):
board = board.lower()
assert board in ["5a-75b", "5a-75e"]
if board == "5a-75b":
platform = colorlight_5a_75b.Platform(revision=revision)
elif board == "5a-75e":
platform = colorlight_5a_75e.Platform(revision=revision)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Colorlight " + board.upper(),
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
with_rst = kwargs["uart_name"] not in [
"serial", "bridge"
] # serial_rx shared with user_btn_n.
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
self.submodules.crg = _CRG(platform,
sys_clk_freq,
with_usb_pll=with_usb_pll,
with_rst=with_rst,
sdram_rate=sdram_rate)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
self.add_sdram("sdram",
phy=self.sdrphy,
module=M12L16161A(sys_clk_freq, sdram_rate),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
def __init__(self, with_etherbone=True, ip_address=None, mac_address=None):
platform = colorlight_5a_75b.Platform(revision="7.0")
sys_clk_freq = int(15e6)
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self, platform, clk_freq=sys_clk_freq)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_etherbone(
phy=self.ethphy,
ip_address=ip_address,
mac_address=mac_address,
)
# SPIFlash ---------------------------------------------------------------------------------
self.submodules.spiflash = ECP5SPIFlash(
pads=platform.request("spiflash"),
sys_clk_freq=sys_clk_freq,
spi_clk_freq=5e6,
)
self.add_csr("spiflash")
# GPIOs ------------------------------------------------------------------------------------
platform.add_extension(_gpios)
# Led --------------------------------------------------------------------------------------
#self.submodules.led = GPIOOut(platform.request("user_led_n"))
#self.add_csr("led")
# Pulsegen RAM -----------------------------------------------------------------------------
self.add_ram("pgen_ram", 0x10000000, contents=[-1, -2, -3], size=8)
port = self.pgen_ram.mem.get_port()
self.specials += port
# PULSEGEN ---------------------------------------------------------------------------------
self.submodules.pulsegen = pg = Pulsegen()
self.add_csr("pulsegen")
# DAC --------------------------------------------------------------------------------------
self.submodules.dac = dac = DAC()
outp = platform.request("gpio", 1)
led = platform.request("user_led_n")
self.comb += [
dac.inp.eq(pg.out0),
outp.eq(self.dac.out),
led.eq(pg.go.storage),
]
def __init__(self,
sys_clk_freq=int(50e6),
with_etherbone=True,
ip_address=None,
mac_address=None):
platform = colorlight_5a_75b.Platform(revision="7.0")
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self, platform, clk_freq=sys_clk_freq)
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
tx_delay=0e-9)
self.add_etherbone(
phy=self.ethphy,
ip_address=ip_address,
mac_address=mac_address,
data_width=32,
)
# SPIFlash ---------------------------------------------------------------------------------
self.submodules.spiflash = ECP5SPIFlash(
pads=platform.request("spiflash"),
sys_clk_freq=sys_clk_freq,
spi_clk_freq=5e6,
)
# Led --------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led_n"), sys_clk_freq=sys_clk_freq)
# GPIOs ------------------------------------------------------------------------------------
platform.add_extension(_gpios)
# Power switch
power_sw_pads = platform.request("gpio", 0)
power_sw_gpio = Signal()
power_sw_timer = WaitTimer(
2 * sys_clk_freq) # Set Power switch high after power up for 2s.
self.comb += power_sw_timer.wait.eq(1)
self.submodules += power_sw_timer
self.submodules.gpio0 = GPIOOut(power_sw_gpio)
self.comb += power_sw_pads.eq(power_sw_gpio | ~power_sw_timer.done)
# Reset Switch
reset_sw_pads = platform.request("gpio", 1)
self.submodules.gpio1 = GPIOOut(reset_sw_pads)
def __init__(self,
revision,
with_ethernet=False,
with_etherbone=False,
sys_clk_freq=60e6,
**kwargs):
platform = colorlight_5a_75b.Platform(revision=revision)
if (with_etherbone):
sys_clk_freq = int(125e6)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
with_rst = kwargs["uart_name"] not in [
"serial", "bridge"
] # serial_rx shared with user_btn_n.
with_usb_pll = kwargs.get("uart_name", None) == "usb_cdc"
self.submodules.crg = _CRG(platform,
sys_clk_freq,
with_usb_pll=with_usb_pll,
with_rst=with_rst)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
self.add_sdram("sdram",
phy=self.sdrphy,
module=M12L16161A(sys_clk_freq, "1:1"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy)
def __init__(self, revision, **kwargs):
platform = colorlight_5a_75b.Platform(revision=revision)
sys_clk_freq = int(125e6)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# Led --------------------------------------------------------------------------------------
led_counter = Signal(32)
self.sync += led_counter.eq(led_counter + 1)
self.comb += platform.request("user_led_n", 0).eq(led_counter[26])
def __init__(self, revision):
SoCCore.mem_map = {
"rom": 0x00000000,
"sram": 0x10000000,
"spiflash": 0x20000000,
"main_ram": 0x40000000,
"csr": 0x82000000,
}
platform = colorlight_5a_75b.Platform(revision)
sys_clk_freq = int(90e6)
# SoC with CPU
SoCCore.__init__(self, platform,
cpu_type = "vexriscv",
cpu_variant = "linux",
clk_freq = sys_clk_freq,
ident = "LiteX RISC-V SoC on 5A-75B",
ident_version = True,
max_sdram_size = 0x200000, # Limit mapped SDRAM to 2MB.
integrated_rom_size = 0x8000)
self.submodules.crg = _CRG(
platform = platform,
sys_clk_freq = sys_clk_freq,
use_internal_osc = False,
with_usb_pll = True,
with_rst = False,
sdram_rate = "1:2")
self.submodules.sdrphy = HalfRateGENSDRPHY(platform.request("sdram"))
self.add_sdram("sdram",
phy = self.sdrphy,
module = M12L16161A(sys_clk_freq, "1:2"),
origin = self.mem_map["main_ram"],
size = 2*mB,
l2_cache_size = 0x8000,
l2_cache_min_data_width = 128,
l2_cache_reverse = True
)
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks", 0),
pads = self.platform.request("eth", 0),
tx_delay = 0e-9)
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
self.add_spi_flash(mode="1x", dummy_cycles=8)
def __init__(self, revision, cpu, freq):
platform = colorlight_5a_75b.Platform(revision)
sys_clk_freq = freq
# SoC with CPU
SoCCore.__init__(self,
platform,
cpu_type=cpu,
clk_freq=sys_clk_freq,
ident="LiteX SoC with PLL on Colorlight 5A-75B",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=0x4000,
uart_name="serial")
# Clock Reset Generation and PLL
self.submodules.crg = _CRG(platform, sys_clk_freq)
def __init__(self, revision, with_ethernet=False, with_etherbone=False, **kwargs):
platform = colorlight_5a_75b.Platform(revision=revision)
sys_clk_freq = int(125e6)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=2)
self.add_sdram("sdram",
phy = self.sdrphy,
module = M12L16161A(sys_clk_freq, "1:1"),
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy)
# Led --------------------------------------------------------------------------------------
led_counter = Signal(32)
self.sync += led_counter.eq(led_counter + 1)
self.comb += platform.request("user_led_n", 0).eq(led_counter[26])
def __init__(self, with_etherbone=True, ip_address=None, mac_address=None):
platform = colorlight_5a_75b.Platform(revision="7.0")
sys_clk_freq = int(125e6)
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self, platform, clk_freq=sys_clk_freq)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_etherbone(
phy=self.ethphy,
ip_address=ip_address,
mac_address=mac_address,
)
# SPIFlash ---------------------------------------------------------------------------------
self.submodules.spiflash = ECP5SPIFlash(
pads=platform.request("spiflash"),
sys_clk_freq=sys_clk_freq,
spi_clk_freq=5e6,
)
self.add_csr("spiflash")
# Led --------------------------------------------------------------------------------------
self.submodules.led = GPIOOut(platform.request("user_led_n"))
self.add_csr("led")
# GPIOs ------------------------------------------------------------------------------------
platform.add_extension(_gpios)
self.submodules.gpio0 = GPIOOut(platform.request("gpio", 0))
self.submodules.gpio1 = GPIOOut(platform.request("gpio", 1))
self.add_csr("gpio0")
self.add_csr("gpio1")
def __init__(self,
debug,
flash_offset,
board,
revision,
with_ethernet=False,
with_etherbone=False,
eth_phy=0,
sys_clk_freq=60e6,
use_internal_osc=False,
sdram_rate="1:1",
**kwargs):
"""Create a basic SoC for Colorlight 5A-75X.
Returns:
Newly-constructed SoC
"""
board = board.lower()
assert board in ["5a-75b", "5a-75e"]
if board == "5a-75b":
platform = colorlight_5a_75b.Platform(revision=revision)
elif board == "5a-75e":
platform = colorlight_5a_75e.Platform(revision=revision)
if board == "5a-75e" and revision == "6.0" and (with_etherbone
or with_ethernet):
assert use_internal_osc, "You cannot use the 25MHz clock as system clock since it is provided by the Ethernet PHY and will stop during PHY reset."
# Set cpu name and variant defaults when none are provided
if "cpu_variant" not in kwargs:
if debug:
kwargs["cpu_variant"] = "imac+debug"
else:
kwargs["cpu_variant"] = "imac"
kwargs["integrated_main_ram_size"] = 0
kwargs["integrated_rom_size"] = 0
kwargs["csr_data_width"] = 32
# Set CPU reset address
kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + flash_offset
# Select "crossover" as soc uart instead of "serial"
# We have to make that selection before calling the parent initializer
if debug:
kwargs["uart_name"] = "crossover"
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
int(sys_clk_freq),
ident="LiteX SoC on Colorlight " + board.upper(),
ident_version=True,
**kwargs)
with_rst = kwargs["uart_name"] not in [
"serial", "bridge", "crossover"
] # serial_rx shared with user_btn_n.
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
self.submodules.crg = _CRG(platform,
sys_clk_freq,
use_internal_osc=use_internal_osc,
with_usb_pll=with_usb_pll,
with_rst=with_rst,
sdram_rate=sdram_rate)
# SDR SDRAM --------------------------------------------------------------------------------
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
if board == "5a-75e" and revision == "6.0":
sdram_cls = M12L64322A
sdram_size = 0x80000000
else:
sdram_cls = M12L16161A
sdram_size = 0x40000000
self.add_sdram("sdram",
phy=self.sdrphy,
module=sdram_cls(sys_clk_freq, sdram_rate),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", sdram_size),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# The litex SPI module supports memory-mapped reads, as well as a bit-banged mode
# for doing writes.
spiflash_size = 32 * 1024 * 1024
self.submodules.spiflash = spiflash = SpiFlash(
platform.request("spiflash"), dummy=8, endianness="little")
spiflash.add_clk_primitive(platform.device)
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=spiflash_size)
self.add_csr("spiflash")
# Add ROM linker region
self.add_memory_region("rom",
self.mem_map["spiflash"] + flash_offset,
spiflash_size - flash_offset,
type="cached+linker")
# In debug mode, add a UART bridge. This takes over from the normal UART bridge,
# however you can use the "crossover" UART to communicate with this over the bridge.
if debug:
self.submodules.uart_bridge = UARTWishboneBridge(
platform.request("serial"), sys_clk_freq, baudrate=115200)
self.add_wb_master(self.uart_bridge.wishbone)
if hasattr(self, "cpu") and self.cpu.name == "vexriscv":
self.register_mem("vexriscv_debug", 0xf00f0000,
self.cpu.debug_bus, 0x100)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks", eth_phy),
pads=self.platform.request("eth", eth_phy))
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
def main():
platform = colorlight_5a_75b.Platform(revision="7.0")
soc = RGMIITest(platform)
builder = Builder(soc, output_dir="build")
builder.build()
def __init__(self, with_etherbone=True, ip_address=None, mac_address=None):
platform = colorlight_5a_75b.Platform(revision="7.0")
sys_clk_freq = int(50e6)
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self, platform, clk_freq=sys_clk_freq)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_etherbone(
phy=self.ethphy,
ip_address=ip_address,
mac_address=mac_address,
)
# SPIFlash ---------------------------------------------------------------------------------
self.submodules.spiflash = ECP5SPIFlash(
pads=platform.request("spiflash"),
sys_clk_freq=sys_clk_freq,
spi_clk_freq=5e6,
)
self.add_csr("spiflash")
# GPIOs ------------------------------------------------------------------------------------
platform.add_extension(_gpios)
# Leds --------------------------------------------------------------------------------------
platform.add_extension(_leds)
led = platform.request("user_led_n")
r = platform.request("r")
y = platform.request("y")
g = platform.request("g")
t = Signal(32)
# PULSEGEN ---------------------------------------------------------------------------------
n = 128
wb = wishbone.Interface()
self.bus.add_slave(
"pulsegen", wb,
SoCRegion(origin=0x20000000, size=n, mode='rw', cached=False))
self.submodules.pulsegen = pg = Pulsegen(width_d=16,
size_fft=n,
r_max=4096)
self.add_csr("pulsegen")
self.comb += [
If((wb.adr[-4:] == 2),
pg.fft.x_in_we.eq(wb.we)), # if in general area in busspace
pg.fft.x_in.eq(wb.dat_w),
pg.fft.x_in_adr.eq(wb.adr),
#pg.fft.x_out_adr.eq(wb.adr),
wb.dat_r.eq(pg.fft.x_out),
]
self.sync += [
wb.ack.eq(wb.stb),
]
# DAC --------------------------------------------------------------------------------------
self.submodules.dac = dac = DAC()
outp = platform.request("gpio", 1)
self.comb += [
dac.inp.eq(pg.out0),
outp.eq(self.dac.out),
led.eq(~t[0]),
y.eq(t[1]),
r.eq(pg.fft.x_out[0]),
g.eq(pg.fft.done),
]
self.sync += If(wb.stb, t.eq(wb.adr))
