def main():
parser = argparse.ArgumentParser(
description="SDRAM Loopback SoC on Marble*")
builder_args(parser)
soc_core_args(parser)
parser.add_argument("--with-ethernet",
action="store_true",
help="enable Ethernet support")
parser.add_argument("--ethernet-phy",
default="rgmii",
help="select Ethernet PHY (rgmii or 1000basex)")
parser.add_argument("-p",
"--program-only",
action="store_true",
help="Don't build, just program the existing bitfile")
parser.add_argument("--build",
action="store_true",
help="Build FPGA bitstream")
parser.add_argument("--load", action="store_true", help="program FPGA")
args = parser.parse_args()
if args.build:
soc = SDRAMLoopbackSoC(with_ethernet=args.with_ethernet,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
# discard result, or save in vns?
builder.build(run=not args.program_only)
if args.load:
prog = kc705.Platform().create_programmer()
prog.load_bitstream(
os.path.join("build", "kc705", "gateware", "kc705.bit"))
def main():
parser = argparse.ArgumentParser(description="LitePCIe SoC on KC705")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--driver",
action="store_true",
help="Generate LitePCIe driver")
parser.add_argument("--load",
action="store_true",
help="Load bitstream (to SRAM)")
parser.add_argument("--nlanes",
default=4,
help="PCIe lanes: 1, 4 (default) or 8")
args = parser.parse_args()
platform = kc705.Platform()
soc = LitePCIeSoC(platform, nlanes=int(args.nlanes))
builder = Builder(soc, output_dir="build/kc705", csr_csv="csr.csv")
builder.build(build_name="kc705", run=args.build)
if args.driver:
generate_litepcie_software(soc,
os.path.join(builder.output_dir, "driver"))
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def __init__(self,
uart="crossover",
sys_clk_freq=int(125e6),
with_bist=False,
with_analyzer=False):
platform = kc705.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
ident="LiteDRAM bench on KC705",
ident_version=True,
integrated_rom_size=0x10000,
integrated_rom_mode="rw",
uart_name=uart)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(pads=PHYPadsReducer(
platform.request("ddram"), [0, 1, 2, 3, 4, 5, 6, 7]),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT8JTF12864(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
with_bist=with_bist)
# UARTBone ---------------------------------------------------------------------------------
if uart != "serial":
self.add_uartbone(name="serial",
clk_freq=100e6,
baudrate=115200,
cd="uart")
# Etherbone --------------------------------------------------------------------------------
self.submodules.ethphy = LiteEthPHY(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
clk_freq=self.clk_freq)
self.add_etherbone(phy=self.ethphy)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
from litescope import LiteScopeAnalyzer
analyzer_signals = [self.ddrphy.dfi]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals,
depth=256,
clock_domain="sys",
csr_csv="analyzer.csv")
# Leds -------------------------------------------------------------------------------------
from litex.soc.cores.led import LedChaser
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self,
sys_clk_freq=int(125e6),
integrated_rom_size=0x8000,
**kwargs):
platform = kc705.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=integrated_rom_size,
integrated_sram_size=0x8000,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = MT8JTF12864(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
def __init__(self, sys_clk_freq=int(125e6), **kwargs):
platform = kc705.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
# sdram
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = MT8JTF12864(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, **kwargs):
platform = kc705.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on KC705",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq,
cmd_latency=1)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT8JTF12864(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHY(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
clk_freq=self.clk_freq)
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def main():
parser = argparse.ArgumentParser(description="LiteSATA bench on KC705")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream (to SRAM)")
parser.add_argument("--gen", default="3", help="SATA Gen: 1, 2 or 3 (default)")
parser.add_argument("--connector", default="fmc", help="SATA Connector: fmc (default) , sfp or pcie")
parser.add_argument("--with-global-analyzer", action="store_true", help="Add Global LiteScope Analyzer")
parser.add_argument("--with-sector2mem-analyzer", action="store_true", help="Add Sector2Mem LiteScope Analyzer")
parser.add_argument("--with-mem2sector-analyzer", action="store_true", help="Add Mem2Sector LiteScope Analyzer")
args = parser.parse_args()
platform = kc705.Platform()
platform.add_extension(_sata_io)
soc = SATATestSoC(platform, args.connector, "gen" + args.gen,
with_global_analyzer = args.with_global_analyzer,
with_sector2mem_analyzer = args.with_sector2mem_analyzer,
with_mem2sector_analyzer = args.with_mem2sector_analyzer,
)
builder = Builder(soc, csr_csv="csr.csv")
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def __init__(self,
sys_clk_freq=int(125e6),
with_ethernet=False,
with_pcie=False,
with_sata=False,
**kwargs):
platform = kc705.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on KC705",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT8JTF12864(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHY(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
clk_freq=self.clk_freq)
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
self.submodules.pcie_phy = S7PCIEPHY(platform,
platform.request("pcie_x4"),
data_width=128,
bar0_size=0x20000)
self.add_csr("pcie_phy")
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# SATA -------------------------------------------------------------------------------------
if with_sata:
from litex.build.generic_platform import Subsignal, Pins
from litesata.phy import LiteSATAPHY
# IOs
_sata_io = [
# SFP 2 SATA Adapter / https://shop.trenz-electronic.de/en/TE0424-01-SFP-2-SATA-Adapter
(
"sfp2sata",
0,
Subsignal("tx_p", Pins("H2")),
Subsignal("tx_n", Pins("H1")),
Subsignal("rx_p", Pins("G4")),
Subsignal("rx_n", Pins("G3")),
),
]
platform.add_extension(_sata_io)
# RefClk, Generate 150MHz from PLL.
self.clock_domains.cd_sata_refclk = ClockDomain()
self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6)
sata_refclk = ClockSignal("sata_refclk")
platform.add_platform_command(
"set_property SEVERITY {{Warning}} [get_drc_checks REQP-52]")
# PHY
self.submodules.sata_phy = LiteSATAPHY(
platform.device,
refclk=sata_refclk,
pads=platform.request("sfp2sata"),
gen="gen2",
clk_freq=sys_clk_freq,
data_width=16)
self.add_csr("sata_phy")
# Core
self.add_sata(phy=self.sata_phy, mode="read+write")
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
