def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Tagus")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--with-pcie",
action="store_true",
help="Enable PCIe support")
parser.add_argument("--driver",
action="store_true",
help="Generate LitePCIe driver")
parser.add_argument("--load", action="store_true", help="Load bitstream")
builder_args(parser)
soc_sdram_args(parser)
args = parser.parse_args()
# Enforce arguments
args.csr_data_width = 32
platform = tagus.Platform()
soc = BaseSoC(platform,
with_pcie=args.with_pcie,
**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.driver:
generate_litepcie_software(soc,
os.path.join(builder.output_dir, "driver"))
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main():
platform = tagus.Platform()
soc = TagusSoC(platform)
builder = Builder(soc, output_dir="../build/tagus", csr_csv="../build/tagus/csr.csv",
compile_gateware=not "no-compile" in sys.argv[1:])
vns = builder.build(build_name="tagus")
soc.generate_software_header("../software/kernel/csr.h")
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Tagus")
builder_args(parser)
soc_sdram_args(parser)
args = parser.parse_args()
args.uart_name = "crossover"
args.csr_data_width = 32
platform = tagus.Platform()
soc = PCIeSoC(platform, **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
vns = builder.build()
soc.generate_software_header("csr.h")
def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, **kwargs):
platform = tagus.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Tagus",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq,
iodelay_clk_freq=200e6)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41J128M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
self.submodules.pcie_phy = S7PCIEPHY(platform,
platform.request("pcie_x1"),
data_width=128,
bar0_size=0x20000)
self.add_csr("pcie_phy")
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Tagus")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
builder_args(parser)
soc_sdram_args(parser)
args = parser.parse_args()
# Enforce arguments
args.uart_name = "crossover"
args.csr_data_width = 32
platform = tagus.Platform()
soc = PCIeSoC(platform, **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
vns = builder.build(run=args.build)
soc.generate_software_headers()
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit"))