from pymtl import *
from lizard.config.general import *
from lizard.bitutil import clog2, bit_enum
from lizard.bitutil.bit_struct_generator import *
from lizard.msg.codes import RVInstMask
PipelineMsgStatus = bit_enum(
'PipelineMsgStatus',
None,
('PIPELINE_MSG_STATUS_VALID', 'va'),
('PIPELINE_MSG_STATUS_EXCEPTION_RAISED', 'ex'),
('PIPELINE_MSG_STATUS_INTERRUPTED', 'it'),
('PIPELINE_MSG_STATUS_TRAPPED', 'tr'),
)
OpClass = bit_enum(
'OpClass',
None,
('OP_CLASS_ALU', 'in'),
('OP_CLASS_MUL', 'md'),
('OP_CLASS_BRANCH', 'br'),
('OP_CLASS_JUMP', 'jp'),
('OP_CLASS_CSR', 'cs'),
('OP_CLASS_SYSTEM', 'sy'),
('OP_CLASS_MEM', 'me'),
)
AluFunc = bit_enum(
'AluFunc',
None,
('ALU_FUNC_ADD', 'ad'),
from pymtl import *
from lizard.bitutil import clog2, bit_enum
from lizard.config.mem import *
from lizard.config.general import *
MemMsgType = bit_enum(
'MemMsgType',
None,
('READ', 'rd'),
('WRITE', 'wr'),
('WRITE_INIT', 'in'),
('AMO_ADD', 'ad'),
('AMO_AND', 'an'),
('AMO_OR', 'or'),
('AMO_XCHG', 'xg'),
('AMO_MIN', 'mn'),
('AMO_MAX', 'mx'),
)
MemMsgStatus = bit_enum(
'MemMsgStatus',
None,
('OK', 'ok'),
('ADDRESS_MISALIGNED', 'ma'),
('ACCESS_FAULT', 'fa'),
)
#-------------------------------------------------------------------------
# MemReqMsg
#-------------------------------------------------------------------------
RV64Inst = bit_enum(
'RV64Inst',
None,
# RV64G instructions (RISC-V Spec, chapter 19, pages 104-108)
# RV32I Base Instruction Set
'LUI',
'AUIPC',
'JAL',
'JALR',
'BEQ',
'BNE',
'BLT',
'BGE',
'BLTU',
'BGEU',
'LB',
'LH',
'LW',
'LBU',
'LHU',
'SB',
'SH',
'SW',
'ADDI',
'SLTI',
'SLTIU',
'XORI',
'ORI',
'ANDI',
'SLLI',
'SRLI',
'SRAI',
'ADD',
'SUB',
'SLL',
'SLT',
'SLTU',
'XOR',
'SRL',
'SRA',
'OR',
'AND',
'FENCE',
'FENCE_I',
'ECALL',
'EBREAK',
'CSRRW',
'CSRRS',
'CSRRC',
'CSRRWI',
'CSRRSI',
'CSRRCI',
# RV64I Base Instruction Set (in addition to RV32I)
'LWU',
'LD',
'SD',
'SLLI',
'SRLI',
'SRAI',
'ADDIW',
'SLLIW',
'SRLIW',
'SRAIW',
'ADDW',
'SUBW',
'SLLW',
'SRLW',
'SRAW',
# RV32M Standard Extension
'MUL',
'MULH',
'MULHSU',
'MULHU',
'DIV',
'DIVU',
'REM',
'REMU',
# RV64M Standard Extension (in addition to RV32M)
'MULW',
'DIVW',
'DIVUW',
'REMW',
'REMUW',
# RV32A Standard Extension
'LR.W',
'SC.W',
'AMOSWAP.W',
'AMOADD.W',
'AMOXOR.W',
'AMOAND.W',
'AMOOR.W',
'AMOMIN.W',
'AMOMAX.W',
'AMOMINU.W',
'AMOMAXU.W',
# RV64A Standard Extension (in addition to RV32A)
'LR.D',
'SC.D',
'AMOSWAP.D',
'AMOADD.D',
'AMOXOR.D',
'AMOAND.D',
'AMOOR.D',
'AMOMIN.D',
'AMOMAX.D',
'AMOMINU.D',
'AMOMAXU.D',
# RV32F Standard Extension
'FLW',
'FSW',
'FMADD.S',
'FMSUB.S',
'FNMSUB.S',
'FNMADD.S',
'FADD.S',
'FSUB.S',
'FMUL.S',
'FDIV.S',
'FSQRT.S',
'FSGNJ.S',
'FSGNJN.S',
'FSGNJX.S',
'FMIN.S',
'FMAX.S',
'FCVT.W.S',
'FCVT.WU.S',
'FMV.X.W',
'FEQ.S',
'FLT.S',
'FLE.S',
'FCLASS.S',
'FCVT.S.W',
'FCVT.S.WU',
'FMV.W.X',
# RV64F Standard Extension (in addition to RV32F)
'FCVT.L.S',
'FCVT.LU.S',
'FCVT.S.L',
'FCVT.S.LU',
# RV32D Standard Extension
'FLD',
'FSD',
'FMADD.D',
'FMSUB.D',
'FNMSUB.D',
'FNMADD.D',
'FADD.D',
'FSUB.D',
'FMUL.D',
'FDIV.D',
'FSQRT.D',
'FSGNJ.D',
'FSGNJN.D',
'FSGNJX.D',
'FMIN.D',
'FMAX.D',
'FCVT.S.D',
'FCVT.D.S',
'FEQ.D',
'FLT.D',
'FLE.D',
'FCLASS.D',
'FCVT.W.D',
'FCVT.WU.D',
'FCVT.D.W',
'FCVT.D.WU',
# RV64D Standard Extension (in addition to RV32D)
'FCVT.L.D',
'FCVT.LU.D',
'FMV.X.D',
'FCVT.D.L',
'FCVT.D.LU',
'FMV.D.X',
)
from pymtl import *
from lizard.config.general import *
from lizard.msg.codes import *
from lizard.bitutil import bit_enum
PacketStatus = bit_enum(
'PacketStatus',
None,
'ALIVE',
'SQUASHED',
'EXCEPTION_TRIGGERED',
'TRAP_TRIGGERED',
'INTERRUPT_TRIGGERED',
)
def valid_name(name):
return '%s_valid' % name
def FieldValidPair(target, name, width):
setattr(target, name, BitField(width))
setattr(target, valid_name(name), BitField(1))
def copy_field_valid_pair(src, dst, name):
setattr(dst, name, getattr(src, name))
setattr(dst, valid_name(name), getattr(src, valid_name(name)))
def add_base(s):
from pymtl import *
from lizard.bitutil import clog2, bit_enum
from lizard.util.rtl.method import MethodSpec
from lizard.util.rtl.interface import Interface, UseInterface
CMPFunc = bit_enum(
'ALUFunc',
None,
'CMP_EQ',
'CMP_NE',
'CMP_LT',
'CMP_GE',
)
class ComparatorInterface(Interface):
def __init__(s, xlen):
s.Xlen = xlen
super(ComparatorInterface, s).__init__([
MethodSpec(
'exec',
args={
'func': CMPFunc.bits,
'src0': Bits(xlen),
'src1': Bits(xlen),
'unsigned': Bits(1),
},
rets={
'res': Bits(1),
},
call=True,
from pymtl import *
from lizard.util.rtl.interface import Interface, UseInterface
from lizard.util.rtl.method import MethodSpec
from lizard.bitutil import bit_enum
from lizard.util.rtl.mux import Mux
from lizard.core.rtl.messages import InstMsg
ImmType = bit_enum(
'ImmType',
None,
('IMM_TYPE_I', 'i'),
('IMM_TYPE_S', 's'),
('IMM_TYPE_B', 'b'),
('IMM_TYPE_U', 'u'),
('IMM_TYPE_J', 'j'),
('IMM_TYPE_C', 'c'),
('IMM_TYPE_SHAMT32', 's3'),
('IMM_TYPE_SHAMT64', 's6'),
)
class ImmDecoderInterface(Interface):
def __init__(s, decoded_length):
s.decoded_length = decoded_length
super(ImmDecoderInterface, s).__init__([
MethodSpec(
'decode',
args={
'inst': InstMsg(),
from pymtl import *
from lizard.bitutil import clog2, bit_enum
from lizard.util.rtl.method import MethodSpec
from lizard.util.rtl.interface import Interface, UseInterface
ALUFunc = bit_enum('ALUFunc', None, 'ALU_ADD', 'ALU_SUB', 'ALU_AND', 'ALU_OR',
'ALU_XOR', 'ALU_SLL', 'ALU_SRL', 'ALU_SRA', 'ALU_SLT')
class ALUInterface(Interface):
def __init__(s, xlen):
s.Xlen = xlen
super(ALUInterface, s).__init__([
MethodSpec(
'exec',
args={
'func': ALUFunc.bits,
'src0': Bits(xlen),
'src1': Bits(xlen),
'unsigned': Bits(1),
},
rets={
'res': xlen,
},
call=True,
rdy=True,
),
])
class ALU(Model):