###############################################################################
print "\n/////////////////////////////////////"
print "// LTC2512 Trace Filter Shape Demo //"
print "/////////////////////////////////////"
raw_input("\nPlease set jumper 10 and 11 to 1, \nthen hit enter")
# Get the host from the command line argument. Can be numeric or hostname.
HOST = sys.argv[1] if len(sys.argv) == 2 else '127.0.0.1'
print '\nStarting client'
client = MemClient(host=HOST)
#Read FPGA type and revision
rev_id = client.reg_read(REV_ID_BASE)
type_id = rev_id & 0x0000FFFF
rev = (rev_id >> 16) & 0x0000FFFF
print 'FPGA load type ID: %04X' % type_id
print 'FPGA load revision: %04X' % rev
start_time = time.time()
print("Setting up system parameters.\n")
client.reg_write(SYSTEM_CLOCK_BASE,
((LUT_NCO_DIVIDER << 16) | SYSTEM_CLOCK_DIVIDER))
client.reg_write(NUM_SAMPLES_BASE, NUM_SAMPLES)
LTC6954_configure(client)
# Set Mux for filtered data
for i in range(0, num_mem_writes):
mem_values.append(i * 2)
i2c_output_base_reg = 0x120
i2c_input_base_reg = 0x140
print("Testing reg_write")
print 'Writing 0x%X to register 0x%X...' % (reg_value, reg_address)
written_address = client.reg_write(reg_address, reg_value, dummy)
if (written_address != reg_address):
print 'ERROR in Register Write. Returned wrong address.'
print("Testing reg_read")
print 'Reading back register 0x%X...' % reg_address
reg_value_read = client.reg_read(reg_address, dummy)
print 'Value at register 0x%X: 0x%X' % (reg_address, reg_value_read)
if (reg_value_read != reg_value):
print 'ERROR in Register Read. Returned wrong value.'
print("** Tested Reg read and write. **\n")
print("Testing reg write block")
print 'Writing block of %d values to register location 0x%X...' % (
num_reg_writes, reg_address)
last_location = client.reg_write_block(reg_address, num_reg_writes, reg_values,
dummy)
print 'Last location written into: 0x%X' % last_location
if (last_location != (reg_address + (num_reg_writes - 1) * 4)):
print 'ERROR in Reg Write Block. Returned wrong last location'
# If you're running this script ON the sockit board itself, you would run:
# python DC2390_hello_world.py
# Now we create an instance of MemClient, called "client", pointing it at
# the SoCkit's IP address. This is the "pipeline" that allows us to communicate.
print('Starting client')
client = MemClient(host=HOST)
# First thing's First!! Unfortunately we can't even blink a light without first
# Configuring the clocks, which are provided from a crystal oscillator and
# LTC6954 clock distribution divider / driver
LTC6954_configure(client)
#Read FPGA type and revision
rev_id = client.reg_read(REV_ID_BASE)
type_id = rev_id & 0x0000FFFF
rev = (rev_id >> 16) & 0x0000FFFF
print ('FPGA load type ID: %04X' % type_id)
print ('FPGA load revision: %04X' % rev)
LUT_DIVIDER = 0xC000 # Let's start with half-depth...
SYSTEM_CLOCK_DIVIDER = 1250
fb_gain = 0x5000
echo_gain = 0x7FF0
#fb_factor = 0xC000 #-4000
print("Setting up datapath...\n");
client.reg_write(SYSTEM_CLOCK_BASE, ((LUT_DIVIDER << 16) | SYSTEM_CLOCK_DIVIDER))
filt = DC2390.LTC2500_SINC_FILT
df = DC2390.LTC2500_DF_2048
# Keep track of start time
start_time = time.time()
# Get the host from the command line argument. Can be numeric or hostname.
HOST = sys.argv[1] if len(sys.argv) == 2 else '127.0.0.1'
# Connect to the SoC
client = MemClient(host=HOST)
# Verify the FPGA bistream
#--------------------------------------------------------------------------
#Read FPGA type and revision
rev_id = client.reg_read(DC2390.REV_ID_BASE)
type_id = rev_id & 0x0000FFFF
rev = (rev_id >> 16) & 0x0000FFFF
if (type_id != 0xABCD) or (rev != 0x1238):
print "Wrong FPGA bitstream on the FPGA"
print 'FPGA load type ID: %04X' % type_id
print 'FPGA load revision: %04X' % rev
else:
print "Correct bitstream file found !!"
# Initialize the FPGA
#--------------------------------------------------------------------------
print("Setting up system parameters.\n")
# Set the LTC695 to 50 MHz
print("Tuning Word:" + str(tuning_word))
print('Starting client')
client = MemClient(host=HOST)
#First thing's First!! Configure clocks...
LTC6954_configure(client)
#Check FPGA type and revision
type_rev_check(client, 0xABCD, 0x1246)
print("Setting up system parameters.\n")
client.reg_write(SYSTEM_CLOCK_BASE, SYSTEM_CLOCK_DIVIDER)
client.reg_write(SYSTEM_CLOCK_BASE,
(LUT_NCO_DIVIDER << 16 | SYSTEM_CLOCK_DIVIDER))
client.reg_write(NUM_SAMPLES_BASE, NUM_SAMPLES)
pll_locked = client.reg_read(DATA_READY_BASE) # Check data ready signal
if ((pll_locked & 0x02) == 0x02):
print("PLL is LOCKED!")
else:
print("PLL is NOT locked, check power to DC2390")
#datapath fields: lut_addr_select, dac_a_select, dac_b_select[1:0], fifo_data_select
#lut addresses: 0=lut_addr_counter, 1=dac_a_data_signed, 2=0x4000, 3=0xC000
# DAC A:
# .data0x ( nco_sin_out ),
# .data1x ( pid_output ),
# .data2x ( 16'h4000 ),
# .data3x ( 16'hC000 ),
# DAC B:
# .data0x ( nco_cos_out ),
# .data1x ( lut_output ),