else: vbias = args.hvBias frameInterval = 16 pulseLow = True else: print "Unkown mode!" exit(1) if vbias > 50: minEventsA *= 10 if vbias > 50: minEventsB *= 10 rootFile = ROOT.TFile(rootFileName, "RECREATE"); uut = atb.ATB("/tmp/d.sock", False, F=1/T) uut.config = loadLocalConfig(useBaseline=False) uut.initialize() rootData1 = DataFile( rootFile, "3") rootData2 = DataFile( rootFile, "3B") if args.asics == None: activeAsics = uut.getActiveTOFPETAsics() else: activeAsics= args.asics activeChannels = [ x for x in range(0,64) ] systemAsics = [ i for i in range(max(activeAsics) + 1) ]
if args.cWindow == None: cWindow = 0 else: cWindow = args.cWindow if args.minToT == None: minTOT = 0 else: minToT = args.minToT acquisitionTime = args.acqTime dataFilePrefix = args.OutputFilePrefix uut = atb.ATB("/tmp/d.sock", False, F=1/T) uut.config = loadLocalConfig() uut.openAcquisition(dataFilePrefix, cWindow*1E-9, minToT*1E-9, writer="TOFPET") uut.initialize() uut.config.writeParams(dataFilePrefix) # Set all HV DAC channels uut.setAllHVDAC(67.50) for step1 in [0]: for step2 in [0]: # Actually upload config into hardware uut.uploadConfig() uut.doSync() print "Acquiring step %d %d..." % (step1, step2) uut.acquire(step1, step2, acquisitionTime)
if args.cWindow == None: cWindow = 0 else: cWindow = args.cWindow if args.minToT == None: minTOT = 0 else: minToT = args.minToT acquisitionTime = args.acqTime dataFilePrefix = args.OutputFilePrefix uut = atb.ATB("/tmp/d.sock", False, F=1 / T) uut.config = loadLocalConfig() uut.openAcquisition(dataFilePrefix, cWindow * 1E-9, minToT * 1E-9, writer="TOFPET") uut.initialize() uut.config.writeParams(dataFilePrefix) # Set all HV DAC channels uut.setAllHVDAC(67.50) for step1 in [0]: for step2 in [0]: # Actually upload config into hardware uut.uploadConfig() uut.doSync() print "Acquiring step %d %d..." % (step1, step2)
T = 6.25E-9 root_file = args.OutputFile + ".root" n_iter = args.nIter dir_path = os.path.dirname(root_file) basename = os.path.basename(root_file) os.system("mkdir -p %s/pdf" % dir_path) base_prefix, base_ext = splitext(basename) prefix, ext = splitext(root_file) log_filename = "%s.log" % prefix log_f = open(log_filename, 'w+') atbConfig = loadLocalConfig(useBaseline=False) uut = atb.ATB("/tmp/d.sock", False, F=1 / T) uut.config = atbConfig uut.initialize() if args.asics == None: activeAsics = uut.getActiveTOFPETAsics() else: activeAsics = args.asics maxAsics = max(activeAsics) + 1 systemAsics = [i for i in range(maxAsics)] targetChannels = [(x, y) for x in activeAsics for y in range(64)] postamp = [0 for i in range(maxAsics)]
# -*- coding: utf-8 -*- import argparse import atb from loadLocalConfig import loadLocalConfig parser = argparse.ArgumentParser( description='Set all active HV DACs to the same voltage') parser.add_argument('ReqVoltage', type=float, help='The requested voltage in Volts ') args = parser.parse_args() uut = atb.ATB("/tmp/d.sock") uut.config = loadLocalConfig(useBaseline=False) uut.setAllHVDAC(args.ReqVoltage)